Pub Date : 2024-07-12DOI: 10.1109/TVLSI.2024.3423341
Yu-Cheng Lin;Ren-Hao Chiou;Chia-Hsiang Yang
In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to $16 times $ MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) $= 10^{-4}$ are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the $16 times $ MU-MIMO configuration.
{"title":"A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems","authors":"Yu-Cheng Lin;Ren-Hao Chiou;Chia-Hsiang Yang","doi":"10.1109/TVLSI.2024.3423341","DOIUrl":"10.1109/TVLSI.2024.3423341","url":null,"abstract":"In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to \u0000<inline-formula> <tex-math>$16 times $ </tex-math></inline-formula>\u0000 MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) \u0000<inline-formula> <tex-math>$= 10^{-4}$ </tex-math></inline-formula>\u0000 are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the \u0000<inline-formula> <tex-math>$16 times $ </tex-math></inline-formula>\u0000 MU-MIMO configuration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141612038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-12DOI: 10.1109/TVLSI.2024.3417385
Yu Lu;Xiaowu Cai;Jian Lu;Longli Pan;Jianying Dang;Yafei Xie;Xupeng Wang;Bo Li
In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.
在具有多个功率域的数字集成电路中，电平转换器（LS）是将电压区域从低电平转换到高电平的重要电路元件。然而，高频栅极驱动器每纳秒可产生数百个电压噪声（高 dV/dt 噪声）。这种高 dV/dt 噪声会导致用于控制高压侧 nMOS 开关的传统脉冲触发交叉耦合 LS（CCLS）出现故障。本文提出并研究了一种具有抗噪能力的新型 LS。与传统的电阻负载 LS 相比，所提出的电路采用了 nMOS-R 交叉耦合 (NRCC) LS，并通过利用滤除 dV/dt 引入的噪声的路径实现了选择性滤波能力。高压栅极驱动集成电路（HVIC）采用 600 V 硅绝缘体（SOI）BCD 工艺实现。分析和实验表明，所提出的设计可帮助 HVIC 保持高达 137 V/ns 的高共模瞬态抗扰度 (CMTI)，同时允许在 15 V 电源电压下实现低至 -9.4 V 的负 VS 摆幅。与采用电阻负载 LS 的传统 HVIC 相比，采用 NRCC LS 的新型 HVIC 将 dV/dt 的抗噪能力提高了 182%。
{"title":"A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity for 600-V High-Voltage Gate Driver IC","authors":"Yu Lu;Xiaowu Cai;Jian Lu;Longli Pan;Jianying Dang;Yafei Xie;Xupeng Wang;Bo Li","doi":"10.1109/TVLSI.2024.3417385","DOIUrl":"10.1109/TVLSI.2024.3417385","url":null,"abstract":"In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141612039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-11DOI: 10.1109/TVLSI.2024.3422501
Thockchom Birjit Singha;Basa Sanjana;Titu Mary Ignatius;Roy Paily Palathinkal;Shaik Rafi Ahamed
Advanced encryption standard (AES) is used to secure the communication process on the Internet-of-Things (IoT) hardware. It is implementable in various 128-bit modes, such as electronic code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR), to facilitate parallel processing of data. The noninvasive nature of power analysis attacks (PAAs) to retrieve secret information off a physical device renders such hardware to be unsafe from the adversaries. Also, the assessment of the aforementioned modes for security remains obscured, which is undertaken by this work as a novel attempt. In addition, this work proposes a novel 64-bit version of CFB mode, which provides the highest security with respect to other modes and several unprotected AES designs. PAAs are performed on ASIC platform utilizing UMC 65-nm technology node and a hardware experimental setup using side-channel attack security evaluation board (SASEBO), both at 16-MHz AES frequency and traces sampled at the rate of 1 GSa/s. The measurements to disclose (MTDs) of >1 000 000 provided by the proposed CFB-64 are significantly more than that provided by usual unprotected AES designs. It also offers the highest MTD, and least signal-to-noise ratio (SNR) and mutual information (MI) among other modes, indicating the highest security. The proposed CFB-64 acts as a countermeasure upon integration with an unprotected AES.
{"title":"Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks","authors":"Thockchom Birjit Singha;Basa Sanjana;Titu Mary Ignatius;Roy Paily Palathinkal;Shaik Rafi Ahamed","doi":"10.1109/TVLSI.2024.3422501","DOIUrl":"10.1109/TVLSI.2024.3422501","url":null,"abstract":"Advanced encryption standard (AES) is used to secure the communication process on the Internet-of-Things (IoT) hardware. It is implementable in various 128-bit modes, such as electronic code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR), to facilitate parallel processing of data. The noninvasive nature of power analysis attacks (PAAs) to retrieve secret information off a physical device renders such hardware to be unsafe from the adversaries. Also, the assessment of the aforementioned modes for security remains obscured, which is undertaken by this work as a novel attempt. In addition, this work proposes a novel 64-bit version of CFB mode, which provides the highest security with respect to other modes and several unprotected AES designs. PAAs are performed on ASIC platform utilizing UMC 65-nm technology node and a hardware experimental setup using side-channel attack security evaluation board (SASEBO), both at 16-MHz AES frequency and traces sampled at the rate of 1 GSa/s. The measurements to disclose (MTDs) of >1 000 000 provided by the proposed CFB-64 are significantly more than that provided by usual unprotected AES designs. It also offers the highest MTD, and least signal-to-noise ratio (SNR) and mutual information (MI) among other modes, indicating the highest security. The proposed CFB-64 acts as a countermeasure upon integration with an unprotected AES.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141612040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-11DOI: 10.1109/TVLSI.2024.3422684
Huihong Shi;Xin Cheng;Wendong Mao;Zhongfeng Wang
Vision transformers (ViTs) have excelled in computer vision (CV) tasks but are memory-consuming and computation-intensive, challenging their deployment on resource-constrained devices. To tackle this limitation, prior works have explored ViT-tailored quantization algorithms but retained floating-point scaling factors, which yield nonnegligible requantization overhead, limiting ViTs’ hardware efficiency and motivating more hardware-friendly solutions. To this end, we propose P2-ViT, the first power-of-two (PoT) posttraining quantization (PTQ) and acceleration framework to accelerate fully quantized ViTs. Specifically, as for quantization, we explore a dedicated quantization scheme to effectively quantize ViTs with PoT scaling factors, thus minimizing the requantization overhead. Furthermore, we propose coarse-to-fine automatic mixed-precision quantization to enable better accuracy-efficiency tradeoffs. In terms of hardware, we develop a dedicated chunk-based accelerator featuring multiple tailored subprocessors to individually handle ViTs’ different types of operations, alleviating reconfigurable overhead. In addition, we design a tailored row-stationary dataflow to seize the pipeline processing opportunity introduced by our PoT scaling factors, thereby enhancing throughput. Extensive experiments consistently validate P2-ViT’s effectiveness. Particularly, we offer comparable or even superior quantization performance with PoT scaling factors when compared with the counterpart with floating-point scaling factors. Besides, we achieve up to $10.1times $ speedup and $36.8times $ energy saving over GPU’s Turing Tensor Cores, and up to $1.84times $ higher computation utilization efficiency against SOTA quantization-based ViT accelerators. Codes are available at https://github.com/shihuihong214/P2-ViT .
视觉变换器（ViT）在计算机视觉（CV）任务中表现出色，但其内存消耗大、计算密集，这对在资源受限的设备上部署视觉变换器提出了挑战。为解决这一限制，之前的工作探索了针对 ViT 的量化算法，但保留了浮点缩放因子，这产生了不可忽略的重新量化开销，限制了 ViT 的硬件效率，并激发了对硬件更友好的解决方案。为此，我们提出了 P2-ViT，这是首个二幂（PoT）训练后量化（PTQ）和加速框架，用于加速完全量化的 ViT。具体来说，在量化方面，我们探索了一种专用量化方案，以有效量化具有 PoT 缩放因子的 ViT，从而最大限度地减少重新量化开销。此外，我们还提出了从粗到细的自动混合精度量化方案，以实现更好的精度-效率权衡。在硬件方面，我们开发了一种基于分块的专用加速器，具有多个定制的子处理器，可单独处理 ViTs 不同类型的操作，从而减轻了可重新配置的开销。此外，我们还设计了量身定制的行静态数据流，以抓住 PoT 扩展因子带来的流水线处理机会，从而提高吞吐量。大量实验不断验证 P2-ViT 的有效性。特别是，与使用浮点缩放因子的对应方案相比，我们使用 PoT 缩放因子提供了相当甚至更优越的量化性能。此外，与GPU的图灵张量核相比，我们实现了高达10.1倍的提速和36.8倍的节能，与基于SOTA量化的ViT加速器相比，我们实现了高达1.84倍的计算利用效率。代码见 https://github.com/shihuihong214/P2-ViT。
{"title":"P2-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer","authors":"Huihong Shi;Xin Cheng;Wendong Mao;Zhongfeng Wang","doi":"10.1109/TVLSI.2024.3422684","DOIUrl":"10.1109/TVLSI.2024.3422684","url":null,"abstract":"Vision transformers (ViTs) have excelled in computer vision (CV) tasks but are memory-consuming and computation-intensive, challenging their deployment on resource-constrained devices. To tackle this limitation, prior works have explored ViT-tailored quantization algorithms but retained floating-point scaling factors, which yield nonnegligible requantization overhead, limiting ViTs’ hardware efficiency and motivating more hardware-friendly solutions. To this end, we propose P2-ViT, the first power-of-two (PoT) posttraining quantization (PTQ) and acceleration framework to accelerate fully quantized ViTs. Specifically, as for quantization, we explore a dedicated quantization scheme to effectively quantize ViTs with PoT scaling factors, thus minimizing the requantization overhead. Furthermore, we propose coarse-to-fine automatic mixed-precision quantization to enable better accuracy-efficiency tradeoffs. In terms of hardware, we develop a dedicated chunk-based accelerator featuring multiple tailored subprocessors to individually handle ViTs’ different types of operations, alleviating reconfigurable overhead. In addition, we design a tailored row-stationary dataflow to seize the pipeline processing opportunity introduced by our PoT scaling factors, thereby enhancing throughput. Extensive experiments consistently validate P2-ViT’s effectiveness. Particularly, we offer comparable or even superior quantization performance with PoT scaling factors when compared with the counterpart with floating-point scaling factors. Besides, we achieve up to \u0000<inline-formula> <tex-math>$10.1times $ </tex-math></inline-formula>\u0000 speedup and \u0000<inline-formula> <tex-math>$36.8times $ </tex-math></inline-formula>\u0000 energy saving over GPU’s Turing Tensor Cores, and up to \u0000<inline-formula> <tex-math>$1.84times $ </tex-math></inline-formula>\u0000 higher computation utilization efficiency against SOTA quantization-based ViT accelerators. Codes are available at \u0000<uri>https://github.com/shihuihong214/P2-ViT</uri>\u0000.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141612041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-10DOI: 10.1109/TVLSI.2024.3417016
Samuel Coulon;Tianyou Bao;Jiafeng Xie
The extended greatest common divisor (XGCD) computation is a critical component in various cryptographic applications and algorithms, including both pre- and postquantum cryptosystems. In addition to computing the greatest common divisor (GCD) of two integers, the XGCD also produces Bézout coefficients $b_{a}$ and $b_{b}$ which satisfy $mathrm {GCD}(a,b) = atimes b_{a} + btimes b_{b}$ . In particular, computing the XGCD for large integers is of significant interest. Most recently, XGCD computation between 6479-bit integers is required for solving Nth-degree truncated polynomial ring unit (NTRU) trapdoors in Falcon, a National Institute of Standards and Technology (NIST)-selected postquantum digital signature scheme. To this point, existing literature has primarily focused on exploring software-based implementations for XGCD. The few existing high-performance hardware architectures require significant hardware resources and may not be desirable for practical usage, and the lightweight architectures suffer from poor performance. To fill the research gap, this work proposes a novel FPGA-based scalable and lightweight accelerator for large integer XGCD (FELIX). First, a new algorithm suitable for scalable and lightweight computation of XGCD is proposed. Next, a hardware accelerator (FELIX) is presented, including both constant- and variable-time versions. Finally, a thorough evaluation is carried out to showcase the efficiency of the proposed FELIX. In certain configurations, FELIX involves 81% less equivalent area-time product (eATP) than the state-of-the-art design for 1024-bit integers, and achieves a 95% reduction in latency over the software for 6479-bit integers (Falcon parameter set) with reasonable resource usage. Overall, the proposed FELIX is highly efficient, scalable, lightweight, and suitable for very large integer computation, making it the first such XGCD accelerator in the literature (to the best of our knowledge).
{"title":"FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD","authors":"Samuel Coulon;Tianyou Bao;Jiafeng Xie","doi":"10.1109/TVLSI.2024.3417016","DOIUrl":"10.1109/TVLSI.2024.3417016","url":null,"abstract":"The extended greatest common divisor (XGCD) computation is a critical component in various cryptographic applications and algorithms, including both pre- and postquantum cryptosystems. In addition to computing the greatest common divisor (GCD) of two integers, the XGCD also produces Bézout coefficients \u0000<inline-formula> <tex-math>$b_{a}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$b_{b}$ </tex-math></inline-formula>\u0000 which satisfy \u0000<inline-formula> <tex-math>$mathrm {GCD}(a,b) = atimes b_{a} + btimes b_{b}$ </tex-math></inline-formula>\u0000. In particular, computing the XGCD for large integers is of significant interest. Most recently, XGCD computation between 6479-bit integers is required for solving Nth-degree truncated polynomial ring unit (NTRU) trapdoors in Falcon, a National Institute of Standards and Technology (NIST)-selected postquantum digital signature scheme. To this point, existing literature has primarily focused on exploring software-based implementations for XGCD. The few existing high-performance hardware architectures require significant hardware resources and may not be desirable for practical usage, and the lightweight architectures suffer from poor performance. To fill the research gap, this work proposes a novel FPGA-based scalable and lightweight accelerator for large integer XGCD (FELIX). First, a new algorithm suitable for scalable and lightweight computation of XGCD is proposed. Next, a hardware accelerator (FELIX) is presented, including both constant- and variable-time versions. Finally, a thorough evaluation is carried out to showcase the efficiency of the proposed FELIX. In certain configurations, FELIX involves 81% less equivalent area-time product (eATP) than the state-of-the-art design for 1024-bit integers, and achieves a 95% reduction in latency over the software for 6479-bit integers (Falcon parameter set) with reasonable resource usage. Overall, the proposed FELIX is highly efficient, scalable, lightweight, and suitable for very large integer computation, making it the first such XGCD accelerator in the literature (to the best of our knowledge).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10593812","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141585201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-09DOI: 10.1109/TVLSI.2024.3422382
Chengzhi Xu;Xufeng Liao;Peiyuan Fu;Yongyuan Li;Lianxi Liu
In order to improve the efficiency over a wide load range, a power converter of the Internet of Things (IoT) usually works in dual modes, which are pulsewidth modulation (PWM) and pulse frequency modulation (PFM). A mixed load detection scheme is adopted to enable the appropriate modes under different loads, whose analog detector has an accurate detection in the heavy load, and the digital load detection improves the light-load efficiency. When the power converter operates in different modes, the control loops are different. Meanwhile, a seamless mode transition technique (SMTT) is presented in this article to improve the transient response during mode change between PWM and PFM. A test chip was fabricated in a 0.18- $mu $ m standard CMOS process, and the chip area is $1.59times 1.37$ mm2. The experimental results show that the efficiency is above 85.3% under $V_{text {IN}}=3.3$ V, $V_{text {OUT}}=1.8$ V, and in the load range from 1 to 300 mA, while peak efficiency can reach 96.1% at 100-mA load. Compared to the case without the proposed technique, the under/overshoot voltage can be reduced by above 55% during the mode transition.
{"title":"A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique","authors":"Chengzhi Xu;Xufeng Liao;Peiyuan Fu;Yongyuan Li;Lianxi Liu","doi":"10.1109/TVLSI.2024.3422382","DOIUrl":"10.1109/TVLSI.2024.3422382","url":null,"abstract":"In order to improve the efficiency over a wide load range, a power converter of the Internet of Things (IoT) usually works in dual modes, which are pulsewidth modulation (PWM) and pulse frequency modulation (PFM). A mixed load detection scheme is adopted to enable the appropriate modes under different loads, whose analog detector has an accurate detection in the heavy load, and the digital load detection improves the light-load efficiency. When the power converter operates in different modes, the control loops are different. Meanwhile, a seamless mode transition technique (SMTT) is presented in this article to improve the transient response during mode change between PWM and PFM. A test chip was fabricated in a 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m standard CMOS process, and the chip area is \u0000<inline-formula> <tex-math>$1.59times 1.37$ </tex-math></inline-formula>\u0000 mm2. The experimental results show that the efficiency is above 85.3% under \u0000<inline-formula> <tex-math>$V_{text {IN}}=3.3$ </tex-math></inline-formula>\u0000 V, \u0000<inline-formula> <tex-math>$V_{text {OUT}}=1.8$ </tex-math></inline-formula>\u0000 V, and in the load range from 1 to 300 mA, while peak efficiency can reach 96.1% at 100-mA load. Compared to the case without the proposed technique, the under/overshoot voltage can be reduced by above 55% during the mode transition.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141568489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least $15 min $ before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes $4.69~mu text { W}$ when implemented using SCL $180text {-nm}$ bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.
{"title":"A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices","authors":"Meenali Janveja;Rushik Parmar;Srichandan Dash;Jan Pidanic;Gaurav Trivedi","doi":"10.1109/TVLSI.2024.3413584","DOIUrl":"10.1109/TVLSI.2024.3413584","url":null,"abstract":"Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least \u0000<inline-formula> <tex-math>$15 min $ </tex-math></inline-formula>\u0000 before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes \u0000<inline-formula> <tex-math>$4.69~mu text { W}$ </tex-math></inline-formula>\u0000 when implemented using SCL \u0000<inline-formula> <tex-math>$180text {-nm}$ </tex-math></inline-formula>\u0000 bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141568490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-08DOI: 10.1109/TVLSI.2024.3421563
Hayoung Lee;Jongho Park;Sungho Kang
The increasing demand for data-intensive analytics, driven by the rapid advances in artificial intelligence (AI), has led to the proposal of various AI accelerators. However, as AI-based solutions are being applied to applications that require high accuracy and reliability, ensuring the dependability of these solutions has become a critical issue. In this brief, we present an area-efficient systolic array redundancy architecture for reliable AI accelerator. In the proposed architecture, computations assigned to faulty multiply-accumulate (MAC) units are bypassed using dedicated routes. Subsequently, the same computations are executed in shiftable redundant MACs or selectable redundant MACs. This ensures the correct completion of calculations all without performance reduction. Moreover, the reassignment of computations can be efficiently managed through a simple scheduling algorithm. As a result, the proposed architecture achieves a high repair rate through the redundant MACs and effective computation reassignment. Despite these capabilities, the proposed architecture incurs only a small area overhead.
在人工智能（AI）飞速发展的推动下，人们对数据密集型分析的需求日益增长，因此各种人工智能加速器应运而生。然而，由于基于人工智能的解决方案正被应用于需要高精度和高可靠性的应用中，确保这些解决方案的可靠性已成为一个关键问题。在本简介中，我们提出了一种用于可靠人工智能加速器的面积效率高的收缩阵列冗余架构。在所提出的架构中，分配给故障乘积（MAC）单元的计算将通过专用路由绕过。随后，相同的计算在可移位冗余 MAC 或可选择冗余 MAC 中执行。这样就能确保在不降低性能的情况下正确完成计算。此外，计算的重新分配可通过简单的调度算法进行有效管理。因此，拟议架构通过冗余 MAC 和有效的计算重新分配实现了高修复率。尽管具有这些功能，但所提出的架构只产生了很小的面积开销。
{"title":"An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator","authors":"Hayoung Lee;Jongho Park;Sungho Kang","doi":"10.1109/TVLSI.2024.3421563","DOIUrl":"10.1109/TVLSI.2024.3421563","url":null,"abstract":"The increasing demand for data-intensive analytics, driven by the rapid advances in artificial intelligence (AI), has led to the proposal of various AI accelerators. However, as AI-based solutions are being applied to applications that require high accuracy and reliability, ensuring the dependability of these solutions has become a critical issue. In this brief, we present an area-efficient systolic array redundancy architecture for reliable AI accelerator. In the proposed architecture, computations assigned to faulty multiply-accumulate (MAC) units are bypassed using dedicated routes. Subsequently, the same computations are executed in shiftable redundant MACs or selectable redundant MACs. This ensures the correct completion of calculations all without performance reduction. Moreover, the reassignment of computations can be efficiently managed through a simple scheduling algorithm. As a result, the proposed architecture achieves a high repair rate through the redundant MACs and effective computation reassignment. Despite these capabilities, the proposed architecture incurs only a small area overhead.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141568492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Elliptic curve scalar multiplication (ECSM) is a fundamental element of public key cryptography. The ECSM implementations on deeply embedded architectures and Internet-of-nano-Things have been vulnerable to both permanent and transient errors, as well as fault attacks. Consequently, error detection is crucial. In this work, we present a novel algorithm-level error detection scheme on Montgomery Ladder often used for a number of elliptic curves featuring highly efficient point arithmetic, known as Montgomery curves. Our error detection simulations achieve high error coverage on loop abort and scalar bit flipping fault model using binary tree data structure. Assuming n is the size of the private key, the overhead of our error detection scheme is $O(n)$ . Finally, we conduct a benchmark of our proposed error detection scheme on both ARMv8 and field-programmable gate array (FPGA) platforms to illustrate the implementation and resource utilization. Deployed on Cortex-A72 processors, our proposed error detection scheme maintains a clock cycle overhead of less than 5.2%. In addition, integrating our error detection approach into FPGAs, including AMD/Xilinx Zynq Ultrascale+ and Artix Ultrascale+, results in a comparable throughput and less than 2% increase in area compared with the original hardware implementation. We note that we envision using adoptions of the proposed architectures in the postquantum cryptography (PQC) based on elliptic curves.
{"title":"Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder","authors":"Kasra Ahmadi;Saeed Aghapour;Mehran Mozaffari Kermani;Reza Azarderakhsh","doi":"10.1109/TVLSI.2024.3419700","DOIUrl":"10.1109/TVLSI.2024.3419700","url":null,"abstract":"Elliptic curve scalar multiplication (ECSM) is a fundamental element of public key cryptography. The ECSM implementations on deeply embedded architectures and Internet-of-nano-Things have been vulnerable to both permanent and transient errors, as well as fault attacks. Consequently, error detection is crucial. In this work, we present a novel algorithm-level error detection scheme on Montgomery Ladder often used for a number of elliptic curves featuring highly efficient point arithmetic, known as Montgomery curves. Our error detection simulations achieve high error coverage on loop abort and scalar bit flipping fault model using binary tree data structure. Assuming n is the size of the private key, the overhead of our error detection scheme is \u0000<inline-formula> <tex-math>$O(n)$ </tex-math></inline-formula>\u0000. Finally, we conduct a benchmark of our proposed error detection scheme on both ARMv8 and field-programmable gate array (FPGA) platforms to illustrate the implementation and resource utilization. Deployed on Cortex-A72 processors, our proposed error detection scheme maintains a clock cycle overhead of less than 5.2%. In addition, integrating our error detection approach into FPGAs, including AMD/Xilinx Zynq Ultrascale+ and Artix Ultrascale+, results in a comparable throughput and less than 2% increase in area compared with the original hardware implementation. We note that we envision using adoptions of the proposed architectures in the postquantum cryptography (PQC) based on elliptic curves.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141568493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-05DOI: 10.1109/TVLSI.2024.3418713
Mizan Abraha Gebremicheal;Ibrahim M. Elfadel
The edge-coded signaling (ECS) protocol enables single-wire signaling in IoT devices and sensors using two important neuromorphic attributes. The first is the coding of bits as a stream of pulses (spikes), and the second is the circumvention of clock and data recovery (CDR) at the receiver. In addition, ECS can be endowed with strong, yet lightweight, security features using an ultralow-latency version of the A5/1 stream cipher. Such strong security comes at the expense of decreased data rates and significant area overhead. In this article, we introduce a new generation of secure ECS protocols that incorporates two notable improvements. The first is a more compact pulse stream definition that results in improved data rates for the plain ECS protocol. The second is a coding-aware version of the low-latency A5/1 stream cipher that results in minimal impact on the effective data rate of the transmission. Consequently, a new all-digital and secure ECS transceiver design is proposed, prototyped, and functionally verified in 65-nm technology. Compared with previous generations of secure ECS transceivers, this new design achieves an increase of approximately 138%, 199%, and 640% in minimum, average, and maximum data rates, respectively, and results in increased resiliency against brute-force attacks by a factor of 16. Furthermore, the ASIC implementation shows that it maintains the compact and energy-efficient features of the ECS architecture, using only $28~mu $ W with an average energy efficiency of 2.745 pJ/bit and a gate count of approximately 2880 gates. This is more than 40% decrease in the equivalent gate count relative to the previous secure ECS generation.
{"title":"Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead","authors":"Mizan Abraha Gebremicheal;Ibrahim M. Elfadel","doi":"10.1109/TVLSI.2024.3418713","DOIUrl":"10.1109/TVLSI.2024.3418713","url":null,"abstract":"The edge-coded signaling (ECS) protocol enables single-wire signaling in IoT devices and sensors using two important neuromorphic attributes. The first is the coding of bits as a stream of pulses (spikes), and the second is the circumvention of clock and data recovery (CDR) at the receiver. In addition, ECS can be endowed with strong, yet lightweight, security features using an ultralow-latency version of the A5/1 stream cipher. Such strong security comes at the expense of decreased data rates and significant area overhead. In this article, we introduce a new generation of secure ECS protocols that incorporates two notable improvements. The first is a more compact pulse stream definition that results in improved data rates for the plain ECS protocol. The second is a coding-aware version of the low-latency A5/1 stream cipher that results in minimal impact on the effective data rate of the transmission. Consequently, a new all-digital and secure ECS transceiver design is proposed, prototyped, and functionally verified in 65-nm technology. Compared with previous generations of secure ECS transceivers, this new design achieves an increase of approximately 138%, 199%, and 640% in minimum, average, and maximum data rates, respectively, and results in increased resiliency against brute-force attacks by a factor of 16. Furthermore, the ASIC implementation shows that it maintains the compact and energy-efficient features of the ECS architecture, using only \u0000<inline-formula> <tex-math>$28~mu $ </tex-math></inline-formula>\u0000W with an average energy efficiency of 2.745 pJ/bit and a gate count of approximately 2880 gates. This is more than 40% decrease in the equivalent gate count relative to the previous secure ECS generation.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141568491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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