Static random access memory (SRAM) plays a critical role in chips due to its high-speed access capabilities, but it suffers from data loss upon power-down and is susceptible to radiation-induced faults. Nonvolatile SRAM (NVSRAM) has attracted substantial research attention for combining the high-speed operation of SRAM with the nonvolatile storage capabilities of emerging memory technologies. This article proposes a 12T2R NVSRAM cell based on resistive random access memory (RRAM), achieving nanosecond-scale data backup and recovery. The novel design integrates an independent RRAM operation path and an SRAM power-gating switch, ensuring reliable backup and low-power sleep mode. Building on the memory array, the system further integrates a power management module, control and driver circuitry, and a dual-layer error correction code (ECC) strategy. This holistic co-design across device, circuit, and architecture levels delivers enhanced reliability, energy efficiency, and fault tolerance. Simulation results under 65 nm CMOS process demonstrate significant improvements in key performance metrics, including speed, power consumption, noise margin, store/restore yield, and bit error rate (BER). All functional modules meet the design specifications, with markedly improved data backup and restoration success rates, providing a promising solution for next-generation high-performance nonvolatile memory (NVM) systems.
{"title":"A Highly Reliable RRAM-Based 12T2R NVSRAM Architecture With Dual-Layer ECC","authors":"Huimeng Guo;Yujia Li;Yiqing Li;Tingrui Ren;Liang Wang;Yuanfu Zhao","doi":"10.1109/TVLSI.2025.3619392","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3619392","url":null,"abstract":"Static random access memory (SRAM) plays a critical role in chips due to its high-speed access capabilities, but it suffers from data loss upon power-down and is susceptible to radiation-induced faults. Nonvolatile SRAM (NVSRAM) has attracted substantial research attention for combining the high-speed operation of SRAM with the nonvolatile storage capabilities of emerging memory technologies. This article proposes a 12T2R NVSRAM cell based on resistive random access memory (RRAM), achieving nanosecond-scale data backup and recovery. The novel design integrates an independent RRAM operation path and an SRAM power-gating switch, ensuring reliable backup and low-power sleep mode. Building on the memory array, the system further integrates a power management module, control and driver circuitry, and a dual-layer error correction code (ECC) strategy. This holistic co-design across device, circuit, and architecture levels delivers enhanced reliability, energy efficiency, and fault tolerance. Simulation results under 65 nm CMOS process demonstrate significant improvements in key performance metrics, including speed, power consumption, noise margin, store/restore yield, and bit error rate (BER). All functional modules meet the design specifications, with markedly improved data backup and restoration success rates, providing a promising solution for next-generation high-performance nonvolatile memory (NVM) systems.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"294-306"},"PeriodicalIF":3.1,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1109/TVLSI.2025.3621655
Pavankumar Ganjimala;Subrahmanyam Mula
The Hammerstein spline adaptive filter (HSAF) is a class of nonlinear adaptive filters (NAFs), known for its flexible nonlinear modeling and low complexity in applications, such as self-interference cancellation in wireless communications. This brief proposes a delayed dual-weight update reformulation for the HSAF and its efficient high-throughput and low-power architecture. We also propose hardware-efficient techniques for mapping spline interpolation and updating the spline control points in HSAF. The proposed delayed HSAF (DHSAF) architecture is synthesized using Cadence Genus in 45-nm CMOS technology. Synthesis results show that the proposed DHSAF achieves significantly higher throughput compared to the basic HSAF, with only minimal area and power overhead. Furthermore, the proposed DHSAF outperforms the state-of-the-art RFF-KLMS architecture in terms of both area and power efficiency.
{"title":"An Efficient VLSI Architecture for Hammerstein-Type Spline Adaptive Filters","authors":"Pavankumar Ganjimala;Subrahmanyam Mula","doi":"10.1109/TVLSI.2025.3621655","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3621655","url":null,"abstract":"The Hammerstein spline adaptive filter (HSAF) is a class of nonlinear adaptive filters (NAFs), known for its flexible nonlinear modeling and low complexity in applications, such as self-interference cancellation in wireless communications. This brief proposes a delayed dual-weight update reformulation for the HSAF and its efficient high-throughput and low-power architecture. We also propose hardware-efficient techniques for mapping spline interpolation and updating the spline control points in HSAF. The proposed delayed HSAF (DHSAF) architecture is synthesized using Cadence Genus in 45-nm CMOS technology. Synthesis results show that the proposed DHSAF achieves significantly higher throughput compared to the basic HSAF, with only minimal area and power overhead. Furthermore, the proposed DHSAF outperforms the state-of-the-art RFF-KLMS architecture in terms of both area and power efficiency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 2","pages":"662-666"},"PeriodicalIF":3.1,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146015911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-07DOI: 10.1109/TVLSI.2025.3615468
Sunrui Zhang;Xiaole Cui;Feng Wei;Xing Zhang
Digital static random access memory-based in-memory computing (SRAM-IMC) is a promising computation paradigm to break the von-Neumann bottleneck. However, the IMC architectures also bring a series of challenges for testing, because of the circuit structures and operations that do not exist in the conventional memories. One of the challenges is the testing of evaluation circuits in the digital SRAM-IMC architectures, because the primary inputs (PIs) of the evaluation circuits cannot be directly accessed by the testers. Several test approaches such as the conventional logic built-in self-test (LBIST) modules, the indirect and the scan-chain-based test methods are proposed to address this issue. Nevertheless, these solutions suffer from the low test performance or the high area consumption. This work proposes a reconfigurable built-in self-test (BIST) scheme for the evaluation circuits. By reusing the IMC bitcells and operations, the proposed BIST scheme implements the separate pattern generation (PG) and response analysis (RA) processes. Furthermore, the diverse pattern generators, including the Fibonacci linear feedback shift register (LFSR) and weighted LFSR (WLFSR) with adjustable feedback polynomials and the cellular automata (CA), are realized to improve the test efficiency and fault coverage. The evaluation results show that the proposed BIST scheme has better test performance comparing with the indirect and the scan-chain-based test approaches. The proposed BIST scheme has comparable test performance, whereas it has much less area overhead comparing with the conventional LBIST schemes. Additionally, the proposed BIST scheme is testable and repairable.
{"title":"A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures","authors":"Sunrui Zhang;Xiaole Cui;Feng Wei;Xing Zhang","doi":"10.1109/TVLSI.2025.3615468","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3615468","url":null,"abstract":"Digital static random access memory-based in-memory computing (SRAM-IMC) is a promising computation paradigm to break the von-Neumann bottleneck. However, the IMC architectures also bring a series of challenges for testing, because of the circuit structures and operations that do not exist in the conventional memories. One of the challenges is the testing of evaluation circuits in the digital SRAM-IMC architectures, because the primary inputs (PIs) of the evaluation circuits cannot be directly accessed by the testers. Several test approaches such as the conventional logic built-in self-test (LBIST) modules, the indirect and the scan-chain-based test methods are proposed to address this issue. Nevertheless, these solutions suffer from the low test performance or the high area consumption. This work proposes a reconfigurable built-in self-test (BIST) scheme for the evaluation circuits. By reusing the IMC bitcells and operations, the proposed BIST scheme implements the separate pattern generation (PG) and response analysis (RA) processes. Furthermore, the diverse pattern generators, including the Fibonacci linear feedback shift register (LFSR) and weighted LFSR (WLFSR) with adjustable feedback polynomials and the cellular automata (CA), are realized to improve the test efficiency and fault coverage. The evaluation results show that the proposed BIST scheme has better test performance comparing with the indirect and the scan-chain-based test approaches. The proposed BIST scheme has comparable test performance, whereas it has much less area overhead comparing with the conventional LBIST schemes. Additionally, the proposed BIST scheme is testable and repairable.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"280-293"},"PeriodicalIF":3.1,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Soft errors and power dissipation emerge as critical challenges in developing high-reliability and cost-sensitive embedded systems. To address these issues, the magnetic tunnel junction (MTJ) is considered a promising solution due to its nonvolatility and its compatibility with traditional CMOS manufacturing processes. In this work, we propose a novel nonvolatile (NV) latch consisting of inverters and MTJs, namely, NVLIM, which provides nonvolatility and robust partial tolerance against triple-node-upsets (TNUs) at low cost. NVLIM integrates a TNU-tolerant block based on CMOS with a backup-restore block using MTJs. Simulation results incorporating process, voltage, and temperature (PVT) variations, bias temperature instability (BTI) impact, and Monte Carlo simulations demonstrate the balanced performance in terms of nonvolatility, robust partial TNU tolerance, and comprehensive overhead of the proposed latch.
{"title":"NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing","authors":"Aibin Yan;Yue Zhang;Litao Wang;Zhengfeng Huang;Qingyang Zhang;Tianming Ni;Patrick Girard;Xiaoqing Wen","doi":"10.1109/TVLSI.2025.3614568","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3614568","url":null,"abstract":"Soft errors and power dissipation emerge as critical challenges in developing high-reliability and cost-sensitive embedded systems. To address these issues, the magnetic tunnel junction (MTJ) is considered a promising solution due to its nonvolatility and its compatibility with traditional CMOS manufacturing processes. In this work, we propose a novel nonvolatile (NV) latch consisting of inverters and MTJs, namely, NVLIM, which provides nonvolatility and robust partial tolerance against triple-node-upsets (TNUs) at low cost. NVLIM integrates a TNU-tolerant block based on CMOS with a backup-restore block using MTJs. Simulation results incorporating process, voltage, and temperature (PVT) variations, bias temperature instability (BTI) impact, and Monte Carlo simulations demonstrate the balanced performance in terms of nonvolatility, robust partial TNU tolerance, and comprehensive overhead of the proposed latch.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"268-279"},"PeriodicalIF":3.1,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents an edge-AIoT speech recognition system, which is based on a new spiking feature extraction (SFE) method and a PoolFormer (PF) neural network optimized for implementation on field-programmable gate array (FPGA) hardware. A Python-driven high-level synthesis (HLS) flow is adopted to accelerate software-to-hardware conversion for fast validation, demonstrating the potential of FPGA-based solutions in edge applications. This work provides a holistic end-to-end solution for ultralow-power speech recognition, leveraging HLS to bridge the gap between software and hardware development. Implemented in a Xilinx PYNQ-Z2 FPGA board, this optimized PF model achieved a speech recognition accuracy rate of 95.41% on the 35-class Google Commands dataset with a parameter count of 39k.
{"title":"FPGA Implementation of PoolFormer Network Using Python-Driven High-Level Synthesis Framework for Edge-AIoT Speech Recognition","authors":"Tiancheng Cao;Zhongyi Zhang;Wei Soon Ng;Wang Ling Goh;Yuan Gao","doi":"10.1109/TVLSI.2025.3614721","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3614721","url":null,"abstract":"This brief presents an edge-AIoT speech recognition system, which is based on a new spiking feature extraction (SFE) method and a PoolFormer (PF) neural network optimized for implementation on field-programmable gate array (FPGA) hardware. A Python-driven high-level synthesis (HLS) flow is adopted to accelerate software-to-hardware conversion for fast validation, demonstrating the potential of FPGA-based solutions in edge applications. This work provides a holistic end-to-end solution for ultralow-power speech recognition, leveraging HLS to bridge the gap between software and hardware development. Implemented in a Xilinx PYNQ-Z2 FPGA board, this optimized PF model achieved a speech recognition accuracy rate of 95.41% on the 35-class Google Commands dataset with a parameter count of 39k.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"317-321"},"PeriodicalIF":3.1,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/TVLSI.2025.3613675
P. J. Zhou;Y. C. Chen;R. C. Ma;G. C. Qiao;N. Ning;Q. Yu;S. G. Hu
Neuromorphic computing is distinguished by its strong hardware friendliness and high computational sparsity, making it well-suited for a wide range of edge applications. However, the highly anticipated neuromorphic transformer still faces significant challenges in energy efficiency due to its heavy computational workload (primarily stemming from the self-attention mechanism), making edge deployment difficult. To address this problem, this work proposes a neuron inhibition mechanism that identifies and bypasses the computation of inactive neurons (i.e., those with extremely negative membrane potentials (MPs) and do not fire spikes). It introduces additional neuron sparsity into neuromorphic computing, significantly reducing the computational workload during inference. The mechanism is implemented using a configurable negative MP threshold. If a neuron’s MP falls below this threshold, a mask is generated to bypass the neuron in subsequent calculations. This technology facilitates the development of a sparse2 synaptic processing unit (S2-SPE), which performs computations only on synapses associated with valid spike inputs in active (non-inhibited) neurons, thereby efficiently leveraging both neuron and spike sparsity. Eventually, a neuromorphic attention core is developed based on the S2-SPE, and its effectiveness is validated on various datasets. The experimental results demonstrate that the core can bypass over 98% of invalid calculations in the neuromorphic attention mechanism, achieving an outstanding energy efficiency of sub-0.06 pJ/SOP, which represents over 50% improvement compared to the baseline and outperforms related state-of-the-art (SOTA) works. This work is expected to advance neuromorphic hardware toward greater energy efficiency and facilitate its deployment in edge applications.
{"title":"An Energy-Efficient Neuromorphic Self-Attention Core Exploiting Dual Sparsity in Neurons and Spikes","authors":"P. J. Zhou;Y. C. Chen;R. C. Ma;G. C. Qiao;N. Ning;Q. Yu;S. G. Hu","doi":"10.1109/TVLSI.2025.3613675","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3613675","url":null,"abstract":"Neuromorphic computing is distinguished by its strong hardware friendliness and high computational sparsity, making it well-suited for a wide range of edge applications. However, the highly anticipated neuromorphic transformer still faces significant challenges in energy efficiency due to its heavy computational workload (primarily stemming from the self-attention mechanism), making edge deployment difficult. To address this problem, this work proposes a neuron inhibition mechanism that identifies and bypasses the computation of inactive neurons (i.e., those with extremely negative membrane potentials (MPs) and do not fire spikes). It introduces additional neuron sparsity into neuromorphic computing, significantly reducing the computational workload during inference. The mechanism is implemented using a configurable negative MP threshold. If a neuron’s MP falls below this threshold, a mask is generated to bypass the neuron in subsequent calculations. This technology facilitates the development of a sparse<sup>2</sup> synaptic processing unit (S<sup>2</sup>-SPE), which performs computations only on synapses associated with valid spike inputs in active (non-inhibited) neurons, thereby efficiently leveraging both neuron and spike sparsity. Eventually, a neuromorphic attention core is developed based on the S<sup>2</sup>-SPE, and its effectiveness is validated on various datasets. The experimental results demonstrate that the core can bypass over 98% of invalid calculations in the neuromorphic attention mechanism, achieving an outstanding energy efficiency of sub-0.06 pJ/SOP, which represents over 50% improvement compared to the baseline and outperforms related state-of-the-art (SOTA) works. This work is expected to advance neuromorphic hardware toward greater energy efficiency and facilitate its deployment in edge applications.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"322-326"},"PeriodicalIF":3.1,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipelined analog-to-digital converter (ADC) with the reusing feedback capacitor (RFC) technique. With the proposed RFC technique, the feedback capacitor can simultaneously accomplish the 1st-stage residue transfer, the 2nd-stage quantization error extraction and feedback, and reference voltage matching, which reduces circuit complexity and enhances linearity. To mitigate the noise leakage resulting from gain error, a single-stage closed-loop gain-boosted cascoded floating inverter amplifier (GBCFIA) with 85-dB open-loop gain is proposed. The GBCFIA demonstrates a combination of robustness, high accuracy, and enhanced energy efficiency. Fabricated in a 65-nm CMOS process, the ADC prototype achieves a measured 78.5-dB signal-to-noise and distortion ratio (SNDR) in a 250 MS/s at an oversampling ratio (OSR) of 8. With 2.96-mW power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 175.7 dB.
{"title":"An SAR-Assisted Noise-Shaping Pipeline ADC With Gain-Boosted Cascoded Floating Inverter Amplifier","authors":"Xianghui Zhang;Guolong Fu;HaoYu Tian;Yanbo Zhang;Zhangming Zhu","doi":"10.1109/TVLSI.2025.3612411","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3612411","url":null,"abstract":"This brief presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipelined analog-to-digital converter (ADC) with the reusing feedback capacitor (RFC) technique. With the proposed RFC technique, the feedback capacitor can simultaneously accomplish the 1st-stage residue transfer, the 2nd-stage quantization error extraction and feedback, and reference voltage matching, which reduces circuit complexity and enhances linearity. To mitigate the noise leakage resulting from gain error, a single-stage closed-loop gain-boosted cascoded floating inverter amplifier (GBCFIA) with 85-dB open-loop gain is proposed. The GBCFIA demonstrates a combination of robustness, high accuracy, and enhanced energy efficiency. Fabricated in a 65-nm CMOS process, the ADC prototype achieves a measured 78.5-dB signal-to-noise and distortion ratio (SNDR) in a 250 MS/s at an oversampling ratio (OSR) of 8. With 2.96-mW power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 175.7 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"312-316"},"PeriodicalIF":3.1,"publicationDate":"2025-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Corrections to “Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach”","authors":"Ming-Yi Lin;Wei-Kuan Chiang;Chin-Hung Wang","doi":"10.1109/TVLSI.2025.3600857","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3600857","url":null,"abstract":"In the above article [1], the citation for “March mSR” in Tables VI through Table IX was incorrect. The correct citation should have been [16].","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 10","pages":"2902-2902"},"PeriodicalIF":3.1,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11181251","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TVLSI.2025.3609598
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2025.3609598","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3609598","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 10","pages":"C3-C3"},"PeriodicalIF":3.1,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11181241","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-26DOI: 10.1109/TVLSI.2025.3611704
Sunghoon Kim;Donghyun Han;Dayoung Kim;Sungho Kang
Through-silicon vias (TSVs) are essential for interdie connections in 3-D integrated circuits (3-D ICs), but their susceptibility to defects necessitates effective testing. As the correct operation of TSVs is critical to the overall reliability of 3-D ICs, their testing is regarded as an essential part of the 3-D IC testing process. Conventional TSV testing based on the IEEE-1838 standard architecture often increases test cycles due to the serial data application through die wrapper registers (DWRs). In this brief, an architecture is proposed that enables efficient TSV testing by using the streaming scan network (SSN) architecture, which is already utilized for logic core testing. TSV groups are treated as identical cores, allowing parallel application of test patterns via the SSN bus and streaming scan host (SSH). The experimental results show that the proposed method achieves a significant reduction in test cycles compared with the conventional TSV test method based on the IEEE-1838 standard architecture, without incurring a noticeable increase in area overhead. The reduction in test cycles becomes more pronounced as the number of TSVs increases.
{"title":"Test Cycle Reduction for TSV Test Using Streaming Scan Network on 3-D IC","authors":"Sunghoon Kim;Donghyun Han;Dayoung Kim;Sungho Kang","doi":"10.1109/TVLSI.2025.3611704","DOIUrl":"https://doi.org/10.1109/TVLSI.2025.3611704","url":null,"abstract":"Through-silicon vias (TSVs) are essential for interdie connections in 3-D integrated circuits (3-D ICs), but their susceptibility to defects necessitates effective testing. As the correct operation of TSVs is critical to the overall reliability of 3-D ICs, their testing is regarded as an essential part of the 3-D IC testing process. Conventional TSV testing based on the IEEE-1838 standard architecture often increases test cycles due to the serial data application through die wrapper registers (DWRs). In this brief, an architecture is proposed that enables efficient TSV testing by using the streaming scan network (SSN) architecture, which is already utilized for logic core testing. TSV groups are treated as identical cores, allowing parallel application of test patterns via the SSN bus and streaming scan host (SSH). The experimental results show that the proposed method achieves a significant reduction in test cycles compared with the conventional TSV test method based on the IEEE-1838 standard architecture, without incurring a noticeable increase in area overhead. The reduction in test cycles becomes more pronounced as the number of TSVs increases.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"34 1","pages":"307-311"},"PeriodicalIF":3.1,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145847835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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