Pub Date : 2024-11-18DOI: 10.1109/TVLSI.2024.3495558
Francesco Gagliardi;Danilo Scintu;Massimo Piotto;Paolo Bruschi;Michele Dei
Driven by the ongoing challenge of designing high-accuracy digital-to-analog converters (DACs) at the cost of a relatively small area occupation, optimal combination algorithms (OCAs) recently gained attention within the myriad of possible calibration techniques for DACs. OCAs show appealing properties with respect to traditional approaches such as dynamic element matching (DEM). At start-up or upon request, mismatches affecting DAC elements are measured on-chip, allowing rearrangement in the selection logic of the DAC unit elements. The newly found arrangement is, hence, used during normal operation, achieving superior linearity. As of today, several alternative OCAs have been proposed; however, designers willing to implement OCA-calibrated DACs are faced with unclear tradeoffs and insufficient design guidelines. In this work, we provide a detailed comparison of existing OCAs based on statistical behavioral simulations. Starting from this, we investigate the relationships between OCAs’ performances and circuit-level design aspects. Specifically, OCAs’ effectiveness in improving the static linearity is linked to the number of DAC bits and the accuracy of the auxiliary comparator required by every OCA. Unforeseen trends emerge, and new design considerations are suggested, fostering novel awareness on the subject of high-accuracy DAC designs enabled by OCA-based calibration techniques.
在设计高精度数模转换器（DAC）的过程中，需要以相对较小的占地面积为代价，在这一挑战的推动下，优化组合算法（OCA）最近在数不胜数的 DAC 校准技术中受到了关注。与动态元素匹配（DEM）等传统方法相比，优化组合算法显示出了极具吸引力的特性。在启动时或根据要求，可在芯片上测量影响 DAC 元件的不匹配情况，从而重新安排 DAC 单元元件的选择逻辑。因此，新发现的排列方式可在正常运行时使用，从而实现出色的线性度。到目前为止，已经提出了几种可供选择的 OCA；但是，愿意采用 OCA 校准 DAC 的设计人员面临着权衡不清和设计指导不足的问题。在这项工作中，我们基于统计行为模拟对现有的 OCA 进行了详细比较。在此基础上，我们研究了 OCA 性能与电路级设计之间的关系。具体来说，OCA 在改善静态线性度方面的有效性与每个 OCA 所需的 DAC 位数和辅助比较器的精度有关。我们发现了不可预见的趋势，并提出了新的设计考虑因素，从而促进了对基于 OCA 校准技术的高精度 DAC 设计这一主题的新认识。
{"title":"Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements","authors":"Francesco Gagliardi;Danilo Scintu;Massimo Piotto;Paolo Bruschi;Michele Dei","doi":"10.1109/TVLSI.2024.3495558","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3495558","url":null,"abstract":"Driven by the ongoing challenge of designing high-accuracy digital-to-analog converters (DACs) at the cost of a relatively small area occupation, optimal combination algorithms (OCAs) recently gained attention within the myriad of possible calibration techniques for DACs. OCAs show appealing properties with respect to traditional approaches such as dynamic element matching (DEM). At start-up or upon request, mismatches affecting DAC elements are measured on-chip, allowing rearrangement in the selection logic of the DAC unit elements. The newly found arrangement is, hence, used during normal operation, achieving superior linearity. As of today, several alternative OCAs have been proposed; however, designers willing to implement OCA-calibrated DACs are faced with unclear tradeoffs and insufficient design guidelines. In this work, we provide a detailed comparison of existing OCAs based on statistical behavioral simulations. Starting from this, we investigate the relationships between OCAs’ performances and circuit-level design aspects. Specifically, OCAs’ effectiveness in improving the static linearity is linked to the number of DAC bits and the accuracy of the auxiliary comparator required by every OCA. Unforeseen trends emerge, and new design considerations are suggested, fostering novel awareness on the subject of high-accuracy DAC designs enabled by OCA-based calibration techniques.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2243-2256"},"PeriodicalIF":2.8,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10756519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-14DOI: 10.1109/TVLSI.2024.3480997
Jia-Li Duan;Chi Zhang;Li-Hui Wang;Lei Shen
Fully homomorphic encryption (FHE) enables calculations on encrypted data and is a crucial foundation for achieving privacy computing. However, the high computation overhead restricts its widespread application. Even after algorithm and software optimization, its processing speed remains low. This article proposes the first practical system-level multicore Brakerski-Gentry-Vaikuntanathan (BGV) hardware acceleration scheme based on field-programmable gate array (FPGA). By analyzing the bottleneck of system acceleration, a hierarchical storage structure is introduced to reduce data movement. A novel 4-2 mixed-radix number theoretic transform (NTT) algorithm is proposed, allowing flexible switching between radix-4 and radix-2, with the ability to reuse twiddle factors. In addition, a reconfigurable processing element (PE) is proposed that supports all homomorphic operations of BGV. The design of this article is evaluated on Xilinx Virtex7 series FPGA, achieving a throughput of NTT/inverse NTT (INTT) up to $14times $ higher than previous designs. Compared with simple encrypted arithmetic library (SEAL), the full system performances of homomorphic encryption (ENC), decryption (DEC), and homomorphic multiplication achieve improvements of $13.9times $ , $7.07times $ , and $16.6times $ , respectively.
{"title":"SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA","authors":"Jia-Li Duan;Chi Zhang;Li-Hui Wang;Lei Shen","doi":"10.1109/TVLSI.2024.3480997","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3480997","url":null,"abstract":"Fully homomorphic encryption (FHE) enables calculations on encrypted data and is a crucial foundation for achieving privacy computing. However, the high computation overhead restricts its widespread application. Even after algorithm and software optimization, its processing speed remains low. This article proposes the first practical system-level multicore Brakerski-Gentry-Vaikuntanathan (BGV) hardware acceleration scheme based on field-programmable gate array (FPGA). By analyzing the bottleneck of system acceleration, a hierarchical storage structure is introduced to reduce data movement. A novel 4-2 mixed-radix number theoretic transform (NTT) algorithm is proposed, allowing flexible switching between radix-4 and radix-2, with the ability to reuse twiddle factors. In addition, a reconfigurable processing element (PE) is proposed that supports all homomorphic operations of BGV. The design of this article is evaluated on Xilinx Virtex7 series FPGA, achieving a throughput of NTT/inverse NTT (INTT) up to <inline-formula> <tex-math>$14times $ </tex-math></inline-formula> higher than previous designs. Compared with simple encrypted arithmetic library (SEAL), the full system performances of homomorphic encryption (ENC), decryption (DEC), and homomorphic multiplication achieve improvements of <inline-formula> <tex-math>$13.9times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$7.07times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$16.6times $ </tex-math></inline-formula>, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"546-557"},"PeriodicalIF":2.8,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-14DOI: 10.1109/TVLSI.2024.3489231
Jie Ding;Fuming Liu;Kuan Deng;Zihan Zheng;Jingnan Zheng;Yongzhen Chen;Jiangfeng Wu
This article introduces a successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a foreground capacitor mismatch self-calibration method. The proposed floating operation puts the uncalibrated high-bit capacitor into the floating state, preventing the sub-ADC from saturating caused by comparator static offset during the calibration process. To address the random mismatch of the LSB capacitors and improve the calibration accuracy, this article employs round-robin grouping of eight sets of LSB capacitors. In addition, a precharged bootstrapped switch is proposed to achieve high sampling linearity with low power consumption and area overhead. An anti-interference custom-designed 0.5-fF capacitor structure is suggested for binary-weighted capacitor mismatch of capacitive DAC (CDAC). Furthermore, the circuit implementation of the comparator utilized by ADC is also discussed. The prototype was fabricated in a 180-nm CMOS process with a 1.8-V supply and achieved spurious-free dynamic ranges of 108.9 and 92.38 dB at an input frequency of 1 kHz while operating at sampling rates of 100 kS/s and 1 MS/s, respectively. The prototype consumes 6.745 mW and occupies 0.91 $text {mm}^{2}$ .
{"title":"A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration","authors":"Jie Ding;Fuming Liu;Kuan Deng;Zihan Zheng;Jingnan Zheng;Yongzhen Chen;Jiangfeng Wu","doi":"10.1109/TVLSI.2024.3489231","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3489231","url":null,"abstract":"This article introduces a successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a foreground capacitor mismatch self-calibration method. The proposed floating operation puts the uncalibrated high-bit capacitor into the floating state, preventing the sub-ADC from saturating caused by comparator static offset during the calibration process. To address the random mismatch of the LSB capacitors and improve the calibration accuracy, this article employs round-robin grouping of eight sets of LSB capacitors. In addition, a precharged bootstrapped switch is proposed to achieve high sampling linearity with low power consumption and area overhead. An anti-interference custom-designed 0.5-fF capacitor structure is suggested for binary-weighted capacitor mismatch of capacitive DAC (CDAC). Furthermore, the circuit implementation of the comparator utilized by ADC is also discussed. The prototype was fabricated in a 180-nm CMOS process with a 1.8-V supply and achieved spurious-free dynamic ranges of 108.9 and 92.38 dB at an input frequency of 1 kHz while operating at sampling rates of 100 kS/s and 1 MS/s, respectively. The prototype consumes 6.745 mW and occupies 0.91 \u0000<inline-formula> <tex-math>$text {mm}^{2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"10-20"},"PeriodicalIF":2.8,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TVLSI.2024.3477731
Zhaolin Yang;Jing Jin;Xiaoming Liu;Jianjun Zhou
A 0.2–2.6 GHz reconfigurable direct conversion receiver is proposed in this article. The receiver’s high-linearity mode and high-gain mode can be configured by either bypassing or including the low-noise amplifier (LNA) stage. An agile-switching module is designed to facilitate the mode transitioning. In high-gain mode, a variable-gain current-reused shunt-feedback (VGCRSF) LNA with radio frequency (RF) gain-adapted impedance matching technique is proposed. Instead of utilizing a shared transconductance (Gm) stage in both the I- and Q-path, the Gm-separated IQ-leakage suppression (GSIQLS) structure is employed in the mixer stage to reduce the complex and frequency-dependent IQ mismatch engendered by the nonideal local oscillator (LO) signal overlap. In baseband, both the gain and the bandwidth are made configurable through the utilization of a bi-quad low pass filter (LPF) and a programmable gain amplifier (PGA). The proposed receiver is fabricated in a 40-nm CMOS technology. Measurement results indicate a maximum conversion gain of 78.5 dB and a minimum noise figure (NF) of 2.5 dB are achieved. The input 1-dB compression point (IP1dB), in-band (IB) third-order input-referred intercept point (IIP3), and out-of-band (OOB) IIP3 are larger than 0, 9.7, and 13.1 dBm, respectively. The gain and phase mismatch of the quadrature receiver are lower than 0.3 dB and 1°, respectively, over the baseband bandwidth ranging from 410 kHz to 24 MHz. The receiver occupies an area of 0.605 mm2 and consumes a power of 75.4 mW.
{"title":"A 0.2–2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS","authors":"Zhaolin Yang;Jing Jin;Xiaoming Liu;Jianjun Zhou","doi":"10.1109/TVLSI.2024.3477731","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3477731","url":null,"abstract":"A 0.2–2.6 GHz reconfigurable direct conversion receiver is proposed in this article. The receiver’s high-linearity mode and high-gain mode can be configured by either bypassing or including the low-noise amplifier (LNA) stage. An agile-switching module is designed to facilitate the mode transitioning. In high-gain mode, a variable-gain current-reused shunt-feedback (VGCRSF) LNA with radio frequency (RF) gain-adapted impedance matching technique is proposed. Instead of utilizing a shared transconductance (Gm) stage in both the I- and Q-path, the Gm-separated IQ-leakage suppression (GSIQLS) structure is employed in the mixer stage to reduce the complex and frequency-dependent IQ mismatch engendered by the nonideal local oscillator (LO) signal overlap. In baseband, both the gain and the bandwidth are made configurable through the utilization of a bi-quad low pass filter (LPF) and a programmable gain amplifier (PGA). The proposed receiver is fabricated in a 40-nm CMOS technology. Measurement results indicate a maximum conversion gain of 78.5 dB and a minimum noise figure (NF) of 2.5 dB are achieved. The input 1-dB compression point (IP1dB), in-band (IB) third-order input-referred intercept point (IIP3), and out-of-band (OOB) IIP3 are larger than 0, 9.7, and 13.1 dBm, respectively. The gain and phase mismatch of the quadrature receiver are lower than 0.3 dB and 1°, respectively, over the baseband bandwidth ranging from 410 kHz to 24 MHz. The receiver occupies an area of 0.605 mm2 and consumes a power of 75.4 mW.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"234-247"},"PeriodicalIF":2.8,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, a unified voltage frequency regulator (UVFR) system is designed to eliminate the voltage margin induced by process, voltage, and temperature (PVT) variations. The frequency is regulated with voltage by a universal logic line oscillator (ULLO), which can protect the system from timing violations. The length of the ULLO is self-calibrated by a ULL-based time-digital converter (ULL-TDC) and an in situ half-critical path timing detector, where the ULL is designed to track the critical path delay. A fully synthesizable digital low dropout (DLDO) is designed with the ULL-TDC and a proportional differential (PD) circuit for voltage regulation. The proposed system is implemented in an ARM Cortex-M0 microcontroller in 22 nm technology. Simulation results show that the ULL can accurately track the critical path delay with a maximum variation of 3% at 0.6 V and 11.5% at 0.45 V. The UVFR system consumes 13.2–112 uW of power overhead, and eliminates the voltage margin by 22.3%–28% while reducing the power consumption by 35%–42.3%.
{"title":"A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit","authors":"Jiliang Liu;Huidong Zhao;Zhi Li;Kangning Wang;Shushan Qiao","doi":"10.1109/TVLSI.2024.3466132","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3466132","url":null,"abstract":"In this brief, a unified voltage frequency regulator (UVFR) system is designed to eliminate the voltage margin induced by process, voltage, and temperature (PVT) variations. The frequency is regulated with voltage by a universal logic line oscillator (ULLO), which can protect the system from timing violations. The length of the ULLO is self-calibrated by a ULL-based time-digital converter (ULL-TDC) and an in situ half-critical path timing detector, where the ULL is designed to track the critical path delay. A fully synthesizable digital low dropout (DLDO) is designed with the ULL-TDC and a proportional differential (PD) circuit for voltage regulation. The proposed system is implemented in an ARM Cortex-M0 microcontroller in 22 nm technology. Simulation results show that the ULL can accurately track the critical path delay with a maximum variation of 3% at 0.6 V and 11.5% at 0.45 V. The UVFR system consumes 13.2–112 uW of power overhead, and eliminates the voltage margin by 22.3%–28% while reducing the power consumption by 35%–42.3%.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"593-597"},"PeriodicalIF":2.8,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142992849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TVLSI.2024.3474954
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3474954","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474954","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736407","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TVLSI.2024.3474952
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3474952","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474952","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736448","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TVLSI.2024.3477632
Dongkwun Kim;Zhaoqing Wang;Paul Xuanyuanliang Huang;Pavan Kumar Chundi;Suhwan Kim;Andrés A. Blanco;Ram K. Krishnamurthy;Mingoo Seok
This article presents a Li-ion battery-compatible single-inductor-multiple-output (SIMO) buck converter that fulfills the power management need of an integrated sub-mW RISC-V microprocessor. The proposed converter can directly take a 4.2-V battery voltage and produce four power rails ranging from 1.8 V for I/O to 0.5 V for the processor core. The three-level input stage is chosen to reduce the inductor ripple size and switching loss, thus increasing power conversion efficiency (PCE). In addition, the fully digital implementation using novel domino flash analog-digital converters (ADCs) enables low static current. Also, pulse frequency modulation (PFM) results in a wide dynamic range. The proposed three-level SIMO converter has been prototyped in a 65-nm CMOS technology with the 32-bit RISC-V processor. Measurement results show that the converter achieves a $1000times $ load current range ( $0.8~mu $ A–0.8 mA) to support the active or sleep modes of the processor. The converter marks the PCE of 56.2%–72.8%. Compared to the ideal buck-low-dropout voltage regulator (LDO) architecture (LDO-only), it improves the PCE by 23.8% (46.4%).
本文提出了一种锂离子电池兼容的单电感多输出（SIMO）降压转换器，它满足了集成的毫瓦以下RISC-V微处理器的电源管理需求。所提出的转换器可以直接采用4.2 V的电池电压，并产生从1.8 V的I/O到0.5 V的处理器核心的四个电源轨。选择三电平输入级是为了减小电感纹波大小和开关损耗，从而提高功率转换效率。此外，采用新型多米诺闪存模数转换器（adc）的全数字实现可以实现低静态电流。此外，脉冲频率调制（PFM）具有宽的动态范围。所提出的三电平SIMO转换器已采用65纳米CMOS技术和32位RISC-V处理器进行原型设计。测量结果表明，该转换器实现了$1000times $负载电流范围（$0.8~ $ a - 0.8 mA），以支持处理器的活动或休眠模式。转换器的PCE为56.2%-72.8%。与理想的buck-low-dropout电压调节器（LDO）架构（仅LDO）相比，PCE提高了23.8%（46.4%）。
{"title":"A 4.2-to-0.5-V, 0.8-μA–0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor","authors":"Dongkwun Kim;Zhaoqing Wang;Paul Xuanyuanliang Huang;Pavan Kumar Chundi;Suhwan Kim;Andrés A. Blanco;Ram K. Krishnamurthy;Mingoo Seok","doi":"10.1109/TVLSI.2024.3477632","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3477632","url":null,"abstract":"This article presents a Li-ion battery-compatible single-inductor-multiple-output (SIMO) buck converter that fulfills the power management need of an integrated sub-mW RISC-V microprocessor. The proposed converter can directly take a 4.2-V battery voltage and produce four power rails ranging from 1.8 V for I/O to 0.5 V for the processor core. The three-level input stage is chosen to reduce the inductor ripple size and switching loss, thus increasing power conversion efficiency (PCE). In addition, the fully digital implementation using novel domino flash analog-digital converters (ADCs) enables low static current. Also, pulse frequency modulation (PFM) results in a wide dynamic range. The proposed three-level SIMO converter has been prototyped in a 65-nm CMOS technology with the 32-bit RISC-V processor. Measurement results show that the converter achieves a \u0000<inline-formula> <tex-math>$1000times $ </tex-math></inline-formula>\u0000 load current range (\u0000<inline-formula> <tex-math>$0.8~mu $ </tex-math></inline-formula>\u0000A–0.8 mA) to support the active or sleep modes of the processor. The converter marks the PCE of 56.2%–72.8%. Compared to the ideal buck-low-dropout voltage regulator (LDO) architecture (LDO-only), it improves the PCE by 23.8% (46.4%).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"193-206"},"PeriodicalIF":2.8,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142918375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1109/TVLSI.2024.3475810
Jere Rusanen;Negar Shabanzadeh;Aarno Pärssinen;Timo Rahkonen;Janne P. Aikio
This article presents an integrated quadrature balanced power amplifier (PA) operating at a 26-GHz frequency range and techniques to mitigate the frequency-dependent amplitude response of quadrature hybrids used in the balanced amplifier design. The overall structure consists of two stacked pseudo-differential PAs and transformer-based quadrature hybrids designed with 22-nm CMOS FDSOI. Two techniques to compensate frequency-dependent amplitude response of the quadrature hybrid when operating away from the center frequency are proposed. The first one involves a dual input drive and the second one involves asymmetric biasing. With distortion contribution analysis, it is shown that asymmetric biasing compensates quadrature hybrid asymmetry but also produces mutually compensating third-order nonlinearity, resulting in improved linearity. Measurements with continuous wave (CW) and high dynamic range fifth generation (5G) modulated signal demonstrate that the described techniques improve output power that can be reached within the linearity specifications when operating away from the center frequency.
{"title":"Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects","authors":"Jere Rusanen;Negar Shabanzadeh;Aarno Pärssinen;Timo Rahkonen;Janne P. Aikio","doi":"10.1109/TVLSI.2024.3475810","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3475810","url":null,"abstract":"This article presents an integrated quadrature balanced power amplifier (PA) operating at a 26-GHz frequency range and techniques to mitigate the frequency-dependent amplitude response of quadrature hybrids used in the balanced amplifier design. The overall structure consists of two stacked pseudo-differential PAs and transformer-based quadrature hybrids designed with 22-nm CMOS FDSOI. Two techniques to compensate frequency-dependent amplitude response of the quadrature hybrid when operating away from the center frequency are proposed. The first one involves a dual input drive and the second one involves asymmetric biasing. With distortion contribution analysis, it is shown that asymmetric biasing compensates quadrature hybrid asymmetry but also produces mutually compensating third-order nonlinearity, resulting in improved linearity. Measurements with continuous wave (CW) and high dynamic range fifth generation (5G) modulated signal demonstrate that the described techniques improve output power that can be reached within the linearity specifications when operating away from the center frequency.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2198-2209"},"PeriodicalIF":2.8,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10726609","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142821280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1109/TVLSI.2024.3474791
Youngki Moon;Seung Ho Shin;Seokjun Jang;Duyeon Won;Sungho Kang
Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.
{"title":"A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM","authors":"Youngki Moon;Seung Ho Shin;Seokjun Jang;Duyeon Won;Sungho Kang","doi":"10.1109/TVLSI.2024.3474791","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474791","url":null,"abstract":"Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"488-498"},"PeriodicalIF":2.8,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：