Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3426516
M. Ghashghai;M. B. Ghaznavi-Ghoushchi
In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18- $mu $ CMOS standard technology with 0.004-mm2 active area and 8.8- $mu $ power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C $_{text {L}} =3.7$ nF. An average slew rate (SR) of 0.38 v/ $mu $ s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.
{"title":"Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach","authors":"M. Ghashghai;M. B. Ghaznavi-Ghoushchi","doi":"10.1109/TVLSI.2024.3426516","DOIUrl":"10.1109/TVLSI.2024.3426516","url":null,"abstract":"In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 CMOS standard technology with 0.004-mm2 active area and 8.8-\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C\u0000<inline-formula> <tex-math>$_{text {L}} =3.7$ </tex-math></inline-formula>\u0000 nF. An average slew rate (SR) of 0.38 v/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 10","pages":"1792-1800"},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3418151
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3418151","DOIUrl":"10.1109/TVLSI.2024.3418151","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 8","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609532","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3430544
Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu
This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain ( $K_{text {VCO}}$ ) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a $K_{text {VCO}}$ of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM $rm {_{T}}$ ) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.
{"title":"Design of Octave Tuning Range LC VCO With Ultralow KVCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique","authors":"Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu","doi":"10.1109/TVLSI.2024.3430544","DOIUrl":"10.1109/TVLSI.2024.3430544","url":null,"abstract":"This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain (\u0000<inline-formula> <tex-math>$K_{text {VCO}}$ </tex-math></inline-formula>\u0000) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a \u0000<inline-formula> <tex-math>$K_{text {VCO}}$ </tex-math></inline-formula>\u0000 of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM\u0000<inline-formula> <tex-math>$rm {_{T}}$ </tex-math></inline-formula>\u0000) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 10","pages":"1908-1918"},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3415749
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3415749","DOIUrl":"10.1109/TVLSI.2024.3415749","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 8","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609531","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Event-driven neuromorphic processors for artificial intelligence (AI) inference on edge/IoT devices require largeon-chip memory capacity, for efficient execution of spiking neural networks (NNs). In this work, we evaluate 3-D stacking benefits on SENECA, a digital neuromorphic accelerator core, sweeping itson-chip memory capacity from 2 up to 32 Mb in both legacy planar and advanced nanosheet CMOS logic nodes. In a planar CMOS node (GF-22 nm), two-die memory-on-logic (MoL) partitioning enables $8times $ moreon-chip memory, and it boosts operating frequency by 7% with 26% less power than the 2-D. Moving to an advanced nanosheet technology (imec A10), multidie (up to 7 dies) MoL stacking enables a performance increase of up to 29% and power savings up to 31%. Furthermore, a core folding (CF) partitioning in A10 shows up to 16% performance improvement with 12% total power savings with respect to the 2-D implementation on the same technology. We also demonstrate no thermal overhead for multidie stacking at advanced nodes for designs exhibiting low power density. These physical design explorations lay the foundation for system technology co-optimization studies for edge devices.
{"title":"Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures","authors":"Leandro M. Giacomini Rocha;Refik Bilgic;Mohamed Naeim;Sudipta Das;Herman Oprins;Amirreza Yousefzadeh;Mario Konijnenburg;Dragomir Milojevic;James Myers;Julien Ryckaert;Dwaipayan Biswas","doi":"10.1109/TVLSI.2024.3421625","DOIUrl":"10.1109/TVLSI.2024.3421625","url":null,"abstract":"Event-driven neuromorphic processors for artificial intelligence (AI) inference on edge/IoT devices require largeon-chip memory capacity, for efficient execution of spiking neural networks (NNs). In this work, we evaluate 3-D stacking benefits on SENECA, a digital neuromorphic accelerator core, sweeping itson-chip memory capacity from 2 up to 32 Mb in both legacy planar and advanced nanosheet CMOS logic nodes. In a planar CMOS node (GF-22 nm), two-die memory-on-logic (MoL) partitioning enables \u0000<inline-formula> <tex-math>$8times $ </tex-math></inline-formula>\u0000 moreon-chip memory, and it boosts operating frequency by 7% with 26% less power than the 2-D. Moving to an advanced nanosheet technology (imec A10), multidie (up to 7 dies) MoL stacking enables a performance increase of up to 29% and power savings up to 31%. Furthermore, a core folding (CF) partitioning in A10 shows up to 16% performance improvement with 12% total power savings with respect to the 2-D implementation on the same technology. We also demonstrate no thermal overhead for multidie stacking at advanced nodes for designs exhibiting low power density. These physical design explorations lay the foundation for system technology co-optimization studies for edge devices.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"2144-2148"},"PeriodicalIF":2.8,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-23DOI: 10.1109/tvlsi.2024.3430094
Byeong Yong Kong
{"title":"Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange","authors":"Byeong Yong Kong","doi":"10.1109/tvlsi.2024.3430094","DOIUrl":"https://doi.org/10.1109/tvlsi.2024.3430094","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"16 1","pages":""},"PeriodicalIF":2.8,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/TVLSI.2024.3425771
Yichen Xu;Zhaoqing Wang;Jonghyun Oh;Mingoo Seok
A digital low dropout (DLDO) regulator is one of the most critical building blocks in on-chip power management for its technology portability, voltage scalability, and other benefits associated with digital-oriented design. A key metric of DLDOs is the dynamic load regulation performance, often measured as the maximum current that a DLDO can quickly supply upon a significant load step under a voltage droop constraint (usually 10% of the output voltage). Previous works focused on architecture and circuit techniques to improve this metric. However, limited research focuses on the model development for the dynamic load regulation performance. To fill this gap, in this article, we propose the analytical models of the maximum load current of the standard DLDOs employing feedback and feedforward control laws. The developed models shed light on the impact of various design parameters on the total load current of a DLDO, with which both circuit and system designers can navigate the design space quickly and effectively.
{"title":"Model-Based Study on the Limit of the Dynamic Load Regulation Performance of a Digital Low Dropout Regulator","authors":"Yichen Xu;Zhaoqing Wang;Jonghyun Oh;Mingoo Seok","doi":"10.1109/TVLSI.2024.3425771","DOIUrl":"10.1109/TVLSI.2024.3425771","url":null,"abstract":"A digital low dropout (DLDO) regulator is one of the most critical building blocks in on-chip power management for its technology portability, voltage scalability, and other benefits associated with digital-oriented design. A key metric of DLDOs is the dynamic load regulation performance, often measured as the maximum current that a DLDO can quickly supply upon a significant load step under a voltage droop constraint (usually 10% of the output voltage). Previous works focused on architecture and circuit techniques to improve this metric. However, limited research focuses on the model development for the dynamic load regulation performance. To fill this gap, in this article, we propose the analytical models of the maximum load current of the standard DLDOs employing feedback and feedforward control laws. The developed models shed light on the impact of various design parameters on the total load current of a DLDO, with which both circuit and system designers can navigate the design space quickly and effectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 10","pages":"1822-1829"},"PeriodicalIF":2.8,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141739165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-16DOI: 10.1109/TVLSI.2024.3425817
Irith Pomeranz;Yervant Zorian
Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.
{"title":"Functionally Possible Path Delay Faults With High Functional Switching Activity","authors":"Irith Pomeranz;Yervant Zorian","doi":"10.1109/TVLSI.2024.3425817","DOIUrl":"10.1109/TVLSI.2024.3425817","url":null,"abstract":"Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"2159-2163"},"PeriodicalIF":2.8,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141717633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/TVLSI.2024.3418930
Bhaskar Gaur;Himanshu Thapliyal
Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement the functions of higher complexity, such as subtraction and multiplication, which are used in applications, such as quantum cryptanalysis, quantum image processing, and securing communication. To the best of our knowledge, there is no existing design of quantum modulo ( $2^{n}+1$ ) adder (QMA). In this work, we propose four quantum adders targeted specifically for modulo ( $2^{n}+1$ ) addition. These adders can provide both regular and modulo ( $2^{n}+1$ ) sum concurrently, enhancing their application in residue number system-based arithmetic. Our first design, QMA1, is a novel quantum modulo ( $2^{n}+1$ ) adder. The second proposed adder, QMA2, optimizes the utilization of quantum gates within the QMA1, resulting in 37.5% reduced CNOT gate count, 46.15% reduced CNOT depth, and 26.5% decrease in both Toffoli gates and depth. We propose a third adder QMA3 that uses zero resets, a dynamic circuits-based feature that reuses qubits, leading to 25% savings in qubit count. Our fourth design, QMA4, demonstrates the benefit of incorporating additional zero resets to achieve a purer $|0$ $rangle $ state, reducing quantum state preparation errors. Notably, we conducted experiments using 5-qubit configurations of the proposed modulo ( $2^{n}+1$ ) adders on the IBM Washington, a 127-qubit quantum computer based on the Eagle R1 architecture, to demonstrate a 28.8% reduction in QMA1’s error of which do the following: 1) 18.63% error reduction happens due to gate/depth reduction in QMA2; 2) 2.53% drop in error due to qubit reduction in QMA3; and 3) 7.64% error decreased due to application of additional zero resets in QMA4.
{"title":"Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing","authors":"Bhaskar Gaur;Himanshu Thapliyal","doi":"10.1109/TVLSI.2024.3418930","DOIUrl":"10.1109/TVLSI.2024.3418930","url":null,"abstract":"Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement the functions of higher complexity, such as subtraction and multiplication, which are used in applications, such as quantum cryptanalysis, quantum image processing, and securing communication. To the best of our knowledge, there is no existing design of quantum modulo (\u0000<inline-formula> <tex-math>$2^{n}+1$ </tex-math></inline-formula>\u0000) adder (QMA). In this work, we propose four quantum adders targeted specifically for modulo (\u0000<inline-formula> <tex-math>$2^{n}+1$ </tex-math></inline-formula>\u0000) addition. These adders can provide both regular and modulo (\u0000<inline-formula> <tex-math>$2^{n}+1$ </tex-math></inline-formula>\u0000) sum concurrently, enhancing their application in residue number system-based arithmetic. Our first design, QMA1, is a novel quantum modulo (\u0000<inline-formula> <tex-math>$2^{n}+1$ </tex-math></inline-formula>\u0000) adder. The second proposed adder, QMA2, optimizes the utilization of quantum gates within the QMA1, resulting in 37.5% reduced CNOT gate count, 46.15% reduced CNOT depth, and 26.5% decrease in both Toffoli gates and depth. We propose a third adder QMA3 that uses zero resets, a dynamic circuits-based feature that reuses qubits, leading to 25% savings in qubit count. Our fourth design, QMA4, demonstrates the benefit of incorporating additional zero resets to achieve a purer \u0000<inline-formula> <tex-math>$|0$ </tex-math></inline-formula>\u0000<inline-formula> <tex-math>$rangle $ </tex-math></inline-formula>\u0000 state, reducing quantum state preparation errors. Notably, we conducted experiments using 5-qubit configurations of the proposed modulo (\u0000<inline-formula> <tex-math>$2^{n}+1$ </tex-math></inline-formula>\u0000) adders on the IBM Washington, a 127-qubit quantum computer based on the Eagle R1 architecture, to demonstrate a 28.8% reduction in QMA1’s error of which do the following: 1) 18.63% error reduction happens due to gate/depth reduction in QMA2; 2) 2.53% drop in error due to qubit reduction in QMA3; and 3) 7.64% error decreased due to application of additional zero resets in QMA4.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 9","pages":"1759-1763"},"PeriodicalIF":2.8,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141717635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces an innovative recursive discrete cosine transform (DCT) algorithm characterized by its exceptional precision and minimal multiplication requirements. Through the strategic implementation of data reordering and “q” value adjustment schemes, the proposed algorithm entails only a single constant-multiplication operation featuring a fixed cosine coefficient within the iterative phase. By judiciously selecting an appropriate “q” value (q =41), it achieves outstanding results, reaching peak signal-to-noise ratios (PSNRs) of 94.9 and 100.9 dB under 18-bit and 20-bit word length (WL) conditions, respectively, in terms of decimal places. Notably, the proposed algorithm substantially diminishes the number of multiplications by 86.08%, offset by an increase of 2688 additions. The proposed design has a simpler structure and utilizes fewer hardware resources. In field programmable gate array (FPGA) implementation, the device is composed of 43 combinational adaptive look-up tables (ALUTs) specifically allocated for constant multiplication (CM). Overall, the proposed accelerator totally takes 158 combinational ALUTs, 65 registers, a 960-bit read-only memory (ROM), and a 1024-bit random access memory (RAM) in hardware realization and can be operated at a maximum frequency of 156.62 MHz. Therefore, it is particularly well-suited for VLSI implementation in a parallel calculation of Mel-scale frequency cepstral coefficients (MFCCs).
{"title":"High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients","authors":"Shin-Chi Lai;Szu-Ting Wang;Yi-Chang Zhu;Ying-Hsiu Hung;Jeng-Dao Lee;Wei-Da Chen","doi":"10.1109/TVLSI.2024.3422994","DOIUrl":"10.1109/TVLSI.2024.3422994","url":null,"abstract":"This brief introduces an innovative recursive discrete cosine transform (DCT) algorithm characterized by its exceptional precision and minimal multiplication requirements. Through the strategic implementation of data reordering and “q” value adjustment schemes, the proposed algorithm entails only a single constant-multiplication operation featuring a fixed cosine coefficient within the iterative phase. By judiciously selecting an appropriate “q” value (q =41), it achieves outstanding results, reaching peak signal-to-noise ratios (PSNRs) of 94.9 and 100.9 dB under 18-bit and 20-bit word length (WL) conditions, respectively, in terms of decimal places. Notably, the proposed algorithm substantially diminishes the number of multiplications by 86.08%, offset by an increase of 2688 additions. The proposed design has a simpler structure and utilizes fewer hardware resources. In field programmable gate array (FPGA) implementation, the device is composed of 43 combinational adaptive look-up tables (ALUTs) specifically allocated for constant multiplication (CM). Overall, the proposed accelerator totally takes 158 combinational ALUTs, 65 registers, a 960-bit read-only memory (ROM), and a 1024-bit random access memory (RAM) in hardware realization and can be operated at a maximum frequency of 156.62 MHz. Therefore, it is particularly well-suited for VLSI implementation in a parallel calculation of Mel-scale frequency cepstral coefficients (MFCCs).","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"2139-2143"},"PeriodicalIF":2.8,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141717634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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