Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3418151
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Pub Date : 2024-07-25DOI: 10.1109/TVLSI.2024.3426516
M. Ghashghai;M. B. Ghaznavi-Ghoushchi
In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18- $mu $