Pub Date : 2024-10-25DOI: 10.1109/TVLSI.2024.3474954
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information","authors":"","doi":"10.1109/TVLSI.2024.3474954","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474954","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"C3-C3"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736407","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TVLSI.2024.3474952
{"title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information","authors":"","doi":"10.1109/TVLSI.2024.3474952","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3474952","url":null,"abstract":"","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 11","pages":"C2-C2"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10736448","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.
{"title":"Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits","authors":"Changle Zhi;Gang Dong;Deguang Yang;Daihang Liu;Yinghao Feng;Yang Wang;Zhangming Zhu","doi":"10.1109/TVLSI.2024.3478846","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3478846","url":null,"abstract":"In this work, a comprehensive analysis and optimization method of electrical and thermal characteristics in 2.5-D integrated circuits (ICs) is performed, including rapid heat distribution modeling, integrated voltage regulator (IVR) chip modeling, and power delivery network (PDN) modeling. Based on the proposed method, chiplet placement, decoupling placement, and IVR parameter settings that compromise the total PDN impedance, IVR impedance, and thermal distribution characteristics can be obtained. First, a rapid thermal analysis method for multiple heat sources is proposed by integrating the equivalent thermal resistance method and commercial tools. The thermal method significantly improves the computational efficiency and reduces the memory usage. Then, we analyze the electrical characteristics of a typical low dropout (LDO) and model the complete 2.5-D PDN, including interposers, chiplets, IVRs, through-silicon vias (TSVs), bumps, decoupling capacitors, and other components. The electrical and thermal problems in the 2.5-D system are formulated and a Metropolis rule-based algorithm is used to derive optimal solutions. Finally, the optimal placement schemes and parameter settings are iterated under different constraints. This method allows for the adjustment of target impedance, noise current, thermal limit, and other constraints based on varying practical situations. In the time-domain analysis, it can be found that the capacitance value is reduced while maintaining the power supply performance. With high accuracy in thermal and electrical modeling, this work provides an in-depth reference for the co-design of chiplet-based 2.5-D ICs.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"627-637"},"PeriodicalIF":2.8,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TVLSI.2024.3477717
Weihao Wang;Kong-Pang Pun
Wide bandwidth and power-area efficient front-ends are required in emerging implantable biosensor applications, e.g., wireless artificial vision systems for the limited vision. This work presents a low-power 0.031 mm$^{2}~3$ -MHz bandwidth noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) tailored for implantable biosensor applications. A highly energy- and area-efficient reset-free residue-processing scheme is proposed. This scheme facilitates noise transfer function (NTF) optimization by enabling control over complex poles. It establishes a unique auxiliary feedback path from the infinite impulse response (IIR) back to the finite impulse response (FIR) by eliminating the need for the FIR filter’s reset phase. This auxiliary feedback loop, which could not be achieved in previous FIR-IIR structures, is a key enabler for achieving high energy efficiency and design flexibility. The in-band quantization noise suppression is boosted by the proposed complex conjugate poles optimization technique, while a low $kT/C$ input-referred noise has resulted. The prototype, fabricated in 65-nm CMOS technology with a 7-bit digital-to-analog converter (DAC), consumes $370~mu $ W from a 1-V supply and occupies an active area of only $0.17times 0.18$ mm (0.031-mm2). Operating at an 80-MHz oversampling frequency, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 70.2 dB over a 3 MHz bandwidth, demonstrating its small area, high efficiency, and high performance for implantable biosensor applications that require high data rates.
{"title":"An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop","authors":"Weihao Wang;Kong-Pang Pun","doi":"10.1109/TVLSI.2024.3477717","DOIUrl":"https://doi.org/10.1109/TVLSI.2024.3477717","url":null,"abstract":"Wide bandwidth and power-area efficient front-ends are required in emerging implantable biosensor applications, e.g., wireless artificial vision systems for the limited vision. This work presents a low-power 0.031 mm<inline-formula> <tex-math>$^{2}~3$ </tex-math></inline-formula>-MHz bandwidth noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) tailored for implantable biosensor applications. A highly energy- and area-efficient reset-free residue-processing scheme is proposed. This scheme facilitates noise transfer function (NTF) optimization by enabling control over complex poles. It establishes a unique auxiliary feedback path from the infinite impulse response (IIR) back to the finite impulse response (FIR) by eliminating the need for the FIR filter’s reset phase. This auxiliary feedback loop, which could not be achieved in previous FIR-IIR structures, is a key enabler for achieving high energy efficiency and design flexibility. The in-band quantization noise suppression is boosted by the proposed complex conjugate poles optimization technique, while a low <inline-formula> <tex-math>$kT/C$ </tex-math></inline-formula> input-referred noise has resulted. The prototype, fabricated in 65-nm CMOS technology with a 7-bit digital-to-analog converter (DAC), consumes <inline-formula> <tex-math>$370~mu $ </tex-math></inline-formula>W from a 1-V supply and occupies an active area of only <inline-formula> <tex-math>$0.17times 0.18$ </tex-math></inline-formula> mm (0.031-mm2). Operating at an 80-MHz oversampling frequency, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 70.2 dB over a 3 MHz bandwidth, demonstrating its small area, high efficiency, and high performance for implantable biosensor applications that require high data rates.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 3","pages":"685-696"},"PeriodicalIF":2.8,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TVLSI.2024.3477632
Dongkwun Kim;Zhaoqing Wang;Paul Xuanyuanliang Huang;Pavan Kumar Chundi;Suhwan Kim;Andrés A. Blanco;Ram K. Krishnamurthy;Mingoo Seok
This article presents a Li-ion battery-compatible single-inductor-multiple-output (SIMO) buck converter that fulfills the power management need of an integrated sub-mW RISC-V microprocessor. The proposed converter can directly take a 4.2-V battery voltage and produce four power rails ranging from 1.8 V for I/O to 0.5 V for the processor core. The three-level input stage is chosen to reduce the inductor ripple size and switching loss, thus increasing power conversion efficiency (PCE). In addition, the fully digital implementation using novel domino flash analog-digital converters (ADCs) enables low static current. Also, pulse frequency modulation (PFM) results in a wide dynamic range. The proposed three-level SIMO converter has been prototyped in a 65-nm CMOS technology with the 32-bit RISC-V processor. Measurement results show that the converter achieves a $1000times $