Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312908
Hyunwook Park, Minsu Kim, Subin Kim, Seungtaek Jeong, Seongguk Kim, Hyungmin Kang, Keunwoo Kim, Keeyoung Son, Gapyeol Park, Kyungjune Son, Taein Shin, Joungho Kim
In this paper, we first propose a policy gradient reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for 2.5-D/3-D integrated circuits (ICs) using a transformer network. The proposed method can provide an optimal decap design that meets target impedance. Unlike previous value-based RL methods with simple value approximators such as multi-layer perceptron (MLP) and convolutional neural network (CNN), the proposed method directly parameterizes policy using an attention-based transformer network model. The model is trained through the policy gradient algorithm so that it can achieve larger action space, i.e. search space. For verification, we applied the proposed method to a test hierarchical power distribution network (PDN). We compared convergence results depending on the action space with the previous value-based RL method. As a result, it is validated that the proposed method can cover ×4 times larger action space than that of the previous work.
在本文中，我们首先提出了一种基于策略梯度强化学习(RL)的2.5 d /3-D集成电路(ic)的最佳去耦电容(decap)设计方法，该方法使用变压器网络。该方法可以提供满足目标阻抗的最优封装设计。与以往基于值的RL方法使用简单的值逼近器(如多层感知器(MLP)和卷积神经网络(CNN))不同，该方法使用基于注意力的变压器网络模型直接参数化策略。通过策略梯度算法对模型进行训练，使其达到更大的动作空间，即搜索空间。为了验证，我们将该方法应用于一个测试的分层配电网络(PDN)。我们将基于动作空间的收敛结果与之前基于值的RL方法进行了比较。结果验证了所提方法覆盖的动作空间比以往的工作大×4倍。
{"title":"Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network","authors":"Hyunwook Park, Minsu Kim, Subin Kim, Seungtaek Jeong, Seongguk Kim, Hyungmin Kang, Keunwoo Kim, Keeyoung Son, Gapyeol Park, Kyungjune Son, Taein Shin, Joungho Kim","doi":"10.1109/EDAPS50281.2020.9312908","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312908","url":null,"abstract":"In this paper, we first propose a policy gradient reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for 2.5-D/3-D integrated circuits (ICs) using a transformer network. The proposed method can provide an optimal decap design that meets target impedance. Unlike previous value-based RL methods with simple value approximators such as multi-layer perceptron (MLP) and convolutional neural network (CNN), the proposed method directly parameterizes policy using an attention-based transformer network model. The model is trained through the policy gradient algorithm so that it can achieve larger action space, i.e. search space. For verification, we applied the proposed method to a test hierarchical power distribution network (PDN). We compared convergence results depending on the action space with the previous value-based RL method. As a result, it is validated that the proposed method can cover ×4 times larger action space than that of the previous work.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130423209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312885
W. Lai
This article introduces a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with analog front-end and optical front-end circuit to detect biomedical signal for electroencephalography (EEG) applications. The proposed integrated design is 16-bit SAR ADC that achieves exceptional performance while consuming very low consumption and high dynamic range (DR) in parallel two pairs of 8-bit SAR ADC with SC low-pass filter. The dynamic comparator contains an asynchronous control sampling switches between high and low potential to internally proposed the timing source to optimizing dissipation of half comparator and digital circuit. The average switching energy and total capacitance are reduced.
{"title":"SAR ADC with Optical Frontend for Biosensor Applications","authors":"W. Lai","doi":"10.1109/EDAPS50281.2020.9312885","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312885","url":null,"abstract":"This article introduces a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with analog front-end and optical front-end circuit to detect biomedical signal for electroencephalography (EEG) applications. The proposed integrated design is 16-bit SAR ADC that achieves exceptional performance while consuming very low consumption and high dynamic range (DR) in parallel two pairs of 8-bit SAR ADC with SC low-pass filter. The dynamic comparator contains an asynchronous control sampling switches between high and low potential to internally proposed the timing source to optimizing dissipation of half comparator and digital circuit. The average switching energy and total capacitance are reduced.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132229739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312892
M. Sahoo, D. Gope
The excessive time and memory requirement for a 3D full-wave solver is a challenge in simulation for signal integrity. This paper presents a hybrid 2D-3D electromagnetic full-wave simulator based on automated segmentation of layout. The novelty of this work is primarily in the classification of segments of layout as 2D or 3D segments using corner points and analysis of the electric field profile. An appropriate error metric is defined and is used in the process of this classification. Finally, cascading studies are performed using different port-structures for concatenating segments to get the overall response. Numerical results for a differential pair is presented with near-end crosstalk (NEXT) and far-end crosstalk (FEXT) to illustrate the time versus accuracy merits.
{"title":"NEXT & FEXT Prediction using Hybrid 2D-3D Solver for Fast Electromagnetic Analysis","authors":"M. Sahoo, D. Gope","doi":"10.1109/EDAPS50281.2020.9312892","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312892","url":null,"abstract":"The excessive time and memory requirement for a 3D full-wave solver is a challenge in simulation for signal integrity. This paper presents a hybrid 2D-3D electromagnetic full-wave simulator based on automated segmentation of layout. The novelty of this work is primarily in the classification of segments of layout as 2D or 3D segments using corner points and analysis of the electric field profile. An appropriate error metric is defined and is used in the process of this classification. Finally, cascading studies are performed using different port-structures for concatenating segments to get the overall response. Numerical results for a differential pair is presented with near-end crosstalk (NEXT) and far-end crosstalk (FEXT) to illustrate the time versus accuracy merits.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new high performance maritime rescue antenna is presented, including VHF, UHF and GPS bands in buoy miniaturization environment. By using innovative method of coaxial design, each of their desired radiation pattern and return loss are achieved. Specially, two VHF antennas, with 10dB impedance bandwidth of 4% (155-162MHz) and 8% (230-250MHz) respectively, port isolation of 15dBi are carefully designed. Meanwhile, the gain of VHF antennas is greater than 2dBi in elevation plane and the variation less than 1dBi in azimuthal plane. Circularly polarized UHF antenna achieves the wide beamwidth of 120 degrees at 406MHz, under the gain of 4.5dBi in elevation plane and axis ratio less than 3dBi with quadrifilar spiral inverted-F structure and shorted stub. GPS antenna is in the form of microstrip patch, which has good radiation characteristics. All antennas are finally verified by both simulations and measurements, showing their great potential applications in maritime rescue system.
{"title":"A New High Performance Miniaturization Antenna for VHF/UHF/GPS Maritime Application","authors":"Chen Chen, Hong-li Peng, Shih-Yu Sun, Ming-Ming Li, Ya-Bin Li, Qingmian Wan","doi":"10.1109/EDAPS50281.2020.9312902","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312902","url":null,"abstract":"A new high performance maritime rescue antenna is presented, including VHF, UHF and GPS bands in buoy miniaturization environment. By using innovative method of coaxial design, each of their desired radiation pattern and return loss are achieved. Specially, two VHF antennas, with 10dB impedance bandwidth of 4% (155-162MHz) and 8% (230-250MHz) respectively, port isolation of 15dBi are carefully designed. Meanwhile, the gain of VHF antennas is greater than 2dBi in elevation plane and the variation less than 1dBi in azimuthal plane. Circularly polarized UHF antenna achieves the wide beamwidth of 120 degrees at 406MHz, under the gain of 4.5dBi in elevation plane and axis ratio less than 3dBi with quadrifilar spiral inverted-F structure and shorted stub. GPS antenna is in the form of microstrip patch, which has good radiation characteristics. All antennas are finally verified by both simulations and measurements, showing their great potential applications in maritime rescue system.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128774074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312922
Shinyoung Park, Seongsoo Lee, Boogyo Sim, Keeyoung Son, Jonghoon J. Kim, Joungho Kim, Seung Woo Woo, Mun Sung Choi, Jung Jae Lee, Jihyung Kim, Jungnan Ryu
In this paper, for the first time, we propose a noise suppression scheme for automotive controller area networks with flexible data rate (CAN-FD) networks that is using series damping resistor-equipped joint connectors (JCs). A CAN-FD is a bus protocol that allows multiple electrical control units (ECUs) to cross-communicate. Signal reflections at the numerous nodes and branches propagate across the entire network and considerably reduce the signal integrity of the communication. The resistors installed in series with signal pins of JCs can attenuate the signal reflection at the expense of DC power loss. We extracted S-parameter models of interconnects of a CAN-FD network, i.e., twisted pair cables, JCs, and configured them with ECU circuit models. We ran time-domain simulations, and evaluated the performance of the JCs by observing the eye diagrams between the ECUs. By equipping optimal size of resistors, the JCs could improve the width of the eye diagrams compared to the JCs without series damping resistors with an expense of DC margin.
{"title":"Signal Integrity Analysis of Automotive CAN-FD Networks with Series Damping Resistor-Equipped Joint Connectors","authors":"Shinyoung Park, Seongsoo Lee, Boogyo Sim, Keeyoung Son, Jonghoon J. Kim, Joungho Kim, Seung Woo Woo, Mun Sung Choi, Jung Jae Lee, Jihyung Kim, Jungnan Ryu","doi":"10.1109/EDAPS50281.2020.9312922","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312922","url":null,"abstract":"In this paper, for the first time, we propose a noise suppression scheme for automotive controller area networks with flexible data rate (CAN-FD) networks that is using series damping resistor-equipped joint connectors (JCs). A CAN-FD is a bus protocol that allows multiple electrical control units (ECUs) to cross-communicate. Signal reflections at the numerous nodes and branches propagate across the entire network and considerably reduce the signal integrity of the communication. The resistors installed in series with signal pins of JCs can attenuate the signal reflection at the expense of DC power loss. We extracted S-parameter models of interconnects of a CAN-FD network, i.e., twisted pair cables, JCs, and configured them with ECU circuit models. We ran time-domain simulations, and evaluated the performance of the JCs by observing the eye diagrams between the ECUs. By equipping optimal size of resistors, the JCs could improve the width of the eye diagrams compared to the JCs without series damping resistors with an expense of DC margin.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312890
K. Shiba, Tatsuo Omori, Mitsuji Okada, M. Hamada, T. Kuroda
This paper conducts an in-depth analysis of crosstalk in a multi-hop inductive coupling interface for a 3D-stacked memory and proposes two countermeasures. The crosstalk among seven stacked dies is analyzed based on 3D electromagnetic (EM) simulation. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress theses crosstalk, this work proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of the shorted coils and 8-shaped coils improves area-efficiency by a factor of 4 in simulation. These techniques enable a high-density inducive coupling interface for a high-bandwidth stacked memory.
{"title":"Crosstalk Analysis and Countermeasures of High-Density Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory","authors":"K. Shiba, Tatsuo Omori, Mitsuji Okada, M. Hamada, T. Kuroda","doi":"10.1109/EDAPS50281.2020.9312890","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312890","url":null,"abstract":"This paper conducts an in-depth analysis of crosstalk in a multi-hop inductive coupling interface for a 3D-stacked memory and proposes two countermeasures. The crosstalk among seven stacked dies is analyzed based on 3D electromagnetic (EM) simulation. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress theses crosstalk, this work proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of the shorted coils and 8-shaped coils improves area-efficiency by a factor of 4 in simulation. These techniques enable a high-density inducive coupling interface for a high-bandwidth stacked memory.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124836921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312899
Ruei-Jhe Liu, Chiu-Chih Chou, Tzong-Lin Wu
An improved transmission/reflection method for high DK, DF liquid material is proposed. The conventional T/R method often requires a nearly-matched transmission line feeding, which is difficult to realize in high DK liquids. To overcome this problem, in this paper we propose a reference impedance transform technique based on the concept of pseudo-wave. The transformed S parameters will then exhibit better transmission due to better (virtual) matching. In addition, a time-gating method is proposed to solve the resulting equations and obtain smoother complex permittivity w.r.t. frequency. Experiments are conducted to verify the proposed method.
{"title":"An Improved Method of Finding Complex Permittivity of Lossy Liquids","authors":"Ruei-Jhe Liu, Chiu-Chih Chou, Tzong-Lin Wu","doi":"10.1109/EDAPS50281.2020.9312899","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312899","url":null,"abstract":"An improved transmission/reflection method for high DK, DF liquid material is proposed. The conventional T/R method often requires a nearly-matched transmission line feeding, which is difficult to realize in high DK liquids. To overcome this problem, in this paper we propose a reference impedance transform technique based on the concept of pseudo-wave. The transformed S parameters will then exhibit better transmission due to better (virtual) matching. In addition, a time-gating method is proposed to solve the resulting equations and obtain smoother complex permittivity w.r.t. frequency. Experiments are conducted to verify the proposed method.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124745250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312918
Chiu-Chih Chou, Thong Nguyen, J. Schutt-Ainé
The first step in Loewner matrix macromodeling is to partition the data into two parts. Previous research has shown that different partition schemes, although theoretically equivalent, may significantly affect matrix condition numbers. The impact of such ill-conditioning on the frequency and time domain responses of the macromodel, however, has been less addressed in the literature. In this paper, we clarify the importance of good conditioning for an accurate modeling in frequency and time domains, and compare different partition schemes using simulated and measured S parameters. The results demonstrate that with the bad schemes, the practically allowable bandwidth of the model will be greatly limited.
{"title":"Impact of Partition Schemes in Loewner Matrix Macromodeling","authors":"Chiu-Chih Chou, Thong Nguyen, J. Schutt-Ainé","doi":"10.1109/EDAPS50281.2020.9312918","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312918","url":null,"abstract":"The first step in Loewner matrix macromodeling is to partition the data into two parts. Previous research has shown that different partition schemes, although theoretically equivalent, may significantly affect matrix condition numbers. The impact of such ill-conditioning on the frequency and time domain responses of the macromodel, however, has been less addressed in the literature. In this paper, we clarify the importance of good conditioning for an accurate modeling in frequency and time domains, and compare different partition schemes using simulated and measured S parameters. The results demonstrate that with the bad schemes, the practically allowable bandwidth of the model will be greatly limited.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134390576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312912
Michael Chang
This paper introduces a methodology to co-design on-chip linear dropout regulator (LDO) with power distribution network of package and PCB board based on Laplace transform method. A practical methodology demonstrates the effectiveness and the efficiency of the Laplace model in the time domain and is derived that takes into account LDO-PDN system impedance response. LDO pass transistor size and output decoupling capacitor optimization flow is proposed to meet the system voltage noise requirements. The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.
{"title":"Power Distribution Network Optimization for On-Die Regulator with Laplace Transform Technique","authors":"Michael Chang","doi":"10.1109/EDAPS50281.2020.9312912","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312912","url":null,"abstract":"This paper introduces a methodology to co-design on-chip linear dropout regulator (LDO) with power distribution network of package and PCB board based on Laplace transform method. A practical methodology demonstrates the effectiveness and the efficiency of the Laplace model in the time domain and is derived that takes into account LDO-PDN system impedance response. LDO pass transistor size and output decoupling capacitor optimization flow is proposed to meet the system voltage noise requirements. The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312884
Vinod Arjun Huddar
In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.
{"title":"On Die SSN Methodology for High Speed IO","authors":"Vinod Arjun Huddar","doi":"10.1109/EDAPS50281.2020.9312884","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312884","url":null,"abstract":"In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116259123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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