Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312911
Trinadhachari Kosuru, Janani Swaminathan, G. Tressler, Preetham Raghavendra, Krishna Thangaraj, Steve Wilson, Tom Kroetsch, A. Lingambudi, Navya Chaitanya Gogula
Spin Torque Transfer Magneto-resistive Random-Access Memory (STT-MRAM) is a type of non-volatile memory that stores data in magnetic domains. It is a very interesting market space that STT-MRAM will support, trying to take the best of both worlds, the ever fast paced DRAM with scaling challenges and the non-volatile world of Flash with latency challenges. Initial setup, bring-up and endurance characterization of the STT-MRAM device are summarized. An overview of the tester-board design, along with the endurance characterization methodology and test results are discussed. Learning shared to introduce and educate about STT-MRAM bring-up and help future system designs using STT-MRAM. STT-MRAM is not as scalable as DRAM or Flash but has high potential based on its performance and persistence characteristics.
{"title":"STT-MRAM Endurance Characterization For Enterprise Systems","authors":"Trinadhachari Kosuru, Janani Swaminathan, G. Tressler, Preetham Raghavendra, Krishna Thangaraj, Steve Wilson, Tom Kroetsch, A. Lingambudi, Navya Chaitanya Gogula","doi":"10.1109/EDAPS50281.2020.9312911","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312911","url":null,"abstract":"Spin Torque Transfer Magneto-resistive Random-Access Memory (STT-MRAM) is a type of non-volatile memory that stores data in magnetic domains. It is a very interesting market space that STT-MRAM will support, trying to take the best of both worlds, the ever fast paced DRAM with scaling challenges and the non-volatile world of Flash with latency challenges. Initial setup, bring-up and endurance characterization of the STT-MRAM device are summarized. An overview of the tester-board design, along with the endurance characterization methodology and test results are discussed. Learning shared to introduce and educate about STT-MRAM bring-up and help future system designs using STT-MRAM. STT-MRAM is not as scalable as DRAM or Flash but has high potential based on its performance and persistence characteristics.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133839536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Signal Integrity analysis for an I/O forms an integral part of high-speed design. Complex routing on the package, board and passive components degrade the signal quality. End to End simulation using highly corelated IBIS AMI models including S parameter models are the need for the day for validating the link simulation. USB4 & TBT3 are the next-generation USB data specification that increases the bandwidth of the interface and allows other protocols to share the physical interface. Doubling the data rate for every generation 5Gbps - 10Gbps – 20Gbps also doubles the Nyquist frequency making frequency dependent insertion losses worse. In addition, increased capacitive coupling at higher frequencies adds more interference or noise to the signal, making the crosstalk worse than it was in USB3.0/1/2 channels. This paper provides the challenges & solutions for on-die & platform to meet the electrical compliance requirements of I/O and talks on generating IBIS-AMI (Algorithmic Modeling Interface) models for 20Gbps PHY with the system.
{"title":"Signal Integrity Challenges and Solutions for USB4 and TBT3 Protocols","authors":"Aruna Bathini, Manjunath Jayasimha, Deepak Nagaraj","doi":"10.1109/EDAPS50281.2020.9312883","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312883","url":null,"abstract":"Signal Integrity analysis for an I/O forms an integral part of high-speed design. Complex routing on the package, board and passive components degrade the signal quality. End to End simulation using highly corelated IBIS AMI models including S parameter models are the need for the day for validating the link simulation. USB4 & TBT3 are the next-generation USB data specification that increases the bandwidth of the interface and allows other protocols to share the physical interface. Doubling the data rate for every generation 5Gbps - 10Gbps – 20Gbps also doubles the Nyquist frequency making frequency dependent insertion losses worse. In addition, increased capacitive coupling at higher frequencies adds more interference or noise to the signal, making the crosstalk worse than it was in USB3.0/1/2 channels. This paper provides the challenges & solutions for on-die & platform to meet the electrical compliance requirements of I/O and talks on generating IBIS-AMI (Algorithmic Modeling Interface) models for 20Gbps PHY with the system.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132290551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312891
Kyungjune Son, Minsu Kim, Hyunwook Park, Shinyoung Park, Gapyeol Park, Daewhan Lho, Seoungguk Kim, Taein Shin, Keeyoung Son, Keunwoo Kim, Joungho Kim
In this paper, we, for the first time, proposed the Reinforcement Learning (RL) based interconnection design for 3D X-Point array structure considering crosstalk and IR drop. We applied the Markov Decision Process (MDP) to correspond to finding the optimal interconnection design problem to RL problem. We defined interconnection state to the vector, design to the action and the number of bits, crosstalk and IR drop are considered as the reward. The Proximal Policy Optimization (PPO) and Long Short-Term Memory (LSTM) are used to RL algorithms. The proposed interconnection design model is well trained and shows convergence of reward score in 16×16, 32×32 and 64×64 cases. We verified that the trained model finds out optimal interconnection design considering both memory size and signal integrity issues.
{"title":"Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity","authors":"Kyungjune Son, Minsu Kim, Hyunwook Park, Shinyoung Park, Gapyeol Park, Daewhan Lho, Seoungguk Kim, Taein Shin, Keeyoung Son, Keunwoo Kim, Joungho Kim","doi":"10.1109/EDAPS50281.2020.9312891","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312891","url":null,"abstract":"In this paper, we, for the first time, proposed the Reinforcement Learning (RL) based interconnection design for 3D X-Point array structure considering crosstalk and IR drop. We applied the Markov Decision Process (MDP) to correspond to finding the optimal interconnection design problem to RL problem. We defined interconnection state to the vector, design to the action and the number of bits, crosstalk and IR drop are considered as the reward. The Proximal Policy Optimization (PPO) and Long Short-Term Memory (LSTM) are used to RL algorithms. The proposed interconnection design model is well trained and shows convergence of reward score in 16×16, 32×32 and 64×64 cases. We verified that the trained model finds out optimal interconnection design considering both memory size and signal integrity issues.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127553028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312895
Daehwan Lho, Hyunwook Park, Seongguk Kim, Taein Shin, Keunwoo Kim, Kyungjune Son, Hyungmin Kang, Boogyo Sim, Keeyoung Son, Minsu Kim, Joungho Kim
Usually, modeling takes a long time because it depends on the engineer's experience and is done through repetitive tuning. In this paper, we propose a deep neural network (DNN)-based lumped circuit modeling method using an impedance curve. The proposed method provides a fast and accurate electrical circuit model of inductance (L), capacitance (C), and conductance (G) using a DNN. Since the LCG parameters are predicted by the impedance curve, it is flexible for various applications. For accurately predicting lumped circuit parameters, the DNN model is designed and trained through various case studies. As a result, the proposed method predicts 100% accuracy in inductance and conductance, and 92% accuracy in capacitance. In other words, the proposed method successfully models the electrical characteristics of various applications.
{"title":"Deep Neural Network-based Lumped Circuit Modeling using Impedance Curve","authors":"Daehwan Lho, Hyunwook Park, Seongguk Kim, Taein Shin, Keunwoo Kim, Kyungjune Son, Hyungmin Kang, Boogyo Sim, Keeyoung Son, Minsu Kim, Joungho Kim","doi":"10.1109/EDAPS50281.2020.9312895","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312895","url":null,"abstract":"Usually, modeling takes a long time because it depends on the engineer's experience and is done through repetitive tuning. In this paper, we propose a deep neural network (DNN)-based lumped circuit modeling method using an impedance curve. The proposed method provides a fast and accurate electrical circuit model of inductance (L), capacitance (C), and conductance (G) using a DNN. Since the LCG parameters are predicted by the impedance curve, it is flexible for various applications. For accurately predicting lumped circuit parameters, the DNN model is designed and trained through various case studies. As a result, the proposed method predicts 100% accuracy in inductance and conductance, and 92% accuracy in capacitance. In other words, the proposed method successfully models the electrical characteristics of various applications.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116524697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312903
S. Chen, A. Tajalli
This work presents a comparative study, analyzing performance of NRZ (Non-Return-to-Zero), PAM4 (Pulse Amplitude Modulation of 4-level), PAM3, and ENRZ (Ensemble NRZ) in terms of sensitivity to channel loss. The advantageous of each signaling scheme based on residual eye opening are being discussed.
{"title":"Link Performance Comparison based on Insertion Loss: NRZ, PAM3, PAM4, and ENRZ","authors":"S. Chen, A. Tajalli","doi":"10.1109/EDAPS50281.2020.9312903","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312903","url":null,"abstract":"This work presents a comparative study, analyzing performance of NRZ (Non-Return-to-Zero), PAM4 (Pulse Amplitude Modulation of 4-level), PAM3, and ENRZ (Ensemble NRZ) in terms of sensitivity to channel loss. The advantageous of each signaling scheme based on residual eye opening are being discussed.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126590442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312921
Siddhesh Arote, Manjunath Jayasimha
Power supply noise budget is scaled for High speed I/O Interfaces like PCIE-Gen5/6. The specification for power supply noise has become tighter and even variation of few mV is considered crucial for high speed I/O interfaces. Presently a 2.5D extraction tool is used for modelling Power delivery network interconnects for Package/Mother board. With data rates increasing, 2.5D tool lacks accuracy & there is a definite need for 3D modelling for improving the quality of the output to meet the ever-growing High speed I/Os (input output). Relying on 2.5D models can lead to pessimistic decoupling solution. The work in this paper mainly focuses on accurate interconnect modelling of Package/Motherboard using a 3-D field solver tool & also provides the impact on HSIO power supply noise and summarizes the need for this methodology upgrade. Also, paper discusses on how 3D PDN models helps design resources (SOC, PKG, BRD) to be optimized only to the most sensitive areas, thereby reducing the overall PDN resource cost.
{"title":"Is There a need for 3D modelling for a Power Delivery Network on Package?","authors":"Siddhesh Arote, Manjunath Jayasimha","doi":"10.1109/EDAPS50281.2020.9312921","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312921","url":null,"abstract":"Power supply noise budget is scaled for High speed I/O Interfaces like PCIE-Gen5/6. The specification for power supply noise has become tighter and even variation of few mV is considered crucial for high speed I/O interfaces. Presently a 2.5D extraction tool is used for modelling Power delivery network interconnects for Package/Mother board. With data rates increasing, 2.5D tool lacks accuracy & there is a definite need for 3D modelling for improving the quality of the output to meet the ever-growing High speed I/Os (input output). Relying on 2.5D models can lead to pessimistic decoupling solution. The work in this paper mainly focuses on accurate interconnect modelling of Package/Motherboard using a 3-D field solver tool & also provides the impact on HSIO power supply noise and summarizes the need for this methodology upgrade. Also, paper discusses on how 3D PDN models helps design resources (SOC, PKG, BRD) to be optimized only to the most sensitive areas, thereby reducing the overall PDN resource cost.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131620662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312904
Mohamed Sahouli, A. Dounavis
This paper presents a passive correction technique using the Loewner matrix (LM) algorithm for modeling distributed circuits characterized by frequency-domain data. A methodology is described based on a frequency point selection technique, which increases the likelihood that the reduced Loewner matrices form a passive system. This process of adding data points to correct passivity is repeated until the LM model is passive. A numerical example is provided to illustrate the validity of the proposed work.
{"title":"Iterative Loewner Matrix Passivity Correction Technique","authors":"Mohamed Sahouli, A. Dounavis","doi":"10.1109/EDAPS50281.2020.9312904","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312904","url":null,"abstract":"This paper presents a passive correction technique using the Loewner matrix (LM) algorithm for modeling distributed circuits characterized by frequency-domain data. A methodology is described based on a frequency point selection technique, which increases the likelihood that the reduced Loewner matrices form a passive system. This process of adding data points to correct passivity is repeated until the LM model is passive. A numerical example is provided to illustrate the validity of the proposed work.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132771669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312905
Rahul Kumar, B. Kumari, Somesh Kumar, Manodipan Sahoo, Rohit Sharma
To exploit the superior performance of copper and graphene interconnects, hybrid interconnects are seen as a promising interconnect technology for future technology nodes. Dielectric surface roughness is a process induced phenomenon that affects the performance of the interconnects. This paper presents an in-depth investigation on the impact of temperature and dielectric surface roughness on performance parameters of Cu-Graphene hybrid interconnects.
{"title":"Temperature and Dielectric Surface Roughness dependent Performance Analysis of Cu-Graphene Hybrid Interconnects","authors":"Rahul Kumar, B. Kumari, Somesh Kumar, Manodipan Sahoo, Rohit Sharma","doi":"10.1109/EDAPS50281.2020.9312905","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312905","url":null,"abstract":"To exploit the superior performance of copper and graphene interconnects, hybrid interconnects are seen as a promising interconnect technology for future technology nodes. Dielectric surface roughness is a process induced phenomenon that affects the performance of the interconnects. This paper presents an in-depth investigation on the impact of temperature and dielectric surface roughness on performance parameters of Cu-Graphene hybrid interconnects.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"52 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312920
I. Erdin, R. Achar
A Newton-Raphson (N-R) based method is developed for performance evaluation of power delivery networks (PDN) with arbitrarily shaped parallel-plate power/ground plane pairs. The proposed method allows for PI assessment in a few iteration steps while providing significant computational efficiency compared to alternative methods. The proposed method is tested on a practical example and the results are observed in good agreement with those obtained from a numerical electromagnetic (EM) simulator.
{"title":"Fast Power Integrity Analysis of PDNs with Arbitrarily Shaped Power-Ground Plane Pairs","authors":"I. Erdin, R. Achar","doi":"10.1109/EDAPS50281.2020.9312920","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312920","url":null,"abstract":"A Newton-Raphson (N-R) based method is developed for performance evaluation of power delivery networks (PDN) with arbitrarily shaped parallel-plate power/ground plane pairs. The proposed method allows for PI assessment in a few iteration steps while providing significant computational efficiency compared to alternative methods. The proposed method is tested on a practical example and the results are observed in good agreement with those obtained from a numerical electromagnetic (EM) simulator.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132349562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-14DOI: 10.1109/EDAPS50281.2020.9312906
Keunwoo Kim, Hyunwook Park, Daehwan Lho, Minsu Kim, Keeyoung Son, Kyungjune Son, Seongguk Kim, Taein Shin, Seonguk Choi, Joungho Kim
In this paper, we propose the through silicon via (TSV) array design optimization method using deep reinforcement learning (DRL) framework. The agent trained through the proposed method can provide an optimal TSV array that minimizes far-end crosstalk (FEXT) in one single step. We define the state, action, and reward that are elements of the Markov Decision Process (MDP) for optimizing the TSV array considering FEXT and train a deep q network (DQN) agent. For verification, we applied the proposed method to a 3 by 3 through silicon via array at stacked DRAM of High Bandwidth Memory (HBM). The network converged well, and as the result, the proposed method provided the optimal design that satisfies the target FEXT in which 3 dB lower than the initial design.
{"title":"Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk","authors":"Keunwoo Kim, Hyunwook Park, Daehwan Lho, Minsu Kim, Keeyoung Son, Kyungjune Son, Seongguk Kim, Taein Shin, Seonguk Choi, Joungho Kim","doi":"10.1109/EDAPS50281.2020.9312906","DOIUrl":"https://doi.org/10.1109/EDAPS50281.2020.9312906","url":null,"abstract":"In this paper, we propose the through silicon via (TSV) array design optimization method using deep reinforcement learning (DRL) framework. The agent trained through the proposed method can provide an optimal TSV array that minimizes far-end crosstalk (FEXT) in one single step. We define the state, action, and reward that are elements of the Markov Decision Process (MDP) for optimizing the TSV array considering FEXT and train a deep q network (DQN) agent. For verification, we applied the proposed method to a 3 by 3 through silicon via array at stacked DRAM of High Bandwidth Memory (HBM). The network converged well, and as the result, the proposed method provided the optimal design that satisfies the target FEXT in which 3 dB lower than the initial design.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133218195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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