Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548900
Jin-Fu Li, Cheng-Wen Wu, M. Aoyagi, Meng-Fan Chang, D. Kwai
Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. This may shorten the global interconnects of a 3D IC and greatly improve its performance and power consumption. High bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduce the unnecessary waste of energy during data movement. In addition, the 3D integration technology shows other advantages over 2D technology, such as high functionality, heterogeneous integration, small form factor, etc. However, there are still challenges that need to be tackled before volume production of 3D ICs using TSV becomes possible, including technology scalability, quality and reliability, yield, thermal management, equipment and infrastructure, and costs. To demonstrate the feasibility of 3D-IC technologies, many academic and industrial institutes have been working on various test vehicles, especially in recent years. An increasing attention also has been attracted around the world in the semiconductor industry by the development of related technologies. In this special session, we will discuss the evolutionary efforts toward the realization of 3-D ICs. As memory dies need to be integrated in most 3D-IC system, we will also address the challenges in the design and test of 3D memories against cross-layer process, voltage and temperature variations while suppressing thermal effect and power consumption, etc. We will share our experiences and show results from some of the test vehicles we have worked on, including processor/memory stacks, analog/logic stacks, logic/logic stacks, etc. We will show a 1,024-bit wide bus chip-to-chip interconnection using 40×40 fine-pitch TSVs to demonstrate ultra-low-power operation. For memories, we will present a 3D-RAM structure using small voltage-swing TSVs, vertical-device-stacking nonvolatile-SRAM and ReRAM, and a 3D vertical-gate NAND flash. To address the challenge of reliability and yield, we will also discuss important test techniques. Demonstration of benefits provided by 3D integration technology will also be shown. Last but not least, we will describe our development plan regarding various types of die stacking using heterogeneous process integration, especially processor/memory stacking that is widely believed to be a key technology in future generations of smart handheld devices.
{"title":"Special session 4C: Hot topic 3D-IC design and test","authors":"Jin-Fu Li, Cheng-Wen Wu, M. Aoyagi, Meng-Fan Chang, D. Kwai","doi":"10.1109/VTS.2013.6548900","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548900","url":null,"abstract":"Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. This may shorten the global interconnects of a 3D IC and greatly improve its performance and power consumption. High bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduce the unnecessary waste of energy during data movement. In addition, the 3D integration technology shows other advantages over 2D technology, such as high functionality, heterogeneous integration, small form factor, etc. However, there are still challenges that need to be tackled before volume production of 3D ICs using TSV becomes possible, including technology scalability, quality and reliability, yield, thermal management, equipment and infrastructure, and costs. To demonstrate the feasibility of 3D-IC technologies, many academic and industrial institutes have been working on various test vehicles, especially in recent years. An increasing attention also has been attracted around the world in the semiconductor industry by the development of related technologies. In this special session, we will discuss the evolutionary efforts toward the realization of 3-D ICs. As memory dies need to be integrated in most 3D-IC system, we will also address the challenges in the design and test of 3D memories against cross-layer process, voltage and temperature variations while suppressing thermal effect and power consumption, etc. We will share our experiences and show results from some of the test vehicles we have worked on, including processor/memory stacks, analog/logic stacks, logic/logic stacks, etc. We will show a 1,024-bit wide bus chip-to-chip interconnection using 40×40 fine-pitch TSVs to demonstrate ultra-low-power operation. For memories, we will present a 3D-RAM structure using small voltage-swing TSVs, vertical-device-stacking nonvolatile-SRAM and ReRAM, and a 3D vertical-gate NAND flash. To address the challenge of reliability and yield, we will also discuss important test techniques. Demonstration of benefits provided by 3D integration technology will also be shown. Last but not least, we will describe our development plan regarding various types of die stacking using heterogeneous process integration, especially processor/memory stacking that is widely believed to be a key technology in future generations of smart handheld devices.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548944
I. Polian, M. Tehranipoor
Integrated circuit counterfeiting is a severe challenge for semiconductor companies, system integrators and product end-users. Substantial revenue losses by individual enterprises as well as detrimental economy-wide effects have triggered significant interest in counterfeit detection and prevention by commercial actors and governments. This resulted in a number of large-scale research initiatives and networks that focus on this topic, in North America, Europe and elsewhere. The hot-topic special session will introduce the test community to counterfeit detection techniques and identify open problems which can be solved using tools and methods from the testing area.
{"title":"Special session 12A: Hot topic counterfeit IC identification: How can test help?","authors":"I. Polian, M. Tehranipoor","doi":"10.1109/VTS.2013.6548944","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548944","url":null,"abstract":"Integrated circuit counterfeiting is a severe challenge for semiconductor companies, system integrators and product end-users. Substantial revenue losses by individual enterprises as well as detrimental economy-wide effects have triggered significant interest in counterfeit detection and prevention by commercial actors and governments. This resulted in a number of large-scale research initiatives and networks that focus on this topic, in North America, Europe and elsewhere. The hot-topic special session will introduce the test community to counterfeit detection techniques and identify open problems which can be solved using tools and methods from the testing area.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122247132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548909
Yue Gao, Yang Zhang, Da Cheng, M. Breuer
Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core level of granularity provides great benefits in yield improvement, but requires additional steering logic and wiring that has a detrimental impact on area and performance. At the other end of the spectrum, coarse-grained core level redundancy can enable spare sharing, but it is only beneficial in highly-parallel GPU architectures. To this end, we will 1) introduce a hybrid spare sharing redundancy insertion scheme that combines the advantages of the above two approaches, while carefully leveraging the associated area and performance overheads, 2) present an extensively verified, systematic scalable model to evaluate the quality of the final design in terms of projected revenue per wafer, and 3) introduce a maximization algorithm to determine the near optimal redundancy configurations during the design stage. Experimental results show that our new design methodology provides more than 15% improvement in revenue per wafer, compared to using existing redundancy insertion techniques.
{"title":"Trading off area, yield and performance via hybrid redundancy in multi-core architectures","authors":"Yue Gao, Yang Zhang, Da Cheng, M. Breuer","doi":"10.1109/VTS.2013.6548909","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548909","url":null,"abstract":"Manufacturing yield is a major concern for modern CMOS technologies. Fortunately, evolving chip architectures such as multi-cores have provided new venues for yield enhancement, and calls for a fresh perspective on the classic method of redundancy insertion. In this paper we outline a new approach towards redundancy insertion in modern multi-core CPU architectures. Traditionally, applying redundancy at a finer intra-core level of granularity provides great benefits in yield improvement, but requires additional steering logic and wiring that has a detrimental impact on area and performance. At the other end of the spectrum, coarse-grained core level redundancy can enable spare sharing, but it is only beneficial in highly-parallel GPU architectures. To this end, we will 1) introduce a hybrid spare sharing redundancy insertion scheme that combines the advantages of the above two approaches, while carefully leveraging the associated area and performance overheads, 2) present an extensively verified, systematic scalable model to evaluate the quality of the final design in terms of projected revenue per wafer, and 3) introduce a maximization algorithm to determine the near optimal redundancy configurations during the design stage. Experimental results show that our new design methodology provides more than 15% improvement in revenue per wafer, compared to using existing redundancy insertion techniques.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548901
P. Das, S. Gupta
All post-silicon tasks - validation, diagnosis, delay testing, and speed-binning - must be carried out by applying vectors to actual chips, and capturing and analyzing responses. Yet, vectors used must be generated and analyzed using pre-silicon models of the circuit. Three comprehensive industrial studies demonstrate that existing approaches for generating such vectors are inadequate, and one major weakness is that existing delay models either do not capture process variations or do not capture advanced delay phenomenon that significantly affect delays. Hence, existing models underestimate the worst case delay leading to selection of non-critical paths and generation of vectors that do not invoke worst case delays. In this paper, we propose a simple notion of bounding approximation and show how it can extend any existing delay model to also capture process variations and to eliminate any underestimation. The main question we investigate is how best to use this approach to select paths and generate or evaluate vectors for post silicon tasks. In particular, we study whether it is better to use this approach to bound simple pin-to-pin delay models or more advanced delay models. At the level of timing analysis, bounded versions of pin-to-pin delay models have lower run-time complexity but looser bounds. However, we conduct path selection for delay testing and vector generation for delay validation and show that bounded versions of more advanced delay models are significantly more efficient in terms of validation cost and runtime complexity.
{"title":"Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning","authors":"P. Das, S. Gupta","doi":"10.1109/VTS.2013.6548901","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548901","url":null,"abstract":"All post-silicon tasks - validation, diagnosis, delay testing, and speed-binning - must be carried out by applying vectors to actual chips, and capturing and analyzing responses. Yet, vectors used must be generated and analyzed using pre-silicon models of the circuit. Three comprehensive industrial studies demonstrate that existing approaches for generating such vectors are inadequate, and one major weakness is that existing delay models either do not capture process variations or do not capture advanced delay phenomenon that significantly affect delays. Hence, existing models underestimate the worst case delay leading to selection of non-critical paths and generation of vectors that do not invoke worst case delays. In this paper, we propose a simple notion of bounding approximation and show how it can extend any existing delay model to also capture process variations and to eliminate any underestimation. The main question we investigate is how best to use this approach to select paths and generate or evaluate vectors for post silicon tasks. In particular, we study whether it is better to use this approach to bound simple pin-to-pin delay models or more advanced delay models. At the level of timing analysis, bounded versions of pin-to-pin delay models have lower run-time complexity but looser bounds. However, we conduct path selection for delay testing and vector generation for delay validation and show that bounded versions of more advanced delay models are significantly more efficient in terms of validation cost and runtime complexity.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125301230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548884
Sreenivaas S. Muthyala, N. Touba
A highly efficient SOC test compression scheme which uses sequential linear decompressors local to each core is proposed. Test data is stored on the tester in compressed form and brought over the TAM to the core before being decompressed. Very high encoding efficiency is achieved by providing the ability to share free variables across test cubes being compressed at the same time as well as in subsequent time steps. The idea of retaining unused non-pivot free variables when decompressing one test cube to help for encoding subsequent test cubes that was introduced in [Muthyala 12] is applied here in the context of SOC testing. It is shown that in this application, a first-in first-out (FIFO) buffer is not required. The ability to retain excess free variables rather than wasting them when the decompressor is reset avoids the need for high precision in matching the number of free variables used for encoding with the number of care bits. This allows greater flexibility in test scheduling to reduce test time, tester storage, and control complexity as indicated by the experimental results.
{"title":"SOC test compression scheme using sequential linear decompressors with retained free variables","authors":"Sreenivaas S. Muthyala, N. Touba","doi":"10.1109/VTS.2013.6548884","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548884","url":null,"abstract":"A highly efficient SOC test compression scheme which uses sequential linear decompressors local to each core is proposed. Test data is stored on the tester in compressed form and brought over the TAM to the core before being decompressed. Very high encoding efficiency is achieved by providing the ability to share free variables across test cubes being compressed at the same time as well as in subsequent time steps. The idea of retaining unused non-pivot free variables when decompressing one test cube to help for encoding subsequent test cubes that was introduced in [Muthyala 12] is applied here in the context of SOC testing. It is shown that in this application, a first-in first-out (FIFO) buffer is not required. The ability to retain excess free variables rather than wasting them when the decompressor is reset avoids the need for high precision in matching the number of free variables used for encoding with the number of care bits. This allows greater flexibility in test scheduling to reduce test time, tester storage, and control complexity as indicated by the experimental results.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114013233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548911
Samed Maltabas, O. Ekekon, Kemal Kulovic, A. Meixner, M. Margala
In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuit's performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.
{"title":"An IDDQ BIST approach to characterize phase-locked loop parameters","authors":"Samed Maltabas, O. Ekekon, Kemal Kulovic, A. Meixner, M. Margala","doi":"10.1109/VTS.2013.6548911","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548911","url":null,"abstract":"In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuit's performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127606211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548888
J. Jeong, S. Ozev, Shreyas Sen, T. M. Mak
Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, the difference in architecture results in differences in potential circuit impairments/fault models, leading to different test/measurement/calibration requirements. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Therefore, measurement and compensation/calibration of these parameters are important to ensure proper operation for the polar transmitter. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth based on the measurement of the 3rd order inter modulation distortion (IMD3) at the output of the transmitter. First, a two-tone input at a sufficiently low frequency is applied to the transmitter baseband input to calculate the delay. Then, we apply another two-tone input at a relatively higher frequency to determine the envelope bandwidth. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately within 10ms which is negligible compared to signal source switching and settling times.
{"title":"Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters","authors":"J. Jeong, S. Ozev, Shreyas Sen, T. M. Mak","doi":"10.1109/VTS.2013.6548888","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548888","url":null,"abstract":"Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, the difference in architecture results in differences in potential circuit impairments/fault models, leading to different test/measurement/calibration requirements. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Therefore, measurement and compensation/calibration of these parameters are important to ensure proper operation for the polar transmitter. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth based on the measurement of the 3rd order inter modulation distortion (IMD3) at the output of the transmitter. First, a two-tone input at a sufficiently low frequency is applied to the transmitter baseband input to calculate the delay. Then, we apply another two-tone input at a relatively higher frequency to determine the envelope bandwidth. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately within 10ms which is negligible compared to signal source switching and settling times.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114765996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548934
Thomas Moon, H. Choi, A. Chatterjee
This paper proposes a new method to reconstruct signal by a monobit receiver based on incoherent subsampling. The proposed method uses a time-variant threshold voltage for the monobit receiver to increase its amplitude resolution. By our methodology, the threshold voltage does not have to be synchronized with the input signal nor the sampling clock of the system. Hardware measurement with FPGA and high-bandwidth clocked-comparators shows that a low-cost multi-channel test is achievable by our method. The hardware measurement results show a square waveform and a sine wave waveform reconstruction.
{"title":"Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling","authors":"Thomas Moon, H. Choi, A. Chatterjee","doi":"10.1109/VTS.2013.6548934","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548934","url":null,"abstract":"This paper proposes a new method to reconstruct signal by a monobit receiver based on incoherent subsampling. The proposed method uses a time-variant threshold voltage for the monobit receiver to increase its amplitude resolution. By our methodology, the threshold voltage does not have to be synchronized with the input signal nor the sampling clock of the system. Hardware measurement with FPGA and high-bandwidth clocked-comparators shows that a low-cost multi-channel test is achievable by our method. The hardware measurement results show a square waveform and a sine wave waveform reconstruction.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122724446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548940
Chih-Sheng Hou, Jin-Fu Li
A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized. To minimize the test and repair time of RAMs in the pre-bond and post-bond test phases, a test scheduling engine is used to determine the pre-bond and post-bond test sequences of RAMs under the corresponding test power constraints. Then, a BISR-circuit minimization algorithm is proposed to reduce the number of required shared BISR circuits for the RAMs under the constraints of pre-bond and post-bond test sequences and distance between the BISR circuit and served RAMs. Simulation results show that in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit), 35% area reduction can be achieved by the shared BISR scheme planned by the proposed allocation technique under lmm distance constraint, and 500mW and 600mW pre-bond and post-bond test power constraints, respectively.
{"title":"Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs","authors":"Chih-Sheng Hou, Jin-Fu Li","doi":"10.1109/VTS.2013.6548940","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548940","url":null,"abstract":"A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized. To minimize the test and repair time of RAMs in the pre-bond and post-bond test phases, a test scheduling engine is used to determine the pre-bond and post-bond test sequences of RAMs under the corresponding test power constraints. Then, a BISR-circuit minimization algorithm is proposed to reduce the number of required shared BISR circuits for the RAMs under the constraints of pre-bond and post-bond test sequences and distance between the BISR circuit and served RAMs. Simulation results show that in comparison with a dedicated BISR scheme (i.e., each RAM has a self-contained BISR circuit), 35% area reduction can be achieved by the shared BISR scheme planned by the proposed allocation technique under lmm distance constraint, and 500mW and 600mW pre-bond and post-bond test power constraints, respectively.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125272070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548929
Chen-Wei Lin, M. Chao, Chih-Chieh Hsu
When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.
{"title":"Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs","authors":"Chen-Wei Lin, M. Chao, Chih-Chieh Hsu","doi":"10.1109/VTS.2013.6548929","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548929","url":null,"abstract":"When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128060655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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