Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548893
Gurgen Harutunyan, S. Shoukourian, V. Vardanian, Y. Zorian
This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation.
{"title":"An effective solution for building memory BIST infrastructure based on fault periodicity","authors":"Gurgen Harutunyan, S. Shoukourian, V. Vardanian, Y. Zorian","doi":"10.1109/VTS.2013.6548893","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548893","url":null,"abstract":"This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134269712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548923
Christopher Bell, Matthew Lewandowski, S. Katkoori
A hardware Trojan is a modification to a hardware design which inserts undesired or malicious functionality. They pose a substantial security risk, and as such, rapid, reliable detection of these Trojans has become a critical necessity. In this paper, we propose a method for detecting compromised designs quickly and effectively. The method involves a multi-parameter analysis of the design and statistical analysis to determine which designs have been compromised. We also briefly discuss a supplemental method of confirming our results using a targeted method of FPGA design analysis. This method was proposed for consideration in the Cyber Security Awareness Week (CSAW) 2012 Embedded Systems Challenge (ESC) hosted by the Polytechnic Institute of New York University. This served to independently verify our results. The method was awarded first place in the competition.
{"title":"A multi-parameter functional side-channel analysis method for hardware trust verification","authors":"Christopher Bell, Matthew Lewandowski, S. Katkoori","doi":"10.1109/VTS.2013.6548923","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548923","url":null,"abstract":"A hardware Trojan is a modification to a hardware design which inserts undesired or malicious functionality. They pose a substantial security risk, and as such, rapid, reliable detection of these Trojans has become a critical necessity. In this paper, we propose a method for detecting compromised designs quickly and effectively. The method involves a multi-parameter analysis of the design and statistical analysis to determine which designs have been compromised. We also briefly discuss a supplemental method of confirming our results using a targeted method of FPGA design analysis. This method was proposed for consideration in the Cyber Security Awareness Week (CSAW) 2012 Embedded Systems Challenge (ESC) hosted by the Polytechnic Institute of New York University. This served to independently verify our results. The method was awarded first place in the competition.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115716033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548891
B. Kaminska, B. Courtois, S. Hassoun
Consider a re-spin of an existing complex SoC, with a partial schematic and an incomplete specification, with limited abilities to test and observe I/O behavior. Additionally, the underlying technology used is only partially understood. Can disciplined engineering approaches yield the re-spin? What are fundamental challenges? How will automation tools enable such designs? This talk will showcase how analysis and synthesis concepts can be applied in the context of biological discovery and design. Various optimization and analysis techniques can be applied to maximize the production of ethanol within an E. Coli cell without kill it. Pathway synthesis techniques can help uncover the fate of environmental chemicals within the human gut, which is colonized by ∼1014 bacteria belonging to ∼1000 species. No biology pre-requisites are needed to attend this talk.
{"title":"New topic session 2B: Why (Re-)Designing Biology is ∗Slightly∗ more challenging than designing electronics","authors":"B. Kaminska, B. Courtois, S. Hassoun","doi":"10.1109/VTS.2013.6548891","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548891","url":null,"abstract":"Consider a re-spin of an existing complex SoC, with a partial schematic and an incomplete specification, with limited abilities to test and observe I/O behavior. Additionally, the underlying technology used is only partially understood. Can disciplined engineering approaches yield the re-spin? What are fundamental challenges? How will automation tools enable such designs? This talk will showcase how analysis and synthesis concepts can be applied in the context of biological discovery and design. Various optimization and analysis techniques can be applied to maximize the production of ethanol within an E. Coli cell without kill it. Pathway synthesis techniques can help uncover the fate of environmental chemicals within the human gut, which is colonized by ∼1014 bacteria belonging to ∼1000 species. No biology pre-requisites are needed to attend this talk.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116278533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548889
L. Abdallah, H. Stratigopoulos, S. Mir, J. Altet
We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.
{"title":"Defect-oriented non-intrusive RF test using on-chip temperature sensors","authors":"L. Abdallah, H. Stratigopoulos, S. Mir, J. Altet","doi":"10.1109/VTS.2013.6548889","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548889","url":null,"abstract":"We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122469204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548910
Aitzan Sari, M. Psarakis, D. Gizopoulos
SRAM-based FPGAs provide an attractive solution for building high-performance embedded computing systems. Fault tolerant mechanisms are usually implemented in FPGA-based critical systems to improve their vulnerability to transient faults. Most fault tolerant approaches proposed so far in the literature for FPGA systems utilize checkpointing and scrubbing techniques for the fault recovery and repair operations, respectively, and rely on redundancy-based fault detection solutions. In this paper, we study the feasibility of building a low-cost fault-tolerant approach for FPGA-based realtime systems that combines checkpointing and scrubbing, the latter for both fault detection and repair. We calculate the checkpoint frequencies that guarantee the execution of the tasks within their deadlines in the presence of transient faults, taking into consideration the scrubbing time of the FPGA processor. Furthermore, we propose a selective scrubbing approach to reduce the scrubbing time and make feasible the fault tolerant execution of tasks with tight deadlines. We demonstrate the proposed approach in a Leon-3-based SoC in a Virtex-5 FPGA.
{"title":"Combining checkpointing and scrubbing in FPGA-based real-time systems","authors":"Aitzan Sari, M. Psarakis, D. Gizopoulos","doi":"10.1109/VTS.2013.6548910","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548910","url":null,"abstract":"SRAM-based FPGAs provide an attractive solution for building high-performance embedded computing systems. Fault tolerant mechanisms are usually implemented in FPGA-based critical systems to improve their vulnerability to transient faults. Most fault tolerant approaches proposed so far in the literature for FPGA systems utilize checkpointing and scrubbing techniques for the fault recovery and repair operations, respectively, and rely on redundancy-based fault detection solutions. In this paper, we study the feasibility of building a low-cost fault-tolerant approach for FPGA-based realtime systems that combines checkpointing and scrubbing, the latter for both fault detection and repair. We calculate the checkpoint frequencies that guarantee the execution of the tasks within their deadlines in the presence of transient faults, taking into consideration the scrubbing time of the FPGA processor. Furthermore, we propose a selective scrubbing approach to reduce the scrubbing time and make feasible the fault tolerant execution of tasks with tight deadlines. We demonstrate the proposed approach in a Leon-3-based SoC in a Virtex-5 FPGA.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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