Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548931
B. Seshadri, B. Cory, S. Mitra
At the 32/28nm node and below, parametric and process marginality contribute increasing yield loss. Additionally, this yield loss is often asserted spatially. A further complication is that the interaction of design rules is increasing node over node, requiring ever more characterization and modeling. Thus, a significant increase in the quantity and quality of electrical characterization — including full wafer coverage — is necessary to rapidly diagnose, eliminate, and monitor these yield loss mechanisms. However, present test time budgets must be maintained. Our presentation focuses on methods to meet these requirements.
{"title":"Innovative practices session 9C: Yield improvement: Challenges and directions","authors":"B. Seshadri, B. Cory, S. Mitra","doi":"10.1109/VTS.2013.6548931","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548931","url":null,"abstract":"At the 32/28nm node and below, parametric and process marginality contribute increasing yield loss. Additionally, this yield loss is often asserted spatially. A further complication is that the interaction of design rules is increasing node over node, requiring ever more characterization and modeling. Thus, a significant increase in the quantity and quality of electrical characterization — including full wafer coverage — is necessary to rapidly diagnose, eliminate, and monitor these yield loss mechanisms. However, present test time budgets must be maintained. Our presentation focuses on methods to meet these requirements.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548941
Mukesh Agrawal, K. Chakrabarty
Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic solution, which is compared to an exact approach for a small test case and to a random-selection baseline method for large test cases.
{"title":"Test-cost optimization and test-flow selection for 3D-stacked ICs","authors":"Mukesh Agrawal, K. Chakrabarty","doi":"10.1109/VTS.2013.6548941","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548941","url":null,"abstract":"Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic solution, which is compared to an exact approach for a small test case and to a random-selection baseline method for large test cases.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117280831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548935
S. Kiamehr, Mojtaba Ebrahimi, F. Firouzi, M. Tahoori
With continuous downscaling of VLSI technologies, logic cells are becoming more susceptible to radiation-induced soft error. To accurately model this at chip-level, the impact of electrical masking should be accurately considered. Moreover, increasing complexity of VLSI chips at nanoscale results in voltage fluctuation across the chip which impacts the electrical masking. In this paper, we present a chip-level electrical masking analysis which accurately considers the impact of voltage fluctuation across the chip. Our analysis shows that neglecting voltage fluctuation in electrical masking can lead up to 152% inaccuracy in the overall soft error rate. We also present a technique based on backward pulse propagation to reduce the runtime of this analysis.
{"title":"Chip-level modeling and analysis of electrical masking of soft errors","authors":"S. Kiamehr, Mojtaba Ebrahimi, F. Firouzi, M. Tahoori","doi":"10.1109/VTS.2013.6548935","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548935","url":null,"abstract":"With continuous downscaling of VLSI technologies, logic cells are becoming more susceptible to radiation-induced soft error. To accurately model this at chip-level, the impact of electrical masking should be accurately considered. Moreover, increasing complexity of VLSI chips at nanoscale results in voltage fluctuation across the chip which impacts the electrical masking. In this paper, we present a chip-level electrical masking analysis which accurately considers the impact of voltage fluctuation across the chip. Our analysis shows that neglecting voltage fluctuation in electrical masking can lead up to 152% inaccuracy in the overall soft error rate. We also present a technique based on backward pulse propagation to reduce the runtime of this analysis.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129967697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548939
Brandon Noia, K. Chakrabarty
Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3D ICs. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for known-good-die (KGD) test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond TSV and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to through-silicon-via (TSV) paths by design-for-test (DfT) insertion. The proposed method is evaluated through simulations using a logic-on-logic 3D benchmark. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming.
{"title":"Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs","authors":"Brandon Noia, K. Chakrabarty","doi":"10.1109/VTS.2013.6548939","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548939","url":null,"abstract":"Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3D ICs. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for known-good-die (KGD) test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond TSV and pre-bond scan test can be performed. The drawback of die wrappers is that two clocked stages are added to each path that crosses a die boundary. In this paper, a bypass mode is added to GSFs to avoid the extra clock stages and retiming is used to recover the additional delay added to through-silicon-via (TSV) paths by design-for-test (DfT) insertion. The proposed method is evaluated through simulations using a logic-on-logic 3D benchmark. Results show that in most cases, retiming at both the die-level and stack-level is sufficient for recovering the delay added by wrapper boundary cells. Stuck-at ATPG is performed to demonstrate that wrapper insertion and retiming have little impact on pattern count. The area overhead due to wrapper insertion is shown to increase as a circuit is partitioned across an increasing number of stack layers, but the area overhead can be reduced using retiming.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548919
Chen-Yong Cher, Y. Makris, C. Thibeault, A. Drake
Critical Path Monitors (CPM) are a way of modeling the frequency response of a microprocessor to voltage, environment, workload, and other operating point changes. When coupled with a frequency controller, the CPM gives the microprocessor the ability to adjust its frequency to match the current operating environment. This allows for more efficient designs since voltage and frequency margins required to compensate for voltage droops, di/dt events, temperature changes, and other noise events are no longer needed. Calibration is key to functional Critical Path Monitors. Calibration compensates for process variation and pulls the CPM in-line with the hardware it is controlling. In this talk the CPM, frequency control loop, and calibration methodology of the Power7+ microprocessor is described. The CPM models frequency response well enough, after calibration, to allow for a 22% margin reduction. Our measurements demonstrate the value of the CPM for modeling frequency response that can be applied to DVFS microprocessors with the potential to reduce development and test times and to make systems more resilient.
{"title":"Innovative practices session 7C: Self-calibration & trimming","authors":"Chen-Yong Cher, Y. Makris, C. Thibeault, A. Drake","doi":"10.1109/VTS.2013.6548919","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548919","url":null,"abstract":"Critical Path Monitors (CPM) are a way of modeling the frequency response of a microprocessor to voltage, environment, workload, and other operating point changes. When coupled with a frequency controller, the CPM gives the microprocessor the ability to adjust its frequency to match the current operating environment. This allows for more efficient designs since voltage and frequency margins required to compensate for voltage droops, di/dt events, temperature changes, and other noise events are no longer needed. Calibration is key to functional Critical Path Monitors. Calibration compensates for process variation and pulls the CPM in-line with the hardware it is controlling. In this talk the CPM, frequency control loop, and calibration methodology of the Power7+ microprocessor is described. The CPM models frequency response well enough, after calibration, to allow for a 22% margin reduction. Our measurements demonstrate the value of the CPM for modeling frequency response that can be applied to DVFS microprocessors with the potential to reduce development and test times and to make systems more resilient.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548880
Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, M. Chang, M. Chao
This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-VDD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.
{"title":"Testing retention flip-flops in power-gated designs","authors":"Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, M. Chang, M. Chao","doi":"10.1109/VTS.2013.6548880","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548880","url":null,"abstract":"This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-VDD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"16 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131686980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548892
Charutosh Dixit, R. Tekumalla, S. Chakravarty, M. d'Abreu, Z. Bao, C. Riccobene
Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that we face.
{"title":"Innovative practices session 2C: Memory test","authors":"Charutosh Dixit, R. Tekumalla, S. Chakravarty, M. d'Abreu, Z. Bao, C. Riccobene","doi":"10.1109/VTS.2013.6548892","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548892","url":null,"abstract":"Use of Nand Flash memory in storage devices is increasing at an exponential rate. As the technology feature size shrink, the reliability and endurance for the Nand device reduces. Currently Nand devices can have more than 258Gb cells. Testing such devices is not a trivial proposition. In this presentation we will discuss the failure modes for Nand flash, the test methods used and the challenges that we face.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115074923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548937
Yuntan Fang, Huawei Li, Xiaowei Li
As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams.
{"title":"RSAK: Random stream attack for phase change memory in video applications","authors":"Yuntan Fang, Huawei Li, Xiaowei Li","doi":"10.1109/VTS.2013.6548937","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548937","url":null,"abstract":"As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116230413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548895
Chen-Wei Lin, Chin-Yuan Huang, M. Chao
Due to the demand of lower power, a lot of research effort has been devoted into developing new SRAM cell designs that can operate with low supply voltage. The new SRAM cell designs have their own cell structures and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM. Accordingly, specialized test methods are usually required for the uncovered faults of traditional tests. In this paper, we focus on testing open defects in a new low-VMIN data-aware dynamic-supply 8T SRAM design. The new SRAM utilizes a data-aware dynamic-supply circuitry cooperating with two write-word-lines to assist the write and an independent read path to enhance the read-SNM. Based on the specific cell structure, we propose a novel test method for the open defects. The test method creates an in-cell self-attacking environment and can detect all the defects undetected by traditional tests in both the SRAM cell and the data-aware dynamic-supply circuitry. Also, the method requires much less test time when being compared to the traditional floating bit-line attacking method.
{"title":"Testing of a low-VMIN data-aware dynamic-supply 8T SRAM","authors":"Chen-Wei Lin, Chin-Yuan Huang, M. Chao","doi":"10.1109/VTS.2013.6548895","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548895","url":null,"abstract":"Due to the demand of lower power, a lot of research effort has been devoted into developing new SRAM cell designs that can operate with low supply voltage. The new SRAM cell designs have their own cell structures and design techniques, which may result in different faulty behaviors than the conventional 6T SRAM. Accordingly, specialized test methods are usually required for the uncovered faults of traditional tests. In this paper, we focus on testing open defects in a new low-VMIN data-aware dynamic-supply 8T SRAM design. The new SRAM utilizes a data-aware dynamic-supply circuitry cooperating with two write-word-lines to assist the write and an independent read path to enhance the read-SNM. Based on the specific cell structure, we propose a novel test method for the open defects. The test method creates an in-cell self-attacking environment and can detect all the defects undetected by traditional tests in both the SRAM cell and the data-aware dynamic-supply circuitry. Also, the method requires much less test time when being compared to the traditional floating bit-line attacking method.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122813046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548906
Kai Hu, Tsung-Yi Ho, K. Chakrabarty
Recent advances in flow-based microfluidics have led to the emergence of biochemistry-on-a-chip as a new paradigm in clinical diagnostics and biomolecular recognition. However, a potential roadblock in the deployment of microfluidic biochips is the lack of test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. Prior work on fault detection in biochips has been limited to digital (“droplet”) microfluidics and other electrode-based technology platforms. We propose the first approach for automated testing of flow-based microfluidic biochips that are designed using membrane-based valves for flow control. The proposed test technique is based on a behavioral abstraction of physical defects in microchannels and valves. The flow paths and flow control in the microfluidic device are modeled as a logic circuit composed of Boolean gates, which allows us to carry out test generation using standard ATPG tools. The tests derived using the logic circuit model are then mapped to fluidic operations involving pumps and pressure meters in the biochip. Feedback from pressure meters can be compared to expected responses based on the logic circuit model, whereby the types and positions of defects are identified. We show how a fabricated biochip can be tested using the proposed method, and we achieve 100% coverage of faults that model defects in channels and valves.
{"title":"Testing of flow-based microfluidic biochips","authors":"Kai Hu, Tsung-Yi Ho, K. Chakrabarty","doi":"10.1109/VTS.2013.6548906","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548906","url":null,"abstract":"Recent advances in flow-based microfluidics have led to the emergence of biochemistry-on-a-chip as a new paradigm in clinical diagnostics and biomolecular recognition. However, a potential roadblock in the deployment of microfluidic biochips is the lack of test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. Prior work on fault detection in biochips has been limited to digital (“droplet”) microfluidics and other electrode-based technology platforms. We propose the first approach for automated testing of flow-based microfluidic biochips that are designed using membrane-based valves for flow control. The proposed test technique is based on a behavioral abstraction of physical defects in microchannels and valves. The flow paths and flow control in the microfluidic device are modeled as a logic circuit composed of Boolean gates, which allows us to carry out test generation using standard ATPG tools. The tests derived using the logic circuit model are then mapped to fluidic operations involving pumps and pressure meters in the biochip. Feedback from pressure meters can be compared to expected responses based on the logic circuit model, whereby the types and positions of defects are identified. We show how a fabricated biochip can be tested using the proposed method, and we achieve 100% coverage of faults that model defects in channels and valves.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130262467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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