Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548930
E. Larsson
As semiconductor technologies enables highly advanced an complex integrated circuits (ICs), there is an increasing need to have more embedded design-for-test (DfT) instruments for test, debug, diagnosis, configuration, monitoring, etc. As these instruments are to be used not only at chip-level but also at board-level and system-level, a key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers low-cost, non-intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. We will discuss the need of embedded instrumentation, the shortcomings of IEEE 1149.1, the features and challenges of IEEE P1687, as well as cases studies on the usage of IEEE P1687.
{"title":"Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies","authors":"E. Larsson","doi":"10.1109/VTS.2013.6548930","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548930","url":null,"abstract":"As semiconductor technologies enables highly advanced an complex integrated circuits (ICs), there is an increasing need to have more embedded design-for-test (DfT) instruments for test, debug, diagnosis, configuration, monitoring, etc. As these instruments are to be used not only at chip-level but also at board-level and system-level, a key challenge is how to access these instruments from chip terminals in a low-cost, non-intrusive, standardized, flexible and scalable manner. The well-adopted IEEE 1149.1 (Joint Test Action Group (JTAG)) standard offers low-cost, non-intrusive and standardized access but lacks flexibility and scalability, which is addressed by the on-going IEEE P1687 (Internal JTAG (IJTAG)) standardization initiative. We will discuss the need of embedded instrumentation, the shortcomings of IEEE 1149.1, the features and challenges of IEEE P1687, as well as cases studies on the usage of IEEE P1687.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129399008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548933
K. Jenkins, P. Restle, P. Wang, David Hogenmiller, D. Boerstler, T. Bucelot
An on-chip circuit to measure full analog waveforms of internal signals is described. It can measure signals up to a repetition rate of at least 7 GHz, a bandwidth of at least 12 GHz, with accuracy required to detect subtle differences in signals, and it can measure overshoot above the rail voltage. It has been demonstrated on an experimental clock grid with optional resonant operation.
{"title":"On-chip circuit for measuring multi-GHz clock signal waveforms","authors":"K. Jenkins, P. Restle, P. Wang, David Hogenmiller, D. Boerstler, T. Bucelot","doi":"10.1109/VTS.2013.6548933","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548933","url":null,"abstract":"An on-chip circuit to measure full analog waveforms of internal signals is described. It can measure signals up to a repetition rate of at least 7 GHz, a bandwidth of at least 12 GHz, with accuracy required to detect subtle differences in signals, and it can measure overshoot above the rail voltage. It has been demonstrated on an experimental clock grid with optional resonant operation.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548894
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine
Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.
{"title":"A built-in scheme for testing and repairing voltage regulators of low-power srams","authors":"L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/VTS.2013.6548894","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548894","url":null,"abstract":"Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124087891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548943
Chen-Yong Cher, Mohan J. Kumar
Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.
{"title":"Innovative practices session 11C: Resilience","authors":"Chen-Yong Cher, Mohan J. Kumar","doi":"10.1109/VTS.2013.6548943","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548943","url":null,"abstract":"Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548906
Kai Hu, Tsung-Yi Ho, K. Chakrabarty
Recent advances in flow-based microfluidics have led to the emergence of biochemistry-on-a-chip as a new paradigm in clinical diagnostics and biomolecular recognition. However, a potential roadblock in the deployment of microfluidic biochips is the lack of test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. Prior work on fault detection in biochips has been limited to digital (“droplet”) microfluidics and other electrode-based technology platforms. We propose the first approach for automated testing of flow-based microfluidic biochips that are designed using membrane-based valves for flow control. The proposed test technique is based on a behavioral abstraction of physical defects in microchannels and valves. The flow paths and flow control in the microfluidic device are modeled as a logic circuit composed of Boolean gates, which allows us to carry out test generation using standard ATPG tools. The tests derived using the logic circuit model are then mapped to fluidic operations involving pumps and pressure meters in the biochip. Feedback from pressure meters can be compared to expected responses based on the logic circuit model, whereby the types and positions of defects are identified. We show how a fabricated biochip can be tested using the proposed method, and we achieve 100% coverage of faults that model defects in channels and valves.
{"title":"Testing of flow-based microfluidic biochips","authors":"Kai Hu, Tsung-Yi Ho, K. Chakrabarty","doi":"10.1109/VTS.2013.6548906","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548906","url":null,"abstract":"Recent advances in flow-based microfluidics have led to the emergence of biochemistry-on-a-chip as a new paradigm in clinical diagnostics and biomolecular recognition. However, a potential roadblock in the deployment of microfluidic biochips is the lack of test techniques to screen defective devices before they are used for biochemical analysis. Defective chips lead to repetition of experiments, which is undesirable due to high reagent cost and limited availability of samples. Prior work on fault detection in biochips has been limited to digital (“droplet”) microfluidics and other electrode-based technology platforms. We propose the first approach for automated testing of flow-based microfluidic biochips that are designed using membrane-based valves for flow control. The proposed test technique is based on a behavioral abstraction of physical defects in microchannels and valves. The flow paths and flow control in the microfluidic device are modeled as a logic circuit composed of Boolean gates, which allows us to carry out test generation using standard ATPG tools. The tests derived using the logic circuit model are then mapped to fluidic operations involving pumps and pressure meters in the biochip. Feedback from pressure meters can be compared to expected responses based on the logic circuit model, whereby the types and positions of defects are identified. We show how a fabricated biochip can be tested using the proposed method, and we achieve 100% coverage of faults that model defects in channels and valves.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130262467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.
{"title":"A hybrid ECC and redundancy technique for reducing refresh power of DRAMs","authors":"Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, D. Kwai, Yung-Fa Chou, Cheng-Wen Wu","doi":"10.1109/VTS.2013.6548927","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548927","url":null,"abstract":"Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40~70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124214648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548922
Xuehui Zhang, K. Xiao, M. Tehranipoor, Jeyavijayan Rajendran, R. Karri
As part of the Embedded Systems Challenge, we assess the effectiveness of Trojan detection techniques. The red team inserted different types of Trojans - combinational, sequential, reliability degrading, and performance degrading - into selected variants of a target design; the other variants are Trojan-free. The blue team has to correctly classify the Trojan-free and Trojan-infected variants. Seven different teams from six different universities performed the blue team activity using different types of Trojan-detection techniques, namely activation-based detection, and power- and delay-based side-channels.
{"title":"A study on the effectiveness of Trojan detection techniques using a red team blue team approach","authors":"Xuehui Zhang, K. Xiao, M. Tehranipoor, Jeyavijayan Rajendran, R. Karri","doi":"10.1109/VTS.2013.6548922","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548922","url":null,"abstract":"As part of the Embedded Systems Challenge, we assess the effectiveness of Trojan detection techniques. The red team inserted different types of Trojans - combinational, sequential, reliability degrading, and performance degrading - into selected variants of a target design; the other variants are Trojan-free. The blue team has to correctly classify the Trojan-free and Trojan-infected variants. Seven different teams from six different universities performed the blue team activity using different types of Trojan-detection techniques, namely activation-based detection, and power- and delay-based side-channels.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129196549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548903
S. K. Rao, R. Robucci, C. Patel
Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay caused by variations in power-supply voltage. This increase in delay can cause significant overkill during transition and delay testing. It is critical to account for this increase in delay during the ATPG process. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. To overcome this issue, our technique uses simulations of individual extracted paths and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for the C6288 ISCAS'85 benchmark circuit are presented. Our technique can also be applied to sequential circuits and simulation results demonstrating this are also presented.
{"title":"Scalable dynamic technique for accurately predicting power-supply noise and path delay","authors":"S. K. Rao, R. Robucci, C. Patel","doi":"10.1109/VTS.2013.6548903","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548903","url":null,"abstract":"Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay caused by variations in power-supply voltage. This increase in delay can cause significant overkill during transition and delay testing. It is critical to account for this increase in delay during the ATPG process. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. To overcome this issue, our technique uses simulations of individual extracted paths and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for the C6288 ISCAS'85 benchmark circuit are presented. Our technique can also be applied to sequential circuits and simulation results demonstrating this are also presented.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129225925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548926
Raymond Paseman, A. Orailoglu
Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection mechanisms. Numerous techniques exist, a subset of which we applied to 6 sets of combinational circuits and 2 sets of sequential circuits in order to effectively determine the presence of a hardware trojan. Utilizing only a single type of functional test and a single type of side-channel test, we were able to make determinations about all 6 sets of combinational circuits and 1 of the 2 sets of sequential circuits.
{"title":"Towards a cost-effective hardware trojan detection methodology","authors":"Raymond Paseman, A. Orailoglu","doi":"10.1109/VTS.2013.6548926","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548926","url":null,"abstract":"Due to the increasing globalization of integrated circuit fabrication, hardware security has emerged as a major issue, necessitating hardware trojan detection mechanisms. Numerous techniques exist, a subset of which we applied to 6 sets of combinational circuits and 2 sets of sequential circuits in order to effectively determine the presence of a hardware trojan. Utilizing only a single type of functional test and a single type of side-channel test, we were able to make determinations about all 6 sets of combinational circuits and 1 of the 2 sets of sequential circuits.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-29DOI: 10.1109/VTS.2013.6548924
D. Hély, Julien Martin, Gerson Dario Piraquive Triana, S. Mounier, Elie Riviere, Thibault Sahuc, Jeremy Savonet, Laura Soundararadjou
In this work, we present and comment several experiments in Hardware Trojan detection based on both testing techniques and side channel analysis. This work has been developed by two teams of Grenoble INP students (Julien Martin, Gerson Dario Piraquive Triana, Simon Piroux Mounier, Elie Rivière, Thibault Sahuc, Jérémy Savonet and Laura Soundararadjou) during the secure IC design labs of the Grenoble INP Esisar and was then presented for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2012 organized by Polytechnic Institute of New York University.
{"title":"Experiences in side channel and testing based Hardware Trojan detection","authors":"D. Hély, Julien Martin, Gerson Dario Piraquive Triana, S. Mounier, Elie Riviere, Thibault Sahuc, Jeremy Savonet, Laura Soundararadjou","doi":"10.1109/VTS.2013.6548924","DOIUrl":"https://doi.org/10.1109/VTS.2013.6548924","url":null,"abstract":"In this work, we present and comment several experiments in Hardware Trojan detection based on both testing techniques and side channel analysis. This work has been developed by two teams of Grenoble INP students (Julien Martin, Gerson Dario Piraquive Triana, Simon Piroux Mounier, Elie Rivière, Thibault Sahuc, Jérémy Savonet and Laura Soundararadjou) during the secure IC design labs of the Grenoble INP Esisar and was then presented for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2012 organized by Polytechnic Institute of New York University.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"20 23-24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116555275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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