Pub Date : 2019-07-15DOI: 10.1109/MECO.2019.8760065
Nan-Sheng Huang, Jan-Matthias Braun, J. C. Larsen, P. Manoonpong
Reservoir computing (RC) features with the rich computational dynamics is a kind of powerful machine learning paradigm that is well suited for non-linear time-series prediction and classification problems. However, this impressive performance comes with a cost of complex arithmetic operations and high memory usage that make it significantly challenging to deploy on embedded systems. Solutions based on CPU and/or GPU-based designs, provides flexibility but suffers from a lack of efficiency in terms of power, performance, and area (PPA). Although hardware-accelerated solutions can improve efficiency, it takes longer design cycles and is time-consuming. Furthermore, it may happen that design spec requires run change due to the fact that the network is retrained with the new data set to improve the performance. It leads to extra effort in the redesign of the hardware-accelerated solution. This preliminary work presents the design and implementation of a hardware generator for RC-ESNs (echo state networks) to tackle the problem. The proposed methodology is demonstrated by various offline-trained network parameters and topologies. Compared to existing solutions, the proposed framework provides scalability with the support of DSE in agile hardware design.
{"title":"A scalable Echo State Networks hardware generator for embedded systems using high-level synthesis","authors":"Nan-Sheng Huang, Jan-Matthias Braun, J. C. Larsen, P. Manoonpong","doi":"10.1109/MECO.2019.8760065","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760065","url":null,"abstract":"Reservoir computing (RC) features with the rich computational dynamics is a kind of powerful machine learning paradigm that is well suited for non-linear time-series prediction and classification problems. However, this impressive performance comes with a cost of complex arithmetic operations and high memory usage that make it significantly challenging to deploy on embedded systems. Solutions based on CPU and/or GPU-based designs, provides flexibility but suffers from a lack of efficiency in terms of power, performance, and area (PPA). Although hardware-accelerated solutions can improve efficiency, it takes longer design cycles and is time-consuming. Furthermore, it may happen that design spec requires run change due to the fact that the network is retrained with the new data set to improve the performance. It leads to extra effort in the redesign of the hardware-accelerated solution. This preliminary work presents the design and implementation of a hardware generator for RC-ESNs (echo state networks) to tackle the problem. The proposed methodology is demonstrated by various offline-trained network parameters and topologies. Compared to existing solutions, the proposed framework provides scalability with the support of DSE in agile hardware design.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123214714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-15DOI: 10.1109/MECO.2019.8760146
Han Cui, N. Dahnoun
This paper investigates the potential of task-based parallelisation for application loops in the presence of cross-iteration dependencies. A novel task-based parallelisation scheme is implemented as an LLVM compiler pass that could automatically parallelise loops without programmer intervention. The parallelisation scheme is shown to be able to achieve significant performance improvements on computationally expensive applications with up to 61x speedup on 64 threads, and is capable of dealing with imbalanced workloads and arbitrary dependency patterns.
{"title":"Exploiting Task-based Parallelism in Application Loops","authors":"Han Cui, N. Dahnoun","doi":"10.1109/MECO.2019.8760146","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760146","url":null,"abstract":"This paper investigates the potential of task-based parallelisation for application loops in the presence of cross-iteration dependencies. A novel task-based parallelisation scheme is implemented as an LLVM compiler pass that could automatically parallelise loops without programmer intervention. The parallelisation scheme is shown to be able to achieve significant performance improvements on computationally expensive applications with up to 61x speedup on 64 threads, and is capable of dealing with imbalanced workloads and arbitrary dependency patterns.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124804955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-15DOI: 10.1109/MECO.2019.8760152
Han Cui, S. Tancock, N. Dahnoun
In engineering education, most emphasis on teaching is centred around Content Knowledge and less on technology and pedagogy. In this paper, we present an e-learning system that enables students to provide real-time feedback during lectures and helps lecturers improve/adjust their teaching by knowing more about the students' needs. We also discuss the relevance of our system in pedagogy. Finally, a complete system prototype contributing to technology, pedagogy, and content knowledge will be demonstrated.
{"title":"E-Learning Tool to Enhance Technological Pedagogical Content Knowledge","authors":"Han Cui, S. Tancock, N. Dahnoun","doi":"10.1109/MECO.2019.8760152","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760152","url":null,"abstract":"In engineering education, most emphasis on teaching is centred around Content Knowledge and less on technology and pedagogy. In this paper, we present an e-learning system that enables students to provide real-time feedback during lectures and helps lecturers improve/adjust their teaching by knowing more about the students' needs. We also discuss the relevance of our system in pedagogy. Finally, a complete system prototype contributing to technology, pedagogy, and content knowledge will be demonstrated.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115482656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760044
L. Verdoscia, Amin Sahebi, R. Giorgi
The native implementation of the N-point digital Fourier Transform involves calculating the scalar product of the sample buffer (treated as an N-dimensional vector) with N separate basis vectors. Since each scalar product involves N multiplications and N additions, the total time is proportional to $N^{2}$, in other words, its an $O(N^{2})$ algorithm. However, it turns out that by cleverly re-arranging these operations, one can optimize the algorithm down to $O(Nlog_{2}(N))$, which for large N makes a huge difference. The optimized version of the algorithm is called the Fast Fourier Transform, or the FFT. In this paper, we discuss about an efficient way to obtain Fast Fourier Transform algorithm (FFT). According to our study, we can eliminate some operations in calculating the FFT algorithm thanks to property of complex numbers and we can achieve the FFT in a better execution time due to a significant reduction of $N/8$ of the needed twiddle factors and to additional factorizations.
{"title":"A Data-Flow Methodology for Accelerating FFT","authors":"L. Verdoscia, Amin Sahebi, R. Giorgi","doi":"10.1109/MECO.2019.8760044","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760044","url":null,"abstract":"The native implementation of the N-point digital Fourier Transform involves calculating the scalar product of the sample buffer (treated as an N-dimensional vector) with N separate basis vectors. Since each scalar product involves N multiplications and N additions, the total time is proportional to $N^{2}$, in other words, its an $O(N^{2})$ algorithm. However, it turns out that by cleverly re-arranging these operations, one can optimize the algorithm down to $O(Nlog_{2}(N))$, which for large N makes a huge difference. The optimized version of the algorithm is called the Fast Fourier Transform, or the FFT. In this paper, we discuss about an efficient way to obtain Fast Fourier Transform algorithm (FFT). According to our study, we can eliminate some operations in calculating the FFT algorithm thanks to property of complex numbers and we can achieve the FFT in a better execution time due to a significant reduction of $N/8$ of the needed twiddle factors and to additional factorizations.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124689046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760150
A. Škraba, Andrej Kolozvari, D. Kofjac, R. Stojanovic, E. Semenkin, V. Stanovov
The paper describes the development of group heart rate monitoring system based on ESP32 module. The system architecture is described considering Wi-Fi, Blue Tooth and Blue Tooth Low Energy connection. The development of full stack prototype monitoring application is described. Power consumption measurements were performed. Short comparison between ESP8266 and ESP32 modules is provided.
{"title":"Prototype of Group Heart Rate Monitoring with ESP32","authors":"A. Škraba, Andrej Kolozvari, D. Kofjac, R. Stojanovic, E. Semenkin, V. Stanovov","doi":"10.1109/MECO.2019.8760150","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760150","url":null,"abstract":"The paper describes the development of group heart rate monitoring system based on ESP32 module. The system architecture is described considering Wi-Fi, Blue Tooth and Blue Tooth Low Energy connection. The development of full stack prototype monitoring application is described. Power consumption measurements were performed. Short comparison between ESP8266 and ESP32 modules is provided.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760043
R. Fujdiak, Petr Blazek, L. Apvrille, Zdenek Martinasek, P. Mlynek, R. Pacalet, D. Smekal, Pavel Mrnustik, M. Barabas, Maysam Zoor
Nowadays, the development of products for modern cyber-physical systems consists of many stages defined by the product life cycle (PLC). However, many manufacturers are not paying full attention - if any at all - to each PLC stage. This, among others, is causing growth of development costs. Therefore, the first stage of PLC becomes crucial. Moreover, a significant part of the development costs might be saved via testing the required parameters in this early stage, e.g., via modeling tools, simulation tools or emulators. Considering among others the current cyber-warfare and everyday growing number of threats, security is becoming one of the most critical topics in PLC. However, the security aspects come with significant trade-offs with performance. This paper focuses on methodology for dealing with these trade-offs via simulation in the early stage of PLC, where basic requirements are settled. To establish security requirements, an extensive Secure Software Development Life Cycle catalog is used together with an advanced modeling framework TTool based on UML/SysML-Sec for performance trade-off analysis. This combination creates a powerful approach for establishing the balance between security and performance requirements. As an example, a particular security requirement is selected. Namely, confidentiality, fulfilled by the encryption algorithm AES. This introduces the methodology and approach to the co-engineering issue in the PLC stages, where two different development teams with also different goals (security, performance) are dealing together with the single combined issue. Our results should help to understand the importance of the early PLC stage and show one possible approach on how to deal with these issues.
{"title":"Modeling the Trade-off Between Security and Performance to Support the Product Life Cycle","authors":"R. Fujdiak, Petr Blazek, L. Apvrille, Zdenek Martinasek, P. Mlynek, R. Pacalet, D. Smekal, Pavel Mrnustik, M. Barabas, Maysam Zoor","doi":"10.1109/MECO.2019.8760043","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760043","url":null,"abstract":"Nowadays, the development of products for modern cyber-physical systems consists of many stages defined by the product life cycle (PLC). However, many manufacturers are not paying full attention - if any at all - to each PLC stage. This, among others, is causing growth of development costs. Therefore, the first stage of PLC becomes crucial. Moreover, a significant part of the development costs might be saved via testing the required parameters in this early stage, e.g., via modeling tools, simulation tools or emulators. Considering among others the current cyber-warfare and everyday growing number of threats, security is becoming one of the most critical topics in PLC. However, the security aspects come with significant trade-offs with performance. This paper focuses on methodology for dealing with these trade-offs via simulation in the early stage of PLC, where basic requirements are settled. To establish security requirements, an extensive Secure Software Development Life Cycle catalog is used together with an advanced modeling framework TTool based on UML/SysML-Sec for performance trade-off analysis. This combination creates a powerful approach for establishing the balance between security and performance requirements. As an example, a particular security requirement is selected. Namely, confidentiality, fulfilled by the encryption algorithm AES. This introduces the methodology and approach to the co-engineering issue in the PLC stages, where two different development teams with also different goals (security, performance) are dealing together with the single combined issue. Our results should help to understand the importance of the early PLC stage and show one possible approach on how to deal with these issues.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132891786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8759997
V. Zolotarev, N. N. Grinchenko, G. Ovechkin, P. Ovechkin
Multithreshold decoders (MTD) of self-orthogonal codes (SOC) for erasure channels implementing error correction methods based on searching global extremum of functions in discrete spaces are considered. To increase the efficiency of erasure recoveries the concatenated codes comprising inner SOC and outer codes being simple for decoding such as parity-check codes, Hamming codes or BCH codes are offered. The usage of the codes offered provides efficient erasure recovery when operating near channel capacity with linear decoder complexity. The questions of high-throughput software MTD implementation recovering erasures using GPU are considered. The MTD versions developed are shown to be able to perform data flow decoding with the rate of several hundred MB/s using GPU.
{"title":"The Performance of Multithreshold Decoders in Concatenated Schemes Over Erasure Channels","authors":"V. Zolotarev, N. N. Grinchenko, G. Ovechkin, P. Ovechkin","doi":"10.1109/MECO.2019.8759997","DOIUrl":"https://doi.org/10.1109/MECO.2019.8759997","url":null,"abstract":"Multithreshold decoders (MTD) of self-orthogonal codes (SOC) for erasure channels implementing error correction methods based on searching global extremum of functions in discrete spaces are considered. To increase the efficiency of erasure recoveries the concatenated codes comprising inner SOC and outer codes being simple for decoding such as parity-check codes, Hamming codes or BCH codes are offered. The usage of the codes offered provides efficient erasure recovery when operating near channel capacity with linear decoder complexity. The questions of high-throughput software MTD implementation recovering erasures using GPU are considered. The MTD versions developed are shown to be able to perform data flow decoding with the rate of several hundred MB/s using GPU.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760284
A. Ivanović, P. Rakovic
In this paper the authors will present improvement of Health insurance system in Montenegro. Information system as a vital part of any business oriented company, hence the same paradigm can be applied in health insurance fund. Main focus of this IS its user focused component in order to introduce SMART cards, improve and facilitate the process of validation of insurance users and improve the overall security of the system. With this novel approach the authors propose creation of platform that will enable Health Insurance Fund of Montenegro to introduce novel services into health care ecosystem of Montenegro [7], [8].
{"title":"E-health Card Information System: Case Study Health Insurance Fund of Montenegro","authors":"A. Ivanović, P. Rakovic","doi":"10.1109/MECO.2019.8760284","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760284","url":null,"abstract":"In this paper the authors will present improvement of Health insurance system in Montenegro. Information system as a vital part of any business oriented company, hence the same paradigm can be applied in health insurance fund. Main focus of this IS its user focused component in order to introduce SMART cards, improve and facilitate the process of validation of insurance users and improve the overall security of the system. With this novel approach the authors propose creation of platform that will enable Health Insurance Fund of Montenegro to introduce novel services into health care ecosystem of Montenegro [7], [8].","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114335295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760054
I. Stanković, M. Brajović, M. Daković, C. Ioana
The quantization (digitalization) of measurements greatly affects the reconstruction performance, especially in algorithms based on the reconstruction in the measurement domain. However, it provides a significant advantage in the hardware implementation sense. In this paper, we analyze the performance of the gradient-based algorithm in the signal reconstruction based on a reduced set of digital measurements. This algorithm is considered as a powerful tool for the reconstruction of various types of signals. The paper investigates the accuracy of the algorithm using $B$-bit quantized measurements. The reconstruction performance is analyzed through numerical examples.
{"title":"Gradient-Descent Algorithm Performance With Reduced Set of Quantized Measurements","authors":"I. Stanković, M. Brajović, M. Daković, C. Ioana","doi":"10.1109/MECO.2019.8760054","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760054","url":null,"abstract":"The quantization (digitalization) of measurements greatly affects the reconstruction performance, especially in algorithms based on the reconstruction in the measurement domain. However, it provides a significant advantage in the hardware implementation sense. In this paper, we analyze the performance of the gradient-based algorithm in the signal reconstruction based on a reduced set of digital measurements. This algorithm is considered as a powerful tool for the reconstruction of various types of signals. The paper investigates the accuracy of the algorithm using $B$-bit quantized measurements. The reconstruction performance is analyzed through numerical examples.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123143815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-10DOI: 10.1109/MECO.2019.8760288
V. Muttillo
This work presents an early-stage statement-level metric for energy consumption of embedded SW. In particular, based on an existing assembly-level analysis and some profiling activities performed on a given C benchmark, it defines a metric related to the average energy consumption of a generic C statement for a given target processor. Such a metric, evaluated with a one-time effort, can be then used to rapidly estimate the energy consumption of a given C function for all the characterized processors. Two reference embedded processors are then considered in order to show an example of usage of the proposed metric.
{"title":"J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW","authors":"V. Muttillo","doi":"10.1109/MECO.2019.8760288","DOIUrl":"https://doi.org/10.1109/MECO.2019.8760288","url":null,"abstract":"This work presents an early-stage statement-level metric for energy consumption of embedded SW. In particular, based on an existing assembly-level analysis and some profiling activities performed on a given C benchmark, it defines a metric related to the average energy consumption of a generic C statement for a given target processor. Such a metric, evaluated with a one-time effort, can be then used to rapidly estimate the energy consumption of a given C function for all the characterized processors. Two reference embedded processors are then considered in order to show an example of usage of the proposed metric.","PeriodicalId":141324,"journal":{"name":"2019 8th Mediterranean Conference on Embedded Computing (MECO)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125629211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：