Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468133
S. Biswas, N. Mohan, W. Robbins
A systematic method of designing a zero-ripple Ćuk converter for PV/Battery-to-grid applications is presented in this paper. The integrated magnetic core design uses an intuitive flux-reluctance model to arrive at the Area Product for this kind of structure. Unlike the earlier designs for this converter, it provides a completely analytical approach to design this converter for a range of specifications. The target application is grid interface of PV or battery. The validity of the proposed method is confirmed using finite element analyses (both 2-D and 3-D), circuit simulations in pspice as well as preliminary experimental validation.
{"title":"A systematic design method and verification for a zero-ripple interface for PV/Battery-to-grid applications","authors":"S. Biswas, N. Mohan, W. Robbins","doi":"10.1109/APEC.2016.7468133","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468133","url":null,"abstract":"A systematic method of designing a zero-ripple Ćuk converter for PV/Battery-to-grid applications is presented in this paper. The integrated magnetic core design uses an intuitive flux-reluctance model to arrive at the Area Product for this kind of structure. Unlike the earlier designs for this converter, it provides a completely analytical approach to design this converter for a range of specifications. The target application is grid interface of PV or battery. The validity of the proposed method is confirmed using finite element analyses (both 2-D and 3-D), circuit simulations in pspice as well as preliminary experimental validation.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121695534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468303
P. Ning, X. Wen, Yao-hua Li, Xiongxuan Ge
The layout of power modules is one of the key points in power module design. In this paper, along with design examples, an improved automatic layout method for planar power module is presented. Some practical considerations and implementations are introduced in the optimization procedure.
{"title":"An improved automatic layout method for planar power module","authors":"P. Ning, X. Wen, Yao-hua Li, Xiongxuan Ge","doi":"10.1109/APEC.2016.7468303","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468303","url":null,"abstract":"The layout of power modules is one of the key points in power module design. In this paper, along with design examples, an improved automatic layout method for planar power module is presented. Some practical considerations and implementations are introduced in the optimization procedure.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468006
Zhe Zhang, M. Andersen
The dual active bridge (DAB) converter is an isolated bidirectional dc-dc topology which is the most critical part for the power conversion systems such as solid-state transformers (SST). This paper focuses on analysis and design of high frequency ac inductors which are the power interfacing component in DAB converters or DAB's derivative topologies for transferring energy between the primary and secondary sides. The DAB converter's operation principles, and the corresponding voltage and current stresses over its ac inductor are analyzed. Hereby, six diverse winding arrangements are studied in order to find a design having the lowest ac resistance and core loss. Core loss is calculated by both GSE and iGSE methods, and then the results are compared under two operating conditions. Based upon the finite element method (FEM) simulation, winding losses are investigated. Finally, the case in which the core loss and the winding loss are almost equal is selected as the optimal one. The experimental results are presented to verify the validity of the analysis and design.
{"title":"High frequency AC inductor analysis and design for dual active bridge (DAB) converters","authors":"Zhe Zhang, M. Andersen","doi":"10.1109/APEC.2016.7468006","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468006","url":null,"abstract":"The dual active bridge (DAB) converter is an isolated bidirectional dc-dc topology which is the most critical part for the power conversion systems such as solid-state transformers (SST). This paper focuses on analysis and design of high frequency ac inductors which are the power interfacing component in DAB converters or DAB's derivative topologies for transferring energy between the primary and secondary sides. The DAB converter's operation principles, and the corresponding voltage and current stresses over its ac inductor are analyzed. Hereby, six diverse winding arrangements are studied in order to find a design having the lowest ac resistance and core loss. Core loss is calculated by both GSE and iGSE methods, and then the results are compared under two operating conditions. Based upon the finite element method (FEM) simulation, winding losses are investigated. Finally, the case in which the core loss and the winding loss are almost equal is selected as the optimal one. The experimental results are presented to verify the validity of the analysis and design.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125136121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7467946
E. Abramov, A. Cervera, M. Peretz
This paper details efficiency analysis and characteristics of a gyrator resonant switched-capacitor converter (GRSCC) operating as a voltage regulator. Following the efficiency analysis, this paper introduces an optimal size-efficiency design procedure for IC realization of the converter. In area-sensitive applications, the optimization method combined with the converter's benefits present an attractive approach for better power delivery concepts for point-of-load (PoL) applications. Based on the optimization principles detailed in this study, an on-chip bridge GRSCC topology has been implemented in 0.18μm 5V CMOS process. The analysis has been verified by post-layout analysis and measurements of the fabricated IC. Neglecting the package limitations, the prototype operation is demonstrated with 10 MHz switching frequency, up to 3A, 4.5 W with 3V input voltage, and the efficiency is measured to be 87%. The study has been extended to survey on effects of the package on the performance. The experimental measurements of the manufactured IC have been found to be in very good agreement with the theoretical analysis and optimization process, as well as to accurately estimate the package contribution to the system performance. In addition, a fully monolithic control system to regulate the output voltage is described and implemented on-chip by an automated synthesis process and place-and route tools.
{"title":"Optimal design of a voltage regulator based resonant switched-capacitor converter IC","authors":"E. Abramov, A. Cervera, M. Peretz","doi":"10.1109/APEC.2016.7467946","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467946","url":null,"abstract":"This paper details efficiency analysis and characteristics of a gyrator resonant switched-capacitor converter (GRSCC) operating as a voltage regulator. Following the efficiency analysis, this paper introduces an optimal size-efficiency design procedure for IC realization of the converter. In area-sensitive applications, the optimization method combined with the converter's benefits present an attractive approach for better power delivery concepts for point-of-load (PoL) applications. Based on the optimization principles detailed in this study, an on-chip bridge GRSCC topology has been implemented in 0.18μm 5V CMOS process. The analysis has been verified by post-layout analysis and measurements of the fabricated IC. Neglecting the package limitations, the prototype operation is demonstrated with 10 MHz switching frequency, up to 3A, 4.5 W with 3V input voltage, and the efficiency is measured to be 87%. The study has been extended to survey on effects of the package on the performance. The experimental measurements of the manufactured IC have been found to be in very good agreement with the theoretical analysis and optimization process, as well as to accurately estimate the package contribution to the system performance. In addition, a fully monolithic control system to regulate the output voltage is described and implemented on-chip by an automated synthesis process and place-and route tools.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468147
O. Ojo, M. Ramezani
This paper presents a sensor-less method to control triple-star nine-phase Interior Permanent Magnet (IPM) machines based on a decoupled machine model. The decoupled model removes the control complexity of the drive caused by the coupling inductance terms between different sets of three-phase windings of the triple-star machine. The rotor position is estimated using high frequency voltage injections into the stator fifth sequence circuit of the machine which is non torque producing. The control strategy which seeks to minimize stator copper loss (equivalently, the peak phase current) is set forth and tested by simulations using the full order coupled model of the machine. It is further validated with experimental results.
{"title":"Sensorless speed control of symmetrical triple-star nine-phase Interior Permanent Magnet machines","authors":"O. Ojo, M. Ramezani","doi":"10.1109/APEC.2016.7468147","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468147","url":null,"abstract":"This paper presents a sensor-less method to control triple-star nine-phase Interior Permanent Magnet (IPM) machines based on a decoupled machine model. The decoupled model removes the control complexity of the drive caused by the coupling inductance terms between different sets of three-phase windings of the triple-star machine. The rotor position is estimated using high frequency voltage injections into the stator fifth sequence circuit of the machine which is non torque producing. The control strategy which seeks to minimize stator copper loss (equivalently, the peak phase current) is set forth and tested by simulations using the full order coupled model of the machine. It is further validated with experimental results.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"44 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114013136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468081
M. Evzelman, R. Zane
The feasibility of applying burst mode control in regulation of classical switched-capacitor converters is reevaluated. The results show that contrary to switched inductor based converters, this simple and easy to implement control has no efficiency advantage in terms of conduction losses over frequency modulation control when used to regulate classical switched-capacitor based converters. It is expected, however, that the burst mode could be viable for very low power applications in reducing biasing and housekeeping associated losses if reduced during the burst off time.
{"title":"Burst mode control and switched-capacitor converters losses","authors":"M. Evzelman, R. Zane","doi":"10.1109/APEC.2016.7468081","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468081","url":null,"abstract":"The feasibility of applying burst mode control in regulation of classical switched-capacitor converters is reevaluated. The results show that contrary to switched inductor based converters, this simple and easy to implement control has no efficiency advantage in terms of conduction losses over frequency modulation control when used to regulate classical switched-capacitor based converters. It is expected, however, that the burst mode could be viable for very low power applications in reducing biasing and housekeeping associated losses if reduced during the burst off time.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122505732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468338
H. Nademi, L. Norum
This paper investigates a Finite-Control-Set Model Predictive Control (FCS-MPC) for the precise control of (un)balanced load currents in Modular Multilevel Converter (MMC). The control objectives are circulating currents minimization inside the converter arms, achieve a capacitors voltage balance and load current control. To achieve the converter constrained optimization and facilitate the implementation on embedded systems, an integrated perturbation analysis and sequential quadratic programming (IPA-SQP) solver is also utilized. As a case study the proposed approach is applied to a grid-connected five-level MMC. The introduced FCS-MPC formulation reduces sensitivity of the converter output voltage to disturbances in grid side and measurement noise with reducing the computational burden. Simulation results reveal the effectiveness of the developed control scheme in cases when operational objectives, e.g., load current reference tracking and disturbance rejection are considered under system model uncertainties.
{"title":"Implicit Finite Control Set Model Predictive current Control for Modular Multilevel Converter based on IPA-SQP algorithm","authors":"H. Nademi, L. Norum","doi":"10.1109/APEC.2016.7468338","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468338","url":null,"abstract":"This paper investigates a Finite-Control-Set Model Predictive Control (FCS-MPC) for the precise control of (un)balanced load currents in Modular Multilevel Converter (MMC). The control objectives are circulating currents minimization inside the converter arms, achieve a capacitors voltage balance and load current control. To achieve the converter constrained optimization and facilitate the implementation on embedded systems, an integrated perturbation analysis and sequential quadratic programming (IPA-SQP) solver is also utilized. As a case study the proposed approach is applied to a grid-connected five-level MMC. The introduced FCS-MPC formulation reduces sensitivity of the converter output voltage to disturbances in grid side and measurement noise with reducing the computational burden. Simulation results reveal the effectiveness of the developed control scheme in cases when operational objectives, e.g., load current reference tracking and disturbance rejection are considered under system model uncertainties.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468109
K. Konishi, T. Mishima, M. Nakaoka
This paper presents a novel prototype of a time-sharing frequency doubler principle-based current-fed zero current soft-switching (ZCS) high frequency resonant (HF-R) inverter for inductive power transfer (IPT) systems. The newly-proposed ZCS HF-R inverter is suitable for producing a higher frequency resonant current with switching power loss reduction by using a middle-class switching frequency insulated-gate-bipolar-power transistor (IGBT). In order to continuously regulate the output power, resonant current phasor control (RCPC) is newly applied. The performances of the newly-proposed IPT resonant power converter are demonstrated by experiment, after which the feasibility of the circuit topology and control method is discussed from a practical point of view.
{"title":"A novel time-sharing current-fed ZCS high frequency inverter-applied resonant DC-DC converter for inductive power transfer","authors":"K. Konishi, T. Mishima, M. Nakaoka","doi":"10.1109/APEC.2016.7468109","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468109","url":null,"abstract":"This paper presents a novel prototype of a time-sharing frequency doubler principle-based current-fed zero current soft-switching (ZCS) high frequency resonant (HF-R) inverter for inductive power transfer (IPT) systems. The newly-proposed ZCS HF-R inverter is suitable for producing a higher frequency resonant current with switching power loss reduction by using a middle-class switching frequency insulated-gate-bipolar-power transistor (IGBT). In order to continuously regulate the output power, resonant current phasor control (RCPC) is newly applied. The performances of the newly-proposed IPT resonant power converter are demonstrated by experiment, after which the feasibility of the circuit topology and control method is discussed from a practical point of view.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131182408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468057
Hao Chen, A. Prasai, D. Divan
This paper presents a novel topology for instantaneous reactive power compensation. The topology is derived from Dynamic-Current or Dyna-C, which is a patented power converter capable of transferring energy for two- or multi-terminal DC, single- and/or multi-phase AC systems. The proposed topology has a modularized low-voltage current source building block that can be stacked for medium-voltage (MV) applications to provide dynamic leading or lagging reactive power. In addition, the phases are coupled through a high-frequency transformer for inter-phase fault isolation among the three-phase. The converter functionality is validated through simulations and experimental results with a 480 V, 75 kVAr prototype.
{"title":"An isolated topology for reactive power compensation with a modularized Dynamic-Current building-block","authors":"Hao Chen, A. Prasai, D. Divan","doi":"10.1109/APEC.2016.7468057","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468057","url":null,"abstract":"This paper presents a novel topology for instantaneous reactive power compensation. The topology is derived from Dynamic-Current or Dyna-C, which is a patented power converter capable of transferring energy for two- or multi-terminal DC, single- and/or multi-phase AC systems. The proposed topology has a modularized low-voltage current source building block that can be stacked for medium-voltage (MV) applications to provide dynamic leading or lagging reactive power. In addition, the phases are coupled through a high-frequency transformer for inter-phase fault isolation among the three-phase. The converter functionality is validated through simulations and experimental results with a 480 V, 75 kVAr prototype.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131263625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468376
Tong Wu, B. Ozpineci, C. Ayers
In this paper, a genetic algorithm- (GA-) based approach is discussed for designing heat sinks based on total heat generation and dissipation for a pre-specified size and shape. This approach combines random iteration processes and genetic algorithms with finite element analysis (FEA) to design the optimized heat sink. With an approach that prefers “survival of the fittest”, a more powerful heat sink can be designed which can cool power electronics more efficiently. Some of the resulting designs can only be 3D printed due to their complexity. In addition to describing the methodology, this paper also includes comparisons of different cases to evaluate the performance of the newly designed heat sink compared to commercially available heat sinks.
{"title":"Genetic algorithm design of a 3D printed heat sink","authors":"Tong Wu, B. Ozpineci, C. Ayers","doi":"10.1109/APEC.2016.7468376","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468376","url":null,"abstract":"In this paper, a genetic algorithm- (GA-) based approach is discussed for designing heat sinks based on total heat generation and dissipation for a pre-specified size and shape. This approach combines random iteration processes and genetic algorithms with finite element analysis (FEA) to design the optimized heat sink. With an approach that prefers “survival of the fittest”, a more powerful heat sink can be designed which can cool power electronics more efficiently. Some of the resulting designs can only be 3D printed due to their complexity. In addition to describing the methodology, this paper also includes comparisons of different cases to evaluate the performance of the newly designed heat sink compared to commercially available heat sinks.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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