Pub Date : 2016-05-12DOI: 10.1109/APEC.2016.7468352
O. Kulkarni, S. Doolla, B. G. Fernandes
This paper proposes a novel automatic mode transition control strategy for multiple inverters to operate in grid-connected and islanded modes without communication. When grid is available, all the inverters operate in grid-tied current control mode and transfer available power to the grid. On grid failure, they automatically shift to conventional droop control mode and shift back to grid-tied current control mode when the grid becomes available. The control signals for mode transition are generated by state machines specific to each inverter. The state machine has appropriate delays to facilitate smooth mode transition. Feasibility of the proposed control strategy is substantiated using MATLAB/SIMULINK simulation results.
{"title":"Mode transition control strategy for multiple inverter based distributed generators operating in grid-connected and stand-alone mode","authors":"O. Kulkarni, S. Doolla, B. G. Fernandes","doi":"10.1109/APEC.2016.7468352","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468352","url":null,"abstract":"This paper proposes a novel automatic mode transition control strategy for multiple inverters to operate in grid-connected and islanded modes without communication. When grid is available, all the inverters operate in grid-tied current control mode and transfer available power to the grid. On grid failure, they automatically shift to conventional droop control mode and shift back to grid-tied current control mode when the grid becomes available. The control signals for mode transition are generated by state machines specific to each inverter. The state machine has appropriate delays to facilitate smooth mode transition. Feasibility of the proposed control strategy is substantiated using MATLAB/SIMULINK simulation results.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120860221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-12DOI: 10.1109/APEC.2016.7468264
D. Mohammadi, S. Ahmed-Zaid
A fault-tolerant topology in a three-phase four-leg inverter which is capable of reducing the common-mode voltage (CMV) during the post-fault condition is presented. The CMV during both post-fault and pre-fault is investigated. This paper proposes a topology to reduce the common-mode voltage during pre- and post-fault operation of the inverter by using the healthy switches. The accompanying simulation results verify the common-mode current reduction during the fault period.
{"title":"Active common-mode voltage reduction in a fault-tolerant three-phase inverter","authors":"D. Mohammadi, S. Ahmed-Zaid","doi":"10.1109/APEC.2016.7468264","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468264","url":null,"abstract":"A fault-tolerant topology in a three-phase four-leg inverter which is capable of reducing the common-mode voltage (CMV) during the post-fault condition is presented. The CMV during both post-fault and pre-fault is investigated. This paper proposes a topology to reduce the common-mode voltage during pre- and post-fault operation of the inverter by using the healthy switches. The accompanying simulation results verify the common-mode current reduction during the fault period.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125615538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The topology of parallel three-phase voltage source inverters (VSIs) has been widely utilized to raise system power rating, but zero-sequence circulating currents (ZSCCs) are generated by control effect and hardware parameter differences. ZSCCs could lead to current distortion and impact the system stability. The model predictive control (MPC) method has been applied to the inverters to get high robustness, fast dynamic response and low switching frequency. However, the MPC method is rarely used in parallel inverters because of the ZSCCs problem. This paper proposes an improved MPC algorithm for parallel system to track the reference currents as well as suppress the ZSCCs. The contribution of each space vector to ZSCCs is analyzed and the cost function is redesigned in the new method. The cost function will pick out the optimal vectors to guarantee the control requirements. Experimental results verified that the improved algorithm is effective and performs well in both current tracking and ZSCCs suppression.
{"title":"A novel model predictive control algorithm to suppress the zero-sequence circulating currents for parallel three-phase voltage source inverters","authors":"Zicheng Zhang, Alian Chen, Xiangyang Xing, Chenghui Zhang","doi":"10.1109/APEC.2016.7468365","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468365","url":null,"abstract":"The topology of parallel three-phase voltage source inverters (VSIs) has been widely utilized to raise system power rating, but zero-sequence circulating currents (ZSCCs) are generated by control effect and hardware parameter differences. ZSCCs could lead to current distortion and impact the system stability. The model predictive control (MPC) method has been applied to the inverters to get high robustness, fast dynamic response and low switching frequency. However, the MPC method is rarely used in parallel inverters because of the ZSCCs problem. This paper proposes an improved MPC algorithm for parallel system to track the reference currents as well as suppress the ZSCCs. The contribution of each space vector to ZSCCs is analyzed and the cost function is redesigned in the new method. The cost function will pick out the optimal vectors to guarantee the control requirements. Experimental results verified that the improved algorithm is effective and performs well in both current tracking and ZSCCs suppression.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-12DOI: 10.1109/APEC.2016.7468177
Qing Ye, Hui Li
In this paper, the stability of solid state transformer (SST)-paralleled inverters system is investigated by using the unified impedance-based stability criterion (UIBSC). Theoretical analysis reveals that the output impedance characteristics of SST are frequency-dependent and multiple resonances can happen in the SST-paralleled inverters system. A lead-lag controller and a negative impedance feedback controller are developed to mitigate the resonances within and beyond the current control loop respectively. Without additional sensors, the proposed negative impedance feedback control is able to achieve better damping function in a much wider frequency range compared to other methods. In addition, the proposed control method is less sensitive to the time delay. Simulation results are provided to validate the functionality of proposed methods.
{"title":"Stability analysis and improvement of solid state transformer (SST)-paralleled inverters system using negative impedance feedback control","authors":"Qing Ye, Hui Li","doi":"10.1109/APEC.2016.7468177","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468177","url":null,"abstract":"In this paper, the stability of solid state transformer (SST)-paralleled inverters system is investigated by using the unified impedance-based stability criterion (UIBSC). Theoretical analysis reveals that the output impedance characteristics of SST are frequency-dependent and multiple resonances can happen in the SST-paralleled inverters system. A lead-lag controller and a negative impedance feedback controller are developed to mitigate the resonances within and beyond the current control loop respectively. Without additional sensors, the proposed negative impedance feedback control is able to achieve better damping function in a much wider frequency range compared to other methods. In addition, the proposed control method is less sensitive to the time delay. Simulation results are provided to validate the functionality of proposed methods.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124310896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-12DOI: 10.1109/APEC.2016.7468115
D. G. Lamar, M. Arias, Alberto Rodríguez, Javier Sebastián, A. Fernández, J. Villarejo
Nowadays, the solid-sate lighting technology evolution has changed traditional solutions in lighting. High-Brightness Light-Emitting Diodes (HB-LEDs) have become very attractive light sources due to their excellent characteristics: high efficiency, high life-time and low maintenance. It is evident that HB-LED drivers must be durable and efficient to achieve these advantages. Moreover, for replacing incandescent bulbs, the ac-dc HB-LED driver must be low cost and comply with international regulations (i.e. injection of low frequency harmonics into the mains). Traditionally, authors have focused its efforts on increasing efficiency. All these solutions obviate the elimination of traditional electrolytic capacitor of ac to dc converters, highlighting that this is the price to pay for a very low-cost solution. This paper presents a new proposal to design a simple and low-cost ac to dc HB-LED driver for retrofit lamps without electrolytic capacitor. The proposed solution comes from a very well-known technique used in the past: Active Input Current Shapers (AICS), but in this case without electrolytic capacitor. If the electrolytic capacitor of an AICS is removed, then low frequency ripple arises in its intermediate dc bus, increasing the distortion of the line input which already has appreciable distortion. However, the increase of distortion is very slight. Also, the low frequency ripple is not transferred to the output due to the high output dynamic response of AICS, avoiding flickering. This paper presents a theoretical analysis that guarantees a trade of between compliance with international regulations and the use of other capacitor technologies different from the electrolytic one. Finally, a 24W experimental prototype has been built and tested in order to validate the theoretical results presented in this digest.
{"title":"A sustained increase of input current distortion in active input current shapers to eliminate electrolytic capacitor for designing ac to dc HB-LED drivers for retrofit lamps applications","authors":"D. G. Lamar, M. Arias, Alberto Rodríguez, Javier Sebastián, A. Fernández, J. Villarejo","doi":"10.1109/APEC.2016.7468115","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468115","url":null,"abstract":"Nowadays, the solid-sate lighting technology evolution has changed traditional solutions in lighting. High-Brightness Light-Emitting Diodes (HB-LEDs) have become very attractive light sources due to their excellent characteristics: high efficiency, high life-time and low maintenance. It is evident that HB-LED drivers must be durable and efficient to achieve these advantages. Moreover, for replacing incandescent bulbs, the ac-dc HB-LED driver must be low cost and comply with international regulations (i.e. injection of low frequency harmonics into the mains). Traditionally, authors have focused its efforts on increasing efficiency. All these solutions obviate the elimination of traditional electrolytic capacitor of ac to dc converters, highlighting that this is the price to pay for a very low-cost solution. This paper presents a new proposal to design a simple and low-cost ac to dc HB-LED driver for retrofit lamps without electrolytic capacitor. The proposed solution comes from a very well-known technique used in the past: Active Input Current Shapers (AICS), but in this case without electrolytic capacitor. If the electrolytic capacitor of an AICS is removed, then low frequency ripple arises in its intermediate dc bus, increasing the distortion of the line input which already has appreciable distortion. However, the increase of distortion is very slight. Also, the low frequency ripple is not transferred to the output due to the high output dynamic response of AICS, avoiding flickering. This paper presents a theoretical analysis that guarantees a trade of between compliance with international regulations and the use of other capacitor technologies different from the electrolytic one. Finally, a 24W experimental prototype has been built and tested in order to validate the theoretical results presented in this digest.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134514702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468043
Steven Chung, M. Nasr, David Guirguis, Masafumi Otsuka, S. Poshtkouhi, David K. W. Li, V. Palaniappan, David Romero, C. Amon, R. Orr, O. Trescases
This paper explores the multi-disciplinary design challenges in building a 240 VAC, 2 kVA modular single-phase inverter with high power-density using wide-bandgap transistors. The compromise between the electrical and mechanical design is extremely important in any high-density power converter. In this work the electrical and mechanical systems were iteratively co-designed using detailed 3D thermal and air-flow simulations. Custom copper heat-sinks and heat-pipes were developed for optimal thermal management. The inverter uses three soft-switching sub-inverters in parallel, which are controlled using a novel digital Hysteretic Current Mode Control (HCMC) scheme. To achieve a flat high efficiency curve with low THD over a wide load range, two operating modes are used: 1) Boundary Conduction Mode (BCM) with a slight negative inductor valley current for soft-switching, and 2) Continuous Conduction Mode (CCM) to limit the required saturation current in the inductors. The design of an active power decoupling scheme to minimize input capacitance is also discussed. The designed single-phase inverter has a volume of 33.1 in3 and resulting theoretical power-density of 60.3 W/in3 at 2 kW load. A measured efficiency of 97.7% is achieved for a single sub-inverter with 4.5% THD at 632.7 W.
{"title":"Thermal and electrical co-design of a modular high-density single-phase inverter using wide-bandgap devices","authors":"Steven Chung, M. Nasr, David Guirguis, Masafumi Otsuka, S. Poshtkouhi, David K. W. Li, V. Palaniappan, David Romero, C. Amon, R. Orr, O. Trescases","doi":"10.1109/APEC.2016.7468043","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468043","url":null,"abstract":"This paper explores the multi-disciplinary design challenges in building a 240 VAC, 2 kVA modular single-phase inverter with high power-density using wide-bandgap transistors. The compromise between the electrical and mechanical design is extremely important in any high-density power converter. In this work the electrical and mechanical systems were iteratively co-designed using detailed 3D thermal and air-flow simulations. Custom copper heat-sinks and heat-pipes were developed for optimal thermal management. The inverter uses three soft-switching sub-inverters in parallel, which are controlled using a novel digital Hysteretic Current Mode Control (HCMC) scheme. To achieve a flat high efficiency curve with low THD over a wide load range, two operating modes are used: 1) Boundary Conduction Mode (BCM) with a slight negative inductor valley current for soft-switching, and 2) Continuous Conduction Mode (CCM) to limit the required saturation current in the inductors. The design of an active power decoupling scheme to minimize input capacitance is also discussed. The designed single-phase inverter has a volume of 33.1 in3 and resulting theoretical power-density of 60.3 W/in3 at 2 kW load. A measured efficiency of 97.7% is achieved for a single sub-inverter with 4.5% THD at 632.7 W.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115284223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468122
J. A. Abu Qahouq, Lin Zhang, Yuan Cao, Bharat Balasubramanian
This paper presents a DC-DC power converter control scheme and system architecture for batteries which are connected in parallel in order to maintain State-Of-Charge (SOC) balancing between batteries without the need for additional circuitries and their associated controllers. When the battery cells or battery packs are connected in parallel, it is desired to maintain SOC balancing during both charging mode and discharging mode. Using conventional balancing circuits is energy inefficient and/or might be complicated/not suitable. This paper addresses this by presenting a controller that is able to maintain a real-time natural charge balance between the in parallel connected batteries while maintaining output voltage regulation at the same time.
{"title":"DC-DC power converter controller for SOC balancing of paralleled battery system","authors":"J. A. Abu Qahouq, Lin Zhang, Yuan Cao, Bharat Balasubramanian","doi":"10.1109/APEC.2016.7468122","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468122","url":null,"abstract":"This paper presents a DC-DC power converter control scheme and system architecture for batteries which are connected in parallel in order to maintain State-Of-Charge (SOC) balancing between batteries without the need for additional circuitries and their associated controllers. When the battery cells or battery packs are connected in parallel, it is desired to maintain SOC balancing during both charging mode and discharging mode. Using conventional balancing circuits is energy inefficient and/or might be complicated/not suitable. This paper addresses this by presenting a controller that is able to maintain a real-time natural charge balance between the in parallel connected batteries while maintaining output voltage regulation at the same time.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468377
Jason C. Neely, L. Rashkin, Marvin A. Cook, David G. Wilson, Steven F. Glover
Future U.S. Navy ships will require power systems that meet more stringent agility, efficiency, scalability, controllability and resiliency requirements. Modularity and the ability to interconnect power systems having their own energy storage, generation, and loads is an enabling capability. To aid in the design of power system controls, much of what has been learned from advances in the control of networked microgrids is being applied. Developing alternative methods for controlling and analyzing these systems will provide insight into tradeoffs that can be made during the design phase. This paper considers the problem of electric ship power disturbances in response to pulsed loads, in particular, to electromagnetic launch systems. Recent literature has indicated that there exists a trade-off in information and power flow and that intelligent, coordinated control of power flow in a microgrid system (i.e. such as an electric ship) can modify energy storage hardware requirements. The control presented herein was developed to provide the necessary flexibility with little computational burden. It is described analytically and then demonstrated in simulation and hardware.
{"title":"Evaluation of power flow control for an all-electric warship power system with pulsed load applications","authors":"Jason C. Neely, L. Rashkin, Marvin A. Cook, David G. Wilson, Steven F. Glover","doi":"10.1109/APEC.2016.7468377","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468377","url":null,"abstract":"Future U.S. Navy ships will require power systems that meet more stringent agility, efficiency, scalability, controllability and resiliency requirements. Modularity and the ability to interconnect power systems having their own energy storage, generation, and loads is an enabling capability. To aid in the design of power system controls, much of what has been learned from advances in the control of networked microgrids is being applied. Developing alternative methods for controlling and analyzing these systems will provide insight into tradeoffs that can be made during the design phase. This paper considers the problem of electric ship power disturbances in response to pulsed loads, in particular, to electromagnetic launch systems. Recent literature has indicated that there exists a trade-off in information and power flow and that intelligent, coordinated control of power flow in a microgrid system (i.e. such as an electric ship) can modify energy storage hardware requirements. The control presented herein was developed to provide the necessary flexibility with little computational burden. It is described analytically and then demonstrated in simulation and hardware.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468012
S. S. R. Bonthu, Seungdeog Choi
This paper presents the optimal design procedure to develop multi-phase external rotor permanent magnet assisted synchronous reluctance machines (EPMa-SynRMs). With its higher torque density and higher power density compared to the internal rotor PMa-SynRM, external rotor PMa-SynRM is best suitable in applications to electric bikes and aircrafts. Enormous amount of research has been done in optimizing internal rotor PM machines. However, an efficient optimization technique to develop a five-phase EPMa-SynRM is not presented in the literature. The optimization of the EPMa-SynRMs is important to provide better performance characteristics and controllability in terms of lower back-EMF harmonics and cogging torque for critical applications. In this study, a detailed analysis on developing magnetic equivalent circuit for the multi-phase EPMa-SynRM is presented. Differential evolution (DE) optimization algorithm is utilized to develop the optimal models for five-phase EPMa-SynRM. The effects of rotational forces on the rotor in both internal and external rotor PMa-SynRMs are analytically studied. A thermal model for the proposed EPMa-SynRM structure is presented. Initial simulation results for stress and thermal heat flow for the proposed designs are presented. Furthermore, electromagnetic finite element simulation results such as back-EMF, flux linkage, cogging torque, and their harmonics are presented for the developed five-phase EPMa-SynRM model. The best design which has lower back-EMF harmonics and cogging torque is chosen to fabricate and conduct experimental tests.
{"title":"Design procedure for multi-phase external rotor permanent magnet assisted synchronous reluctance machines","authors":"S. S. R. Bonthu, Seungdeog Choi","doi":"10.1109/APEC.2016.7468012","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468012","url":null,"abstract":"This paper presents the optimal design procedure to develop multi-phase external rotor permanent magnet assisted synchronous reluctance machines (EPMa-SynRMs). With its higher torque density and higher power density compared to the internal rotor PMa-SynRM, external rotor PMa-SynRM is best suitable in applications to electric bikes and aircrafts. Enormous amount of research has been done in optimizing internal rotor PM machines. However, an efficient optimization technique to develop a five-phase EPMa-SynRM is not presented in the literature. The optimization of the EPMa-SynRMs is important to provide better performance characteristics and controllability in terms of lower back-EMF harmonics and cogging torque for critical applications. In this study, a detailed analysis on developing magnetic equivalent circuit for the multi-phase EPMa-SynRM is presented. Differential evolution (DE) optimization algorithm is utilized to develop the optimal models for five-phase EPMa-SynRM. The effects of rotational forces on the rotor in both internal and external rotor PMa-SynRMs are analytically studied. A thermal model for the proposed EPMa-SynRM structure is presented. Initial simulation results for stress and thermal heat flow for the proposed designs are presented. Furthermore, electromagnetic finite element simulation results such as back-EMF, flux linkage, cogging torque, and their harmonics are presented for the developed five-phase EPMa-SynRM model. The best design which has lower back-EMF harmonics and cogging torque is chosen to fabricate and conduct experimental tests.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123137257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468225
N. Shafiei, S. A. Arefifar, Mohammad Ali Saket, M. Ordonez
In order to support different types of rechargeable batteries (e.g. Li-Ion, Lead-Acid, NiMh), the design of universal battery chargers must focus on wide conversion efficiency instead of traditional peak efficiency design. Wide efficiency is the ability to maintain high performance within the nominal output power while supporting the charging cycle voltage of different battery technologies. The objective of this paper is to tackle this new wide efficiency technical challenge and provide a design methodology that focuses on multiple operating points rather than obtaining peak efficiency at one operating point. The universal battery charger is expected to provide a demanding output voltage range between nominal and 1.5 times nominal and sustaining maximum power delivery with high efficiency. The proposed LLC converter design procedure successfully selects the resonant tank elements and operating frequencies to maximize efficiency for the maximum power region. The design procedure employs analytical equations and a Tabu Search algorithm (TS) for a 96V DC, 960W universal battery charger implementation. The experimental results exhibit the excellent performance of the designed converter, which has an average efficiency of 96.1% within the nominal output power delivery range (between 96V DC and 144V DC output voltage range) with extreme regulation capability.
为了支持不同类型的可充电电池(如锂离子电池、铅酸电池、镍氢电池)，通用电池充电器的设计必须注重宽转换效率，而不是传统的峰值效率设计。宽效率是指在额定输出功率范围内保持高性能，同时支持不同电池技术的充电周期电压的能力。本文的目标是解决这一新的宽效率技术挑战，并提供一种设计方法，该方法侧重于多个工作点，而不是在一个工作点上获得最高效率。通用电池充电器预计将提供一个苛刻的输出电压范围之间的标称和1.5倍标称和维持高效率的最大功率输送。提出的LLC变换器设计程序成功地选择了谐振槽元件和工作频率，以最大限度地提高功率区域的效率。本设计程序采用解析方程和禁忌搜索算法(TS)对一个96V直流、960W通用电池充电器进行实现。实验结果表明，所设计的变换器性能优异，在额定输出功率范围内(96V DC ~ 144V DC输出电压范围)平均效率为96.1%，具有极强的调节能力。
{"title":"High efficiency LLC converter design for universal battery chargers","authors":"N. Shafiei, S. A. Arefifar, Mohammad Ali Saket, M. Ordonez","doi":"10.1109/APEC.2016.7468225","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468225","url":null,"abstract":"In order to support different types of rechargeable batteries (e.g. Li-Ion, Lead-Acid, NiMh), the design of universal battery chargers must focus on wide conversion efficiency instead of traditional peak efficiency design. Wide efficiency is the ability to maintain high performance within the nominal output power while supporting the charging cycle voltage of different battery technologies. The objective of this paper is to tackle this new wide efficiency technical challenge and provide a design methodology that focuses on multiple operating points rather than obtaining peak efficiency at one operating point. The universal battery charger is expected to provide a demanding output voltage range between nominal and 1.5 times nominal and sustaining maximum power delivery with high efficiency. The proposed LLC converter design procedure successfully selects the resonant tank elements and operating frequencies to maximize efficiency for the maximum power region. The design procedure employs analytical equations and a Tabu Search algorithm (TS) for a 96V DC, 960W universal battery charger implementation. The experimental results exhibit the excellent performance of the designed converter, which has an average efficiency of 96.1% within the nominal output power delivery range (between 96V DC and 144V DC output voltage range) with extreme regulation capability.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114678932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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