Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804399
M. Goto, Y. Honda, T. Watabe, K. Hagiwara, M. Nanba, Yoshinori Iguch, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto
We report in-pixel analog-to-digital converters (ADCs) using event-driven correlated double sampling (CDS) for stacked silicon-on-insulator (SOI) image sensors. The pulse-frequency-modulation ADCs enable a pixel-parallel operation that leads to superior imaging performance. We designed a novel CDS for an ADC comprising comparators, capacitors, and timing control logic circuits to generate clocks for in-pixel operation to suppress reset noise. The developed ADC is successfully confirmed to exhibit an excellent linearity in a wide dynamic range of 120 dB and it shows noise reduction effects, indicating the feasibility of high-performance pixel-level imaging for next-generation image sensors.
{"title":"In-pixel A/D converters with 120-dB dynamic range using event-driven correlated double sampling for stacked SOI image sensors","authors":"M. Goto, Y. Honda, T. Watabe, K. Hagiwara, M. Nanba, Yoshinori Iguch, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/S3S.2016.7804399","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804399","url":null,"abstract":"We report in-pixel analog-to-digital converters (ADCs) using event-driven correlated double sampling (CDS) for stacked silicon-on-insulator (SOI) image sensors. The pulse-frequency-modulation ADCs enable a pixel-parallel operation that leads to superior imaging performance. We designed a novel CDS for an ADC comprising comparators, capacitors, and timing control logic circuits to generate clocks for in-pixel operation to suppress reset noise. The developed ADC is successfully confirmed to exhibit an excellent linearity in a wide dynamic range of 120 dB and it shows noise reduction effects, indicating the feasibility of high-performance pixel-level imaging for next-generation image sensors.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132412802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804391
B. Martineau, C. Jany, F. Todeschini, D. Morche, E. Mercier
This paper reports the design of a Wake up Receiver taking advantage of the 28nm UTBB FD-SOI. This design is motivated by the integration of the IOT node containing processing, connectivity and sensing in a unique System on Chip.
{"title":"Towards fully integrated 28nm UTBB FD-SOI IoT node: The sub-50μW RF receiver","authors":"B. Martineau, C. Jany, F. Todeschini, D. Morche, E. Mercier","doi":"10.1109/S3S.2016.7804391","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804391","url":null,"abstract":"This paper reports the design of a Wake up Receiver taking advantage of the 28nm UTBB FD-SOI. This design is motivated by the integration of the IOT node containing processing, connectivity and sensing in a unique System on Chip.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126637885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804386
A. Vandooren, A. Alian, A. Verhulst, J. Franco, R. Rooyackers, Q. Smets, D. Verreck, N. Waldron, D. Mocuta, N. Collaert
We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.
{"title":"Tunnel FETs for low power electronics","authors":"A. Vandooren, A. Alian, A. Verhulst, J. Franco, R. Rooyackers, Q. Smets, D. Verreck, N. Waldron, D. Mocuta, N. Collaert","doi":"10.1109/S3S.2016.7804386","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804386","url":null,"abstract":"We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125829147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804383
A. Salman, F. Farbiz, A. Appaswamy
This paper is a review of the latest advances in ESD protection for analog and digital technologies. The paper will introduce the latest ESD protection devices for FinFET and FDSOI technologies such as Field effect diode, Field effect resistor. We will introduce an example of innovation for analog ESD protection focusing on system level automotive applications namely Mutual ballasting layout technique.
{"title":"State-of-the-art ESD protection devices and techniques for digital and analog technologies","authors":"A. Salman, F. Farbiz, A. Appaswamy","doi":"10.1109/S3S.2016.7804383","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804383","url":null,"abstract":"This paper is a review of the latest advances in ESD protection for analog and digital technologies. The paper will introduce the latest ESD protection devices for FinFET and FDSOI technologies such as Field effect diode, Field effect resistor. We will introduce an example of innovation for analog ESD protection focusing on system level automotive applications namely Mutual ballasting layout technique.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116280605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804395
Takahiro Yoshida, J. Ida, Takashi Horii, M. Okihara, Y. Arai
It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N-. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.
{"title":"Super steep subthreshold slope PN-body tied SOI FET's of ultra low drain voltage=0.1V with body bias below 1.0V","authors":"Takahiro Yoshida, J. Ida, Takashi Horii, M. Okihara, Y. Arai","doi":"10.1109/S3S.2016.7804395","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804395","url":null,"abstract":"It was demonstrated that the body bias appearing the super steep Subthreshold Slope (SS) reduces from over 5V to below 1V on the PN-body tied SOIFET's which show the super steep SS with the ultralow drain voltage of 0.1V, when the impurity concentration of the N region on the body tied area is redesigned from the high concentration of the N+ to the low N-. The 3D device simulations also confirmed it and indicated that the optimum length of the N region exits on the different impurity concentration of it for appearing the super steep SS with the low body bias.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"2012 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132678865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804401
Xuan-Thuan Nguyen, Hong-Thu Nguyen, C. Pham
This paper presents the efficient architecture of a bitmap-index-based query processor for fast data analytics on 65-nm SOTB CMOS process. The post-simulation with a supply voltage of 0.55 V indicates that the processor could operate at 125 MHz and process up to 232 million records/second in case 32 keys and queries are utilized. Furthermore, by applying the reverse body bias voltage of -2 V, the leakage current reduces up to 73 times as compared to that in normal body bias.
{"title":"A high-performance bitmap-index-based query processor on 65-nm SOTB CMOS process","authors":"Xuan-Thuan Nguyen, Hong-Thu Nguyen, C. Pham","doi":"10.1109/S3S.2016.7804401","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804401","url":null,"abstract":"This paper presents the efficient architecture of a bitmap-index-based query processor for fast data analytics on 65-nm SOTB CMOS process. The post-simulation with a supply voltage of 0.55 V indicates that the processor could operate at 125 MHz and process up to 232 million records/second in case 32 keys and queries are utilized. Furthermore, by applying the reverse body bias voltage of -2 V, the leakage current reduces up to 73 times as compared to that in normal body bias.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804389
D. Rossi
Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth Internet of-Things (IoT) applications requiring near-sensor processing. A promising approach to achieve major energy efficiency improvements is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable for performance-constrained applications. The PULP platform leverages multi-core parallelism with explicitly-managed shared L1 memory to overcome performance degradation at low voltage, while maintaining the flexibility and programmability typical of instruction processors. PULP supports OpenMP, OpenCL, and OpenVX parallel programming with hardware support for energy efficient synchronization. Multiple silicon implementations of PULP have been taped out and achieve hundreds of GOPS/W on video, audio, inertial sensor data processing and classification, within power envelopes of a few milliwatts. PULP hardware and software are open-source, with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.
{"title":"Sub-pJ per operation scalable computing: The PULP experience","authors":"D. Rossi","doi":"10.1109/S3S.2016.7804389","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804389","url":null,"abstract":"Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth Internet of-Things (IoT) applications requiring near-sensor processing. A promising approach to achieve major energy efficiency improvements is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable for performance-constrained applications. The PULP platform leverages multi-core parallelism with explicitly-managed shared L1 memory to overcome performance degradation at low voltage, while maintaining the flexibility and programmability typical of instruction processors. PULP supports OpenMP, OpenCL, and OpenVX parallel programming with hardware support for energy efficient synchronization. Multiple silicon implementations of PULP have been taped out and achieve hundreds of GOPS/W on video, audio, inertial sensor data processing and classification, within power envelopes of a few milliwatts. PULP hardware and software are open-source, with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116172661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804397
K. Arai, C. Pham
This paper presents an all-digital PLL (ADPLL) which synthesizes any frequency using the successive approximation (SAR) algorithm. The proposed ADPLL consists of a high-frequency resolution digitally controlled oscillator, a time-to-digital converter, a frequency detection divider and the SAR controller. The proposed ADPLL is designed using 65nm SOTB CMOS process and occupies an area of 124.6×68.4μm2. The range of output frequency is from 577 to 1876MHz at 1.0V power supply. The power consumption is 0.46mW at 1876MHz. The number of clocks to lock-in is 10 clocks in the best case and 34 clocks in the typical cases.
{"title":"An all-digital PLL with SAR frequency locking system in 65nm SOTB CMOS","authors":"K. Arai, C. Pham","doi":"10.1109/S3S.2016.7804397","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804397","url":null,"abstract":"This paper presents an all-digital PLL (ADPLL) which synthesizes any frequency using the successive approximation (SAR) algorithm. The proposed ADPLL consists of a high-frequency resolution digitally controlled oscillator, a time-to-digital converter, a frequency detection divider and the SAR controller. The proposed ADPLL is designed using 65nm SOTB CMOS process and occupies an area of 124.6×68.4μm2. The range of output frequency is from 577 to 1876MHz at 1.0V power supply. The power consumption is 0.46mW at 1876MHz. The number of clocks to lock-in is 10 clocks in the best case and 34 clocks in the typical cases.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122825002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804398
M. Motoyoshi, T. Miyoshi, M. Ikebec, Y. Arai
This paper presents the experimental result of a fabricated prototype with 3-μm-diameter Au cone-bump connections with adhesive injection, and compares it with that of an indium microbump (μ-bump). The resistance of the 3-μm-diameter Au cone bump is approximately 0.25 Ω. We also investigated the influence of stress caused by bump junction on the MOS characteristics.
{"title":"3D stacked SOI-CMOS pixel detector using Au micro-bump junctions","authors":"M. Motoyoshi, T. Miyoshi, M. Ikebec, Y. Arai","doi":"10.1109/S3S.2016.7804398","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804398","url":null,"abstract":"This paper presents the experimental result of a fabricated prototype with 3-μm-diameter Au cone-bump connections with adhesive injection, and compares it with that of an indium microbump (μ-bump). The resistance of the 3-μm-diameter Au cone bump is approximately 0.25 Ω. We also investigated the influence of stress caused by bump junction on the MOS characteristics.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/S3S.2016.7804387
R. Doria, R. Trevisoli, M. de Souza, M. Pavanello, D. Flandre
This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.
本文旨在首次展示利用反向偏置来改善由自级联码结构组成的25 nm长n型和p型UTBB SOI mosfet的电流反射镜的模拟性能。使用后门偏置可以将p型器件的固有增益提高约7 dB，使其高于具有等效信道长度的单个器件的固有增益，而镜像精度则比单个器件提高20%。
{"title":"Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors","authors":"R. Doria, R. Trevisoli, M. de Souza, M. Pavanello, D. Flandre","doi":"10.1109/S3S.2016.7804387","DOIUrl":"https://doi.org/10.1109/S3S.2016.7804387","url":null,"abstract":"This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130040868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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