Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493370
K. Tatas
Performance analysis and design space exploration of bufferless Networks-on-Chip is done mainly through cycle accurate simulation which is time-consuming, while an analytical model seems out of reach for now. In order to raise the level of abstraction as well as capture the inherently probabilistic behavior of deflection routing, this paper presents a methodology for employing Markov chain models in the analysis of the behavior of bufferless Networks-on-Chip. A formal way of describing a bufferless NoC topology as a set of discrete-time Markov chains is presented. It is demonstrated that by combining this description with the network average distance, it is possible to obtain the expectation of the number of hops between any pair of nodes in the network as a function of the flit deflection probability. Comparisons between the proposed model and cycle-accurate simulation show that the proposed methodology achieves good accuracy at the useful injection rate range, with negligible computational cost.
{"title":"Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs","authors":"K. Tatas","doi":"10.1109/MOCAST52088.2021.9493370","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493370","url":null,"abstract":"Performance analysis and design space exploration of bufferless Networks-on-Chip is done mainly through cycle accurate simulation which is time-consuming, while an analytical model seems out of reach for now. In order to raise the level of abstraction as well as capture the inherently probabilistic behavior of deflection routing, this paper presents a methodology for employing Markov chain models in the analysis of the behavior of bufferless Networks-on-Chip. A formal way of describing a bufferless NoC topology as a set of discrete-time Markov chains is presented. It is demonstrated that by combining this description with the network average distance, it is possible to obtain the expectation of the number of hops between any pair of nodes in the network as a function of the flit deflection probability. Comparisons between the proposed model and cycle-accurate simulation show that the proposed methodology achieves good accuracy at the useful injection rate range, with negligible computational cost.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130723642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493336
Jinming Sun, Yanqiu Huang, Wanli Yu, A. Ortiz
System identification has been used in various domains for analyzing system properties and carrying out filtering, prediction and automatic control. Prediction error method (PEM) is one of the classic methods to estimate system parameters and exploit dynamical structure of the studied system; while neural network (NN) is favorable for black-box systems with unknown structures. As the popularity of Internet of Things (IoT) and Cyber-physical systems (CPS) increases, the identification tasks are moving more towards resource-constrained devices. Accordingly, some studies incorporate system prior knowledge into NN to improve its efficiency. However, it is unclear whether the adapted NN outperforms the classic PEM.This paper provides a fair comparison between two techniques in terms of estimation accuracy and speed on several common nonlinear systems. The results indicate that NN is wider applicable and accurate, but more expensive from computational perspective; whereas PEM is more lightweight, but has limitations when the system input has frequent abrupt changes.
{"title":"Nonlinear System Identification: Prediction Error Method vs Neural Network","authors":"Jinming Sun, Yanqiu Huang, Wanli Yu, A. Ortiz","doi":"10.1109/MOCAST52088.2021.9493336","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493336","url":null,"abstract":"System identification has been used in various domains for analyzing system properties and carrying out filtering, prediction and automatic control. Prediction error method (PEM) is one of the classic methods to estimate system parameters and exploit dynamical structure of the studied system; while neural network (NN) is favorable for black-box systems with unknown structures. As the popularity of Internet of Things (IoT) and Cyber-physical systems (CPS) increases, the identification tasks are moving more towards resource-constrained devices. Accordingly, some studies incorporate system prior knowledge into NN to improve its efficiency. However, it is unclear whether the adapted NN outperforms the classic PEM.This paper provides a fair comparison between two techniques in terms of estimation accuracy and speed on several common nonlinear systems. The results indicate that NN is wider applicable and accurate, but more expensive from computational perspective; whereas PEM is more lightweight, but has limitations when the system input has frequent abrupt changes.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132911437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493395
T. Karimov, O. Druzhina, A. Karimov, A. Tutueva, D. Butusov
Sensors with coupled inductive coils are used in many applications: for metal detection, for linear and angular displacements measurements, for magnetometry, etc. One of the promising ways to increase technical characteristics of these sensors, such as sensitivity, is the use of a chaotic oscillator to excite the transmitting coil and constructing the path from the receiving coil back to the oscillator. The paper proposes several topologies of sensor circuits with coupled inductances, a technique for including inductive coils in chaotic circuits with their minimal modification, and discusses methods for detecting the measurement signal. As a result, we designed a proximity sensor and shown its high performance in a numerical experiment.
{"title":"Sensitive Chaotic Circuits with Coupled Inductances","authors":"T. Karimov, O. Druzhina, A. Karimov, A. Tutueva, D. Butusov","doi":"10.1109/MOCAST52088.2021.9493395","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493395","url":null,"abstract":"Sensors with coupled inductive coils are used in many applications: for metal detection, for linear and angular displacements measurements, for magnetometry, etc. One of the promising ways to increase technical characteristics of these sensors, such as sensitivity, is the use of a chaotic oscillator to excite the transmitting coil and constructing the path from the receiving coil back to the oscillator. The paper proposes several topologies of sensor circuits with coupled inductances, a technique for including inductive coils in chaotic circuits with their minimal modification, and discusses methods for detecting the measurement signal. As a result, we designed a proximity sensor and shown its high performance in a numerical experiment.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493358
V. Papanikolaou, Nikos A. Mitsiou, P. Diamantoulakis, S. Goudos, G. Karagiannidis
In this paper, we introduce a multiple access protocol, termed hierarchical non-orthogonal multiple access (HiNOMA), optimized for fog-radio access networks (F-RANs). Resource allocation optimization is deemed critical in order to guarantee the users’ fairness in the network, while energy efficiency can be increased through energy harvesting (EH) at the user equipment (UE) nodes. Therefore, the HiNOMA protocol with energy harvesting capabilities is examined for F-RANs, leading to the optimization of the proportional fairness metric. Finally, numerical results reveal the effectiveness of the joint design and the interesting trade-off between harvested power and achievable rate in the case of F-RAN.
{"title":"On the Resource Allocation of Hierarchical NOMA for Fog-RAN with Energy Harvesting","authors":"V. Papanikolaou, Nikos A. Mitsiou, P. Diamantoulakis, S. Goudos, G. Karagiannidis","doi":"10.1109/MOCAST52088.2021.9493358","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493358","url":null,"abstract":"In this paper, we introduce a multiple access protocol, termed hierarchical non-orthogonal multiple access (HiNOMA), optimized for fog-radio access networks (F-RANs). Resource allocation optimization is deemed critical in order to guarantee the users’ fairness in the network, while energy efficiency can be increased through energy harvesting (EH) at the user equipment (UE) nodes. Therefore, the HiNOMA protocol with energy harvesting capabilities is examined for F-RANs, leading to the optimization of the proportional fairness metric. Finally, numerical results reveal the effectiveness of the joint design and the interesting trade-off between harvested power and achievable rate in the case of F-RAN.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115745860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493350
F. Bahnsen, Vanessa Klebe, Goerschwin Fey
Artificial Neural Networks (ANN) are increasingly deployed in various applications and devices using hardware accelerators. However, faults in the processing hardware can affect the output of the ANN and, thus, the reliability of the application using it. Analyzing the effect of hardware faults on the application at design time is essential but non-trivial.We introduce a framework to emulate ANN inference on hardware resource descriptions under hardware faults. Hardware architecture, scheduling, and fault models are fully adaptable. An in-depth controlled experiment shows how hardware faults jeopardize any robustness guar-antees. Benchmark experiments on state-of-the-art ANN demonstrate the scalability of our framework.
{"title":"Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference","authors":"F. Bahnsen, Vanessa Klebe, Goerschwin Fey","doi":"10.1109/MOCAST52088.2021.9493350","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493350","url":null,"abstract":"Artificial Neural Networks (ANN) are increasingly deployed in various applications and devices using hardware accelerators. However, faults in the processing hardware can affect the output of the ANN and, thus, the reliability of the application using it. Analyzing the effect of hardware faults on the application at design time is essential but non-trivial.We introduce a framework to emulate ANN inference on hardware resource descriptions under hardware faults. Hardware architecture, scheduling, and fault models are fully adaptable. An in-depth controlled experiment shows how hardware faults jeopardize any robustness guar-antees. Benchmark experiments on state-of-the-art ANN demonstrate the scalability of our framework.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493341
Mohsen Khajoee, H. Moradi
High-quality, high-production-rate machining operations are significantly hindered by the regenerative chatter. Therefore, chatter suppression is of great significance; and active control is one of the best ways to curb it. In this paper, the orthogonal turning process is modeled as a single-degree-of-freedom system that includes the effect of tool wear; and described through a delay differential equation (DDE). Based on the model, stability lobes diagrams are obtained by the trial and error. The actuator force is the input for the control system and the tool vibration is the output. A classical PID controller is designed to improve the stability of the process and curb the self-excited vibrations. The controller is then tuned in order to achieve the vibration's suppression, short settling time, low overshoot and small actuator force. Based on the stability lobes diagram, the presented controller increases the limit of stability and attenuates the chatter in turning process. Although the effect of the controller on a system's vibration depends on the actuator's saturation force, using an actuator with a relatively low saturation force leads to a satisfactory performance. An electronic circuit for the force actuator that implements the proposed controller is a future phase of the current research.
{"title":"A PID controller design to suppress chatter vibrations in the turning process & studying its effect in nonlinear delayed process","authors":"Mohsen Khajoee, H. Moradi","doi":"10.1109/MOCAST52088.2021.9493341","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493341","url":null,"abstract":"High-quality, high-production-rate machining operations are significantly hindered by the regenerative chatter. Therefore, chatter suppression is of great significance; and active control is one of the best ways to curb it. In this paper, the orthogonal turning process is modeled as a single-degree-of-freedom system that includes the effect of tool wear; and described through a delay differential equation (DDE). Based on the model, stability lobes diagrams are obtained by the trial and error. The actuator force is the input for the control system and the tool vibration is the output. A classical PID controller is designed to improve the stability of the process and curb the self-excited vibrations. The controller is then tuned in order to achieve the vibration's suppression, short settling time, low overshoot and small actuator force. Based on the stability lobes diagram, the presented controller increases the limit of stability and attenuates the chatter in turning process. Although the effect of the controller on a system's vibration depends on the actuator's saturation force, using an actuator with a relatively low saturation force leads to a satisfactory performance. An electronic circuit for the force actuator that implements the proposed controller is a future phase of the current research.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116198777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493365
I. Kouretas, Vassilis Paliouras
In this paper a parallel neural network architecture is proposed targeting efficient hardware implementation on low-resource devices. Following the introduction of the proposed technique, the novel concept is applied on two basic function approximation examples namely cos(x) and sin(x). Quantitative results are offered and discussed in terms of accuracy and hardware complexity. It is shown that the proposed technique achieves promising results when considering low-power and high-performance hardware implementations targeted to edge devices.
{"title":"Hardware Aspects of Parallel Neural Network Implementation","authors":"I. Kouretas, Vassilis Paliouras","doi":"10.1109/MOCAST52088.2021.9493365","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493365","url":null,"abstract":"In this paper a parallel neural network architecture is proposed targeting efficient hardware implementation on low-resource devices. Following the introduction of the proposed technique, the novel concept is applied on two basic function approximation examples namely cos(x) and sin(x). Quantitative results are offered and discussed in terms of accuracy and hardware complexity. It is shown that the proposed technique achieves promising results when considering low-power and high-performance hardware implementations targeted to edge devices.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116202756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493420
Nikolaos Baras, Dimitris Ziouzios, M. Dasygenis, C. Tsanaktsidis
The rate of urban waste production is constantly increasing as a result of the Earth’s rapid population growth and modern lifestyle. Organic and non-organic recyclable waste, which accounts for a significant portion of urban solid waste, has raised environmental concerns. The best way to create a healthy ecosystem is to recycle. According to estimates from the US Environmental Protection Agency, approximately 75% of total waste can be recycled, but we only recycle 25% of it. The majority of the non-recyclable waste is dumped on the ground or incinerated. We can save energy and create a valuable by-product that can be used as a locally generated fertilizer through recycling organic materials through the compost process, whereas non organic materials can be used as industrial materials. Under this study, we suggest a solution: a low-cost and efficient Smart Recycle Bin that aides the recycling process by using modern technologies such as environmental sensors and the LoRaWAN protocol. A centralized Information System gathers data from smart bins that can be placed virtually anywhere and can help with waste collection. The Information System will generate real-time routes for waste collection vehicles. We ran several tests with our smart bin prototype, assessed its performance, and came to the conclusion that it is a viable solution.
{"title":"A modern cloud based recycling system for smart cities","authors":"Nikolaos Baras, Dimitris Ziouzios, M. Dasygenis, C. Tsanaktsidis","doi":"10.1109/MOCAST52088.2021.9493420","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493420","url":null,"abstract":"The rate of urban waste production is constantly increasing as a result of the Earth’s rapid population growth and modern lifestyle. Organic and non-organic recyclable waste, which accounts for a significant portion of urban solid waste, has raised environmental concerns. The best way to create a healthy ecosystem is to recycle. According to estimates from the US Environmental Protection Agency, approximately 75% of total waste can be recycled, but we only recycle 25% of it. The majority of the non-recyclable waste is dumped on the ground or incinerated. We can save energy and create a valuable by-product that can be used as a locally generated fertilizer through recycling organic materials through the compost process, whereas non organic materials can be used as industrial materials. Under this study, we suggest a solution: a low-cost and efficient Smart Recycle Bin that aides the recycling process by using modern technologies such as environmental sensors and the LoRaWAN protocol. A centralized Information System gathers data from smart bins that can be placed virtually anywhere and can help with waste collection. The Information System will generate real-time routes for waste collection vehicles. We ran several tests with our smart bin prototype, assessed its performance, and came to the conclusion that it is a viable solution.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493357
Konstantinos-Filippos Kollias, Christine K. Syriopoulou-Delli, P. Sarigiannidis, G. Fragulis
According to Diagnostic and Statistical Manual of Mental Disorders, Autism spectrum disorder (ASD) is a developmental disorder characterised by reduced social interaction and communication, and by restricted, repetitive, and stereotyped behaviour. An important characteristic of autism, referred in several diagnostic tests, is a deficit in eye gaze. The objective of this study is to review the literature concerning machine learning and eye-tracking in ASD studies conducted since 2015. Our search on PubMed identified 18 studies which used various eye-tracking instruments, applied machine learning in different ways, distributed several tasks and had a wide range of sample sizes, age groups and functional skills of participants. There were also studies that utilised other instruments, such as Electroencephalography (EEG) and movement measures. Taken together, the results of these studies show that the combination of machine learning, and eye-tracking technology can contribute to autism identification characteristics by detecting the visual atypicalities of ASD people. In conclusion, machine learning and eye-tracking ASD studies could be considered a promising tool in autism research and future studies could involve other technological approaches, such as Internet of Things (IoT), as well.
{"title":"The contribution of Machine Learning and Eye-tracking technology in Autism Spectrum Disorder research: A Review Study","authors":"Konstantinos-Filippos Kollias, Christine K. Syriopoulou-Delli, P. Sarigiannidis, G. Fragulis","doi":"10.1109/MOCAST52088.2021.9493357","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493357","url":null,"abstract":"According to Diagnostic and Statistical Manual of Mental Disorders, Autism spectrum disorder (ASD) is a developmental disorder characterised by reduced social interaction and communication, and by restricted, repetitive, and stereotyped behaviour. An important characteristic of autism, referred in several diagnostic tests, is a deficit in eye gaze. The objective of this study is to review the literature concerning machine learning and eye-tracking in ASD studies conducted since 2015. Our search on PubMed identified 18 studies which used various eye-tracking instruments, applied machine learning in different ways, distributed several tasks and had a wide range of sample sizes, age groups and functional skills of participants. There were also studies that utilised other instruments, such as Electroencephalography (EEG) and movement measures. Taken together, the results of these studies show that the combination of machine learning, and eye-tracking technology can contribute to autism identification characteristics by detecting the visual atypicalities of ASD people. In conclusion, machine learning and eye-tracking ASD studies could be considered a promising tool in autism research and future studies could involve other technological approaches, such as Internet of Things (IoT), as well.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128708731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493380
R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev
This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.
{"title":"FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards","authors":"R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev","doi":"10.1109/MOCAST52088.2021.9493380","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493380","url":null,"abstract":"This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125089203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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