Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493380
R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev
This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.
{"title":"FPGA Implementation of LDPC Decoder Architecture for Wireless Communication Standards","authors":"R. Goriushkin, P. Nikishkin, E. Likhobabin, V. Vityazev","doi":"10.1109/MOCAST52088.2021.9493380","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493380","url":null,"abstract":"This paper presents a decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. The design is parameterized and can be easily rebuilt to support various LDPC Parity-Check matrices taken from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards. New techniques such as parallelization of the decoding architecture cores are proposed. These cores calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update posterior probabilities (APPs). The parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Our decoder is implemented on FPGAs of the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900). The throughput of up to 1,2 GBit/s and the operation frequency of up to 240 MHz have been achieved.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125089203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493368
Anastasios Vlachos, Nikos Temenos, P. Sotiriadis
A soft-filtering processing architecture based on Sigma-Delta Modulation and Stochastic Computing is proposed. It converts a high-resolution signal using a first order digital Sigma-Delta Modulator into a single-bit one and then exploits Stochastic Computing’s encoding to perform area-efficient multiplications. The Sigma-Delta Modulator allows for the input signal to be oversampled at a much higher frequency rate, offering improved performance in terms of SNR, which is not possible with standard Stochastic Computing filter realizations. Spectral simulations results demonstrate the proper signal quantization and operation of the filter, including the filter’s roll-off behavior. FPGA synthesis results of the proposed architecture, illustrate its area advantages in comparison to conventional binary filtering.
{"title":"Exploring the Effectiveness of Sigma-Delta Modulators in Stochastic Computing-Based FIR Filtering","authors":"Anastasios Vlachos, Nikos Temenos, P. Sotiriadis","doi":"10.1109/MOCAST52088.2021.9493368","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493368","url":null,"abstract":"A soft-filtering processing architecture based on Sigma-Delta Modulation and Stochastic Computing is proposed. It converts a high-resolution signal using a first order digital Sigma-Delta Modulator into a single-bit one and then exploits Stochastic Computing’s encoding to perform area-efficient multiplications. The Sigma-Delta Modulator allows for the input signal to be oversampled at a much higher frequency rate, offering improved performance in terms of SNR, which is not possible with standard Stochastic Computing filter realizations. Spectral simulations results demonstrate the proper signal quantization and operation of the filter, including the filter’s roll-off behavior. FPGA synthesis results of the proposed architecture, illustrate its area advantages in comparison to conventional binary filtering.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126020368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493369
Stylianos Voutsinas, D. Karolidis, I. Voyiatzis, M. Samarakou
During the last decade, exponential growth in energy production by Photovoltaic systems (PVS) has been observed. Although very promising concerning energy production, PVS are often prone to faults that arise either due to environmental conditions or to the quality of materials used for their manufacturing and handling during installation. If these faults are left untreated, a risk arises both to the operation of the system itself (risk of destruction) and to its very ability to produce energy reliably. This paper discusses methods for fault detection and identification on the DC side of the photovoltaic systems. The methods are studied for their ability to identify various fault types as well as their complexity and limitations.
{"title":"Photovoltaic Faults: A comparative overview of detection and identification methods","authors":"Stylianos Voutsinas, D. Karolidis, I. Voyiatzis, M. Samarakou","doi":"10.1109/MOCAST52088.2021.9493369","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493369","url":null,"abstract":"During the last decade, exponential growth in energy production by Photovoltaic systems (PVS) has been observed. Although very promising concerning energy production, PVS are often prone to faults that arise either due to environmental conditions or to the quality of materials used for their manufacturing and handling during installation. If these faults are left untreated, a risk arises both to the operation of the system itself (risk of destruction) and to its very ability to produce energy reliably. This paper discusses methods for fault detection and identification on the DC side of the photovoltaic systems. The methods are studied for their ability to identify various fault types as well as their complexity and limitations.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127106578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493361
Dimitrios Danopoulos, Konstantinos Anagnostopoulos, C. Kachris, D. Soudris
Accurate and efficient Machine Learning algorithms are of vital importance to many problems, especially on classification or clustering tasks. In recent years, a new class of Machine Learning has been introduced called Generative Adversarial Network (GAN) which relies on two neural networks: a generative network (generator) and a discriminative network (discriminator). These two networks compete with each other with aim to generate new data such as images. For example, a GAN is capable of reconstructing an image which is filled by noise or has some regions damaged. Image reconstruction has found its application in the field of computer vision, augmented reality, human computer interaction and animation as well as medical imaging. However, this type of algorithm requires many MAC (multiply-accumulate) operations and high power consumption to operate. In this work, we implement an Image reconstruction algorithm with GANs, specifically as a case study we train a model capable of restoring clothing images based on the fashion-MNIST dataset. Additionally, we implement and accelerate it on a Xilinx FPGA SoC which as platforms are proven to address these kind of problems very efficiently in terms of performance and power. The design also achieves better performance and power efficiency from CPU and GPU with 0.013 ms average reconstruction time per image and 43 db PSNR on the FPGA quantized configuration.
{"title":"FPGA Acceleration of Generative Adversarial Networks for Image Reconstruction","authors":"Dimitrios Danopoulos, Konstantinos Anagnostopoulos, C. Kachris, D. Soudris","doi":"10.1109/MOCAST52088.2021.9493361","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493361","url":null,"abstract":"Accurate and efficient Machine Learning algorithms are of vital importance to many problems, especially on classification or clustering tasks. In recent years, a new class of Machine Learning has been introduced called Generative Adversarial Network (GAN) which relies on two neural networks: a generative network (generator) and a discriminative network (discriminator). These two networks compete with each other with aim to generate new data such as images. For example, a GAN is capable of reconstructing an image which is filled by noise or has some regions damaged. Image reconstruction has found its application in the field of computer vision, augmented reality, human computer interaction and animation as well as medical imaging. However, this type of algorithm requires many MAC (multiply-accumulate) operations and high power consumption to operate. In this work, we implement an Image reconstruction algorithm with GANs, specifically as a case study we train a model capable of restoring clothing images based on the fashion-MNIST dataset. Additionally, we implement and accelerate it on a Xilinx FPGA SoC which as platforms are proven to address these kind of problems very efficiently in terms of performance and power. The design also achieves better performance and power efficiency from CPU and GPU with 0.013 ms average reconstruction time per image and 43 db PSNR on the FPGA quantized configuration.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130691877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493399
Alaa AbdAlRahman, A. M. Abdelaty, A. Soltan, A. Radwan
Fractional calculus increases the flexibility of a system by studying the unexplored space between two integers. However, fractional calculus’s main challenge is its implementation due to its memory dependency, which appears in the amplitudes of the w coefficients in Grunwald–Letnikov(GL) definition. A modified GL approximation is proposed to control this dependency and decrease the error. The suggested approximation is based on the difference of the w binomial coefficients, which makes the new coefficients amplitudes decay faster. Three methods are discussed and compared for implementing the standard and the proposed GL approximation. The modified approximation shows an improvement, especially in the integration region of − 1 < α < −0.5. For example, the modified approximation results in an average absolute error of (0.1987) while the standard approximation results in an average absolute error of (0.8636) for sin(t) signal at α = −0.95, step size (h) of 0.01, window size of 64, and number of samples of 6283.
{"title":"An Improved Approximation of Grunwald-Letnikov Fractional Integral","authors":"Alaa AbdAlRahman, A. M. Abdelaty, A. Soltan, A. Radwan","doi":"10.1109/MOCAST52088.2021.9493399","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493399","url":null,"abstract":"Fractional calculus increases the flexibility of a system by studying the unexplored space between two integers. However, fractional calculus’s main challenge is its implementation due to its memory dependency, which appears in the amplitudes of the w coefficients in Grunwald–Letnikov(GL) definition. A modified GL approximation is proposed to control this dependency and decrease the error. The suggested approximation is based on the difference of the w binomial coefficients, which makes the new coefficients amplitudes decay faster. Three methods are discussed and compared for implementing the standard and the proposed GL approximation. The modified approximation shows an improvement, especially in the integration region of − 1 < α < −0.5. For example, the modified approximation results in an average absolute error of (0.1987) while the standard approximation results in an average absolute error of (0.8636) for sin(t) signal at α = −0.95, step size (h) of 0.01, window size of 64, and number of samples of 6283.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134268702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493357
Konstantinos-Filippos Kollias, Christine K. Syriopoulou-Delli, P. Sarigiannidis, G. Fragulis
According to Diagnostic and Statistical Manual of Mental Disorders, Autism spectrum disorder (ASD) is a developmental disorder characterised by reduced social interaction and communication, and by restricted, repetitive, and stereotyped behaviour. An important characteristic of autism, referred in several diagnostic tests, is a deficit in eye gaze. The objective of this study is to review the literature concerning machine learning and eye-tracking in ASD studies conducted since 2015. Our search on PubMed identified 18 studies which used various eye-tracking instruments, applied machine learning in different ways, distributed several tasks and had a wide range of sample sizes, age groups and functional skills of participants. There were also studies that utilised other instruments, such as Electroencephalography (EEG) and movement measures. Taken together, the results of these studies show that the combination of machine learning, and eye-tracking technology can contribute to autism identification characteristics by detecting the visual atypicalities of ASD people. In conclusion, machine learning and eye-tracking ASD studies could be considered a promising tool in autism research and future studies could involve other technological approaches, such as Internet of Things (IoT), as well.
{"title":"The contribution of Machine Learning and Eye-tracking technology in Autism Spectrum Disorder research: A Review Study","authors":"Konstantinos-Filippos Kollias, Christine K. Syriopoulou-Delli, P. Sarigiannidis, G. Fragulis","doi":"10.1109/MOCAST52088.2021.9493357","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493357","url":null,"abstract":"According to Diagnostic and Statistical Manual of Mental Disorders, Autism spectrum disorder (ASD) is a developmental disorder characterised by reduced social interaction and communication, and by restricted, repetitive, and stereotyped behaviour. An important characteristic of autism, referred in several diagnostic tests, is a deficit in eye gaze. The objective of this study is to review the literature concerning machine learning and eye-tracking in ASD studies conducted since 2015. Our search on PubMed identified 18 studies which used various eye-tracking instruments, applied machine learning in different ways, distributed several tasks and had a wide range of sample sizes, age groups and functional skills of participants. There were also studies that utilised other instruments, such as Electroencephalography (EEG) and movement measures. Taken together, the results of these studies show that the combination of machine learning, and eye-tracking technology can contribute to autism identification characteristics by detecting the visual atypicalities of ASD people. In conclusion, machine learning and eye-tracking ASD studies could be considered a promising tool in autism research and future studies could involve other technological approaches, such as Internet of Things (IoT), as well.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128708731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493346
Nick Rigogiannis, A. Boubaris, Zoi Agorastou, N. Papanikolaou, S. Siskos, E. Koutroulis
This paper focuses on the design of a low-voltage power converter for an on-chip PV cell-level inverter. Various topologies are discussed for the DC/DC stage, whereas the ZVS quasi-resonant boost and the synchronous boost are considered the most appropriate for this application. Both the aforementioned topologies are modeled and evaluated in terms of efficiency, by the aid of PSpice simulations. Due to requirements and limitations of the available 0.18 μm CMOS process technology, the synchronous boost is finally chosen as the most appropriate solution. As for the DC/AC stage, the H-bridge inverter configuration is selected, as a simple, compact and cost-effective solution. A prototype converter is designed and constructed with discrete components, so as to validate the functionality and performance of the proposed system. Finally, experimental results are presented, indicating the high efficiency that can be achieved.
{"title":"Experimental Study of a Low-Voltage PV Cell-Level DC/AC Converter","authors":"Nick Rigogiannis, A. Boubaris, Zoi Agorastou, N. Papanikolaou, S. Siskos, E. Koutroulis","doi":"10.1109/MOCAST52088.2021.9493346","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493346","url":null,"abstract":"This paper focuses on the design of a low-voltage power converter for an on-chip PV cell-level inverter. Various topologies are discussed for the DC/DC stage, whereas the ZVS quasi-resonant boost and the synchronous boost are considered the most appropriate for this application. Both the aforementioned topologies are modeled and evaluated in terms of efficiency, by the aid of PSpice simulations. Due to requirements and limitations of the available 0.18 μm CMOS process technology, the synchronous boost is finally chosen as the most appropriate solution. As for the DC/AC stage, the H-bridge inverter configuration is selected, as a simple, compact and cost-effective solution. A prototype converter is designed and constructed with discrete components, so as to validate the functionality and performance of the proposed system. Finally, experimental results are presented, indicating the high efficiency that can be achieved.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493340
Christos C. Spandonidis, Giannopoulos Fotis, N. Galiatsatos, Reppas Dimitris, A. Petsa, D. Spyropoulos
Pipelines are one of the most common systems for storing and transporting petroleum products, both liquid and gaseous. Despite the durable structures, leakages can occur for many reasons, causing environmental disasters, energy waste, and, in some cases, human losses. The object of the ESTHISIS project is the development of a low-cost and low-energy wireless sensor system for the immediate detection of leaks in metallic piping systems for the transport of liquid and gaseous petroleum products in a noisy industrial environment. The method to be followed will be based on processing the changes monitored in the spectrum of vibration signals appearing in the pipeline walls due to a leakage effect and will aim at minimal interference in the piping system. It is intended to use low frequencies to detect and characterize leakage to increase the range of sensors and thus to reduce cost. In the current work, the smart sensor system developed for signal acquisition and data analysis is described. The work focuses on the hardware of the system and crucial details that enable the time synchronization of the system. Discussion on the main challenges faced as well as results of integration and lab-scale tests have been also included.
{"title":"Autonomous low-cost Wireless Sensor platform for Leakage Detection in Oil and Gas Pipes","authors":"Christos C. Spandonidis, Giannopoulos Fotis, N. Galiatsatos, Reppas Dimitris, A. Petsa, D. Spyropoulos","doi":"10.1109/MOCAST52088.2021.9493340","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493340","url":null,"abstract":"Pipelines are one of the most common systems for storing and transporting petroleum products, both liquid and gaseous. Despite the durable structures, leakages can occur for many reasons, causing environmental disasters, energy waste, and, in some cases, human losses. The object of the ESTHISIS project is the development of a low-cost and low-energy wireless sensor system for the immediate detection of leaks in metallic piping systems for the transport of liquid and gaseous petroleum products in a noisy industrial environment. The method to be followed will be based on processing the changes monitored in the spectrum of vibration signals appearing in the pipeline walls due to a leakage effect and will aim at minimal interference in the piping system. It is intended to use low frequencies to detect and characterize leakage to increase the range of sensors and thus to reduce cost. In the current work, the smart sensor system developed for signal acquisition and data analysis is described. The work focuses on the hardware of the system and crucial details that enable the time synchronization of the system. Discussion on the main challenges faced as well as results of integration and lab-scale tests have been also included.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129899230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493376
G. Georgiou, G. Theodoridis
In this work, the impacts of the loop unrolling and pipeline in the FPGA implementation of the Simon and RoadRunneR lightweight ciphers is studied. To achieve this, two basic architectures were used. In the first architecture only loop unrolling is applied while, the second one supports both the loop unrolling and pipeline. Using these architectures, three designs versions were developed, for each algorithm. The first and second ones concern individually the encryption and decryption procedures while, the third version is a hybrid one that supports both encryption and decryption. The metrics that were studied the area, frequency, throughput, throughput/area and energy consumption. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.
{"title":"Studying the impacts of loop unrolling and pipeline in the FPGA design of the Simon and RoadRunneR lightweght ciphers","authors":"G. Georgiou, G. Theodoridis","doi":"10.1109/MOCAST52088.2021.9493376","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493376","url":null,"abstract":"In this work, the impacts of the loop unrolling and pipeline in the FPGA implementation of the Simon and RoadRunneR lightweight ciphers is studied. To achieve this, two basic architectures were used. In the first architecture only loop unrolling is applied while, the second one supports both the loop unrolling and pipeline. Using these architectures, three designs versions were developed, for each algorithm. The first and second ones concern individually the encryption and decryption procedures while, the third version is a hybrid one that supports both encryption and decryption. The metrics that were studied the area, frequency, throughput, throughput/area and energy consumption. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128834833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493421
Vasileios Leon, I. Stratakos, Giorgos Armeniakos, G. Lentaris, D. Soudris
Modern mobile communication systems utilize increased bandwidth to provide advanced network performance and connectivity, all while their most computationally-intensive functions must be accelerated within the limited power envelope of embedded devices. In this paper, we improve the circuit complexity and throughput of a key digital function in the baseband processing chain, namely the high-order QAM demodulation. In particular, we explore 4 different demodulation algorithms, we employ both floating- and fixed-point arithmetic, and we insert approximations in the arithmetic units. In terms of accuracy of our most prominent implementations, i.e., for 64-QAM, our designs deliver BER values ranging from 10−1 to 10−4 for SNR 0−14dB. In terms of FPGA resources on Xilinx ZCU106, these 64-QAM designs achieve up to 98% reduction in LUT utilization compared to the accurate floating-point model of the same algorithm, and up to 122% increase in operating frequency. When targeting demodulation with high levels of accuracy, i.e., almost zero BER degradation with respect to that of the original floating-point model, the prevailing solution is the Approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency to sustain a throughput of 323 Msamples/second.
{"title":"ApproxQAM: High-Order QAM Demodulation Circuits with Approximate Arithmetic","authors":"Vasileios Leon, I. Stratakos, Giorgos Armeniakos, G. Lentaris, D. Soudris","doi":"10.1109/MOCAST52088.2021.9493421","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493421","url":null,"abstract":"Modern mobile communication systems utilize increased bandwidth to provide advanced network performance and connectivity, all while their most computationally-intensive functions must be accelerated within the limited power envelope of embedded devices. In this paper, we improve the circuit complexity and throughput of a key digital function in the baseband processing chain, namely the high-order QAM demodulation. In particular, we explore 4 different demodulation algorithms, we employ both floating- and fixed-point arithmetic, and we insert approximations in the arithmetic units. In terms of accuracy of our most prominent implementations, i.e., for 64-QAM, our designs deliver BER values ranging from 10−1 to 10−4 for SNR 0−14dB. In terms of FPGA resources on Xilinx ZCU106, these 64-QAM designs achieve up to 98% reduction in LUT utilization compared to the accurate floating-point model of the same algorithm, and up to 122% increase in operating frequency. When targeting demodulation with high levels of accuracy, i.e., almost zero BER degradation with respect to that of the original floating-point model, the prevailing solution is the Approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency to sustain a throughput of 323 Msamples/second.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117332439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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