Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493352
Konstantinos G. Tsiknas, Paraskevas I. Aidinidis, K. Zoiros
Data center networks (DCNs) hold a key role in information industry as the infrastructure for hosting cloud data services and related applications. The increasing number of customers using cloud services sets, however, new challenges for the efficient management of the DCN traffic handled by the transport protocols. TCP is adapted as the main transport control protocol in DCNs, but the standard congestion control algorithm it employs has been found to be very inefficient in providing a fair sharing of the available channel capacity among the competing DCN traffic flows. DCTCP and CUBIC are two promising TCP variants designed to resolve the fairness issues identified in these environments. In this paper, we evaluate the fairness properties of these two TCP variants in comparison to the conventional TCP Reno with the use of network simulator 3 (ns-3) in realistic DCN scenarios. Our results show that DTCP improves substantially the fairness properties of TCP, but it requires more buffer space for large number of flows; it also requires the intermediate switches to be Explicit Congestion Notification (ECN)-aware. CUBIC achieves very low queue occupancies, but it demonstrates low fairness when a large and a small set of flows compete at the output port of a bottleneck switch (TCP Outcast issue).
{"title":"On the Fairness of DCTCP and CUBIC in Cloud Data Center Networks","authors":"Konstantinos G. Tsiknas, Paraskevas I. Aidinidis, K. Zoiros","doi":"10.1109/MOCAST52088.2021.9493352","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493352","url":null,"abstract":"Data center networks (DCNs) hold a key role in information industry as the infrastructure for hosting cloud data services and related applications. The increasing number of customers using cloud services sets, however, new challenges for the efficient management of the DCN traffic handled by the transport protocols. TCP is adapted as the main transport control protocol in DCNs, but the standard congestion control algorithm it employs has been found to be very inefficient in providing a fair sharing of the available channel capacity among the competing DCN traffic flows. DCTCP and CUBIC are two promising TCP variants designed to resolve the fairness issues identified in these environments. In this paper, we evaluate the fairness properties of these two TCP variants in comparison to the conventional TCP Reno with the use of network simulator 3 (ns-3) in realistic DCN scenarios. Our results show that DTCP improves substantially the fairness properties of TCP, but it requires more buffer space for large number of flows; it also requires the intermediate switches to be Explicit Congestion Notification (ECN)-aware. CUBIC achieves very low queue occupancies, but it demonstrates low fairness when a large and a small set of flows compete at the output port of a bottleneck switch (TCP Outcast issue).","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126135381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493376
G. Georgiou, G. Theodoridis
In this work, the impacts of the loop unrolling and pipeline in the FPGA implementation of the Simon and RoadRunneR lightweight ciphers is studied. To achieve this, two basic architectures were used. In the first architecture only loop unrolling is applied while, the second one supports both the loop unrolling and pipeline. Using these architectures, three designs versions were developed, for each algorithm. The first and second ones concern individually the encryption and decryption procedures while, the third version is a hybrid one that supports both encryption and decryption. The metrics that were studied the area, frequency, throughput, throughput/area and energy consumption. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.
{"title":"Studying the impacts of loop unrolling and pipeline in the FPGA design of the Simon and RoadRunneR lightweght ciphers","authors":"G. Georgiou, G. Theodoridis","doi":"10.1109/MOCAST52088.2021.9493376","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493376","url":null,"abstract":"In this work, the impacts of the loop unrolling and pipeline in the FPGA implementation of the Simon and RoadRunneR lightweight ciphers is studied. To achieve this, two basic architectures were used. In the first architecture only loop unrolling is applied while, the second one supports both the loop unrolling and pipeline. Using these architectures, three designs versions were developed, for each algorithm. The first and second ones concern individually the encryption and decryption procedures while, the third version is a hybrid one that supports both encryption and decryption. The metrics that were studied the area, frequency, throughput, throughput/area and energy consumption. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128834833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493386
L. Iliadis, T. Kaifas
A Darknet is an overlay network within the Internet, and packets’ traffic originating from it is usually termed as suspicious. In this paper common machine learning classification algorithms are employed to identify Darknet traffic. A ROC analysis along with a feature importance analysis for the best classifier was performed, to provide a better visualisation of the results. The experiments were conducted in the new dataset CIC-Darknet2020 and the classifiers were trained to both binary and multiclass classification. In the first classification task, there were two classes: "Benign" and "Darknet", whereas in the second there were four classes: "Tor", "Non Tor", "VPN" and "Non VPN". An average prediction accuracy of over 98% was achieved with the implementation of Random Forest algorithm for both classification tasks. This is the first work, to the best of our knowledge providing a comprehensive performance evaluation of machine learning classifiers employed for Darknet traffic classification in the new dataset CIC-Darknet2020.
{"title":"Darknet Traffic Classification using Machine Learning Techniques","authors":"L. Iliadis, T. Kaifas","doi":"10.1109/MOCAST52088.2021.9493386","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493386","url":null,"abstract":"A Darknet is an overlay network within the Internet, and packets’ traffic originating from it is usually termed as suspicious. In this paper common machine learning classification algorithms are employed to identify Darknet traffic. A ROC analysis along with a feature importance analysis for the best classifier was performed, to provide a better visualisation of the results. The experiments were conducted in the new dataset CIC-Darknet2020 and the classifiers were trained to both binary and multiclass classification. In the first classification task, there were two classes: \"Benign\" and \"Darknet\", whereas in the second there were four classes: \"Tor\", \"Non Tor\", \"VPN\" and \"Non VPN\". An average prediction accuracy of over 98% was achieved with the implementation of Random Forest algorithm for both classification tasks. This is the first work, to the best of our knowledge providing a comprehensive performance evaluation of machine learning classifiers employed for Darknet traffic classification in the new dataset CIC-Darknet2020.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121904344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493421
Vasileios Leon, I. Stratakos, Giorgos Armeniakos, G. Lentaris, D. Soudris
Modern mobile communication systems utilize increased bandwidth to provide advanced network performance and connectivity, all while their most computationally-intensive functions must be accelerated within the limited power envelope of embedded devices. In this paper, we improve the circuit complexity and throughput of a key digital function in the baseband processing chain, namely the high-order QAM demodulation. In particular, we explore 4 different demodulation algorithms, we employ both floating- and fixed-point arithmetic, and we insert approximations in the arithmetic units. In terms of accuracy of our most prominent implementations, i.e., for 64-QAM, our designs deliver BER values ranging from 10−1 to 10−4 for SNR 0−14dB. In terms of FPGA resources on Xilinx ZCU106, these 64-QAM designs achieve up to 98% reduction in LUT utilization compared to the accurate floating-point model of the same algorithm, and up to 122% increase in operating frequency. When targeting demodulation with high levels of accuracy, i.e., almost zero BER degradation with respect to that of the original floating-point model, the prevailing solution is the Approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency to sustain a throughput of 323 Msamples/second.
{"title":"ApproxQAM: High-Order QAM Demodulation Circuits with Approximate Arithmetic","authors":"Vasileios Leon, I. Stratakos, Giorgos Armeniakos, G. Lentaris, D. Soudris","doi":"10.1109/MOCAST52088.2021.9493421","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493421","url":null,"abstract":"Modern mobile communication systems utilize increased bandwidth to provide advanced network performance and connectivity, all while their most computationally-intensive functions must be accelerated within the limited power envelope of embedded devices. In this paper, we improve the circuit complexity and throughput of a key digital function in the baseband processing chain, namely the high-order QAM demodulation. In particular, we explore 4 different demodulation algorithms, we employ both floating- and fixed-point arithmetic, and we insert approximations in the arithmetic units. In terms of accuracy of our most prominent implementations, i.e., for 64-QAM, our designs deliver BER values ranging from 10−1 to 10−4 for SNR 0−14dB. In terms of FPGA resources on Xilinx ZCU106, these 64-QAM designs achieve up to 98% reduction in LUT utilization compared to the accurate floating-point model of the same algorithm, and up to 122% increase in operating frequency. When targeting demodulation with high levels of accuracy, i.e., almost zero BER degradation with respect to that of the original floating-point model, the prevailing solution is the Approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency to sustain a throughput of 323 Msamples/second.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117332439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493349
Georgios-Panagiotis Kousiopoulos, N. Karagiorgos, D. Kampelopoulos, V. Konstantakos, S. Nikolaidis
One of the most serious problems occurring in a pipeline network is the appearance of leaks. The process of detecting and localizing leaks in pipeline systems concerns a very extensive field of signal processing methods employed for this matter. In this paper a leak localization method combining the segmentation of acoustic leak signals, both in the time and in the frequency domain, with a statistical algorithm needed for dealing with the non-deterministic (stochastic) nature of these signals is proposed. This algorithm involves the use of cross-correlation techniques along with the grouping of the time-delay data in a histogram and selecting the bin with the largest number of elements as the one that provides the correct answer. The successful detection of the leak position requires the knowledge of the acoustic wave velocity in the pipe. In the present paper the calculation of the acoustic velocity is performed by the use of a PCB hammer to cover more realistic situations. The proposed leak localization method is tested experimentally in a laboratory setup containing a 67-meter steel pipeline and the results show that the presented method can localize leaks efficiently, since the average localization error is around 3%.
{"title":"Acoustic leak localization method based on signal segmentation and statistical analysis","authors":"Georgios-Panagiotis Kousiopoulos, N. Karagiorgos, D. Kampelopoulos, V. Konstantakos, S. Nikolaidis","doi":"10.1109/MOCAST52088.2021.9493349","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493349","url":null,"abstract":"One of the most serious problems occurring in a pipeline network is the appearance of leaks. The process of detecting and localizing leaks in pipeline systems concerns a very extensive field of signal processing methods employed for this matter. In this paper a leak localization method combining the segmentation of acoustic leak signals, both in the time and in the frequency domain, with a statistical algorithm needed for dealing with the non-deterministic (stochastic) nature of these signals is proposed. This algorithm involves the use of cross-correlation techniques along with the grouping of the time-delay data in a histogram and selecting the bin with the largest number of elements as the one that provides the correct answer. The successful detection of the leak position requires the knowledge of the acoustic wave velocity in the pipe. In the present paper the calculation of the acoustic velocity is performed by the use of a PCB hammer to cover more realistic situations. The proposed leak localization method is tested experimentally in a laboratory setup containing a 67-meter steel pipeline and the results show that the presented method can localize leaks efficiently, since the average localization error is around 3%.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124409573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493384
V. Mladenov, S. Kirilov
In this article an enhanced and simplified alteration of a memristor model based on tantalum oxide is proposed. Its application in hybrid memory crossbars is presented. The suggested model is founded on the classical Hewlett Packard Ta2O5 memristor model including several main refinements – incorporation of a simple window function, enhancement of its efficiency applying rationalized expression for the current-voltage relation and by substitution of the Heaviside function with continuous and smooth logistic function. The memristor model’s parameters are obtained by collation to tentative current-voltage characteristics and applying procedure for parameters estimation. A LTSpice library model is generated in agreement to the considered memristor model. The modified model of tantalum oxide memristor is tested in a hybrid memory crossbar. After comparison to several basic models the major advantages of the suggested memristor model are demonstrated – better performance, higher speed of operation, improved adjustment process and a sound switching representation.
{"title":"A Simplified Model of Tantalum Oxide Based Memristor and Application in Memory Crossbars","authors":"V. Mladenov, S. Kirilov","doi":"10.1109/MOCAST52088.2021.9493384","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493384","url":null,"abstract":"In this article an enhanced and simplified alteration of a memristor model based on tantalum oxide is proposed. Its application in hybrid memory crossbars is presented. The suggested model is founded on the classical Hewlett Packard Ta2O5 memristor model including several main refinements – incorporation of a simple window function, enhancement of its efficiency applying rationalized expression for the current-voltage relation and by substitution of the Heaviside function with continuous and smooth logistic function. The memristor model’s parameters are obtained by collation to tentative current-voltage characteristics and applying procedure for parameters estimation. A LTSpice library model is generated in agreement to the considered memristor model. The modified model of tantalum oxide memristor is tested in a hybrid memory crossbar. After comparison to several basic models the major advantages of the suggested memristor model are demonstrated – better performance, higher speed of operation, improved adjustment process and a sound switching representation.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493387
K. Tatas, Ahmad Al-Zoubi, A. Antoniou, D. Zolotareva
This paper presents the design, and implementation of an intelligent, low-cost IoT-based control and monitoring system for hydroponics greenhouses. The system is based on three types of sensor nodes: The main (master) node is responsible for controlling the pump, monitoring the quality of the water in the greenhouse and aggregating and transmitting the data from the slave nodes. Environment sensing slave nodes that monitor the ambient conditions in the greenhouse and transmit the data to the main node. Security nodes that monitor activity (movement in the area). The system monitors water quality and greenhouse temperature and humidity, ensuring that crops grow under the optimal conditions according to hydroponics guidelines. Remote monitoring for the greenhouse keepers is facilitated by monitoring these parameters by connecting to a website. The system is optimized for low power consumption in order to facilitate off-grid operation.
{"title":"iPONICS: IoT Monitoring and Control for Hydroponics","authors":"K. Tatas, Ahmad Al-Zoubi, A. Antoniou, D. Zolotareva","doi":"10.1109/MOCAST52088.2021.9493387","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493387","url":null,"abstract":"This paper presents the design, and implementation of an intelligent, low-cost IoT-based control and monitoring system for hydroponics greenhouses. The system is based on three types of sensor nodes: The main (master) node is responsible for controlling the pump, monitoring the quality of the water in the greenhouse and aggregating and transmitting the data from the slave nodes. Environment sensing slave nodes that monitor the ambient conditions in the greenhouse and transmit the data to the main node. Security nodes that monitor activity (movement in the area). The system monitors water quality and greenhouse temperature and humidity, ensuring that crops grow under the optimal conditions according to hydroponics guidelines. Remote monitoring for the greenhouse keepers is facilitated by monitoring these parameters by connecting to a website. The system is optimized for low power consumption in order to facilitate off-grid operation.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493406
M. Weißbrich, Javier Andrés Moreno-Medina, G. P. Vayá
An optimized instruction-set encoding can reduce the silicon area and power consumption of a processor architecture implementation. However, the design space of the input encoding problem is of factorial growth with the number of instruction patterns, so effective heuristics and an automated exploration tool are required to facilitate instruction-set encoding optimization in a processor design flow. This paper proposes a novel approach based on genetic algorithms to automatically optimize the instruction-set encoding of a specific processor architecture, reducing the silicon area and power consumption requirements for specific applications and hardware implementation technologies. Furthermore, an open-source tool, called VANAGA, is presented, which implements the proposed approach and allows flexible adaptation to custom instruction-set optimization scenarios. The tool flow is evaluated with an exemplary 65 nm standard cell ASIC implementation of a minimal controller architecture with 4-bit wide opcodes (NanoController). For different optimization scenarios, logic silicon area and total power consumption vary within a design space range of 6.3% and 0.46% for different instruction-set encodings, respectively.
{"title":"Using Genetic Algorithms to Optimize the Instruction-Set Encoding on Processor Cores","authors":"M. Weißbrich, Javier Andrés Moreno-Medina, G. P. Vayá","doi":"10.1109/MOCAST52088.2021.9493406","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493406","url":null,"abstract":"An optimized instruction-set encoding can reduce the silicon area and power consumption of a processor architecture implementation. However, the design space of the input encoding problem is of factorial growth with the number of instruction patterns, so effective heuristics and an automated exploration tool are required to facilitate instruction-set encoding optimization in a processor design flow. This paper proposes a novel approach based on genetic algorithms to automatically optimize the instruction-set encoding of a specific processor architecture, reducing the silicon area and power consumption requirements for specific applications and hardware implementation technologies. Furthermore, an open-source tool, called VANAGA, is presented, which implements the proposed approach and allows flexible adaptation to custom instruction-set optimization scenarios. The tool flow is evaluated with an exemplary 65 nm standard cell ASIC implementation of a minimal controller architecture with 4-bit wide opcodes (NanoController). For different optimization scenarios, logic silicon area and total power consumption vary within a design space range of 6.3% and 0.46% for different instruction-set encodings, respectively.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"19 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493374
G. Vergos, S. Sotiroudis, G. Athanasiadou, G. Tsoulos, S. Goudos
Machine Learning-based models gain increasingly momentum regarding the problem of path loss prediction. The work at hand deploys four machine learning algorithms (k Nearest Neighbors - kNN, Support Vector Regression - SVR, Random Forest - RF and AdaBoost), in order to simulate the radio coverage provided from a flying base station in the greek city of Tripolis. Their comparison shows that tree-based ensemble models (RF and AdaBoost) can be used as fast and reliable alternatives to the Ray Tracing technique.
{"title":"Comparing Machine Learning Methods for Air-to-Ground Path Loss Prediction","authors":"G. Vergos, S. Sotiroudis, G. Athanasiadou, G. Tsoulos, S. Goudos","doi":"10.1109/MOCAST52088.2021.9493374","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493374","url":null,"abstract":"Machine Learning-based models gain increasingly momentum regarding the problem of path loss prediction. The work at hand deploys four machine learning algorithms (k Nearest Neighbors - kNN, Support Vector Regression - SVR, Random Forest - RF and AdaBoost), in order to simulate the radio coverage provided from a flying base station in the greek city of Tripolis. Their comparison shows that tree-based ensemble models (RF and AdaBoost) can be used as fast and reliable alternatives to the Ray Tracing technique.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132403622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-05DOI: 10.1109/MOCAST52088.2021.9493343
S. Kapoulea, C. Psychalinos, A. Elwakil
A novel procedure for compact realization of complex, multiple-parameter impedance functions is introduced in this paper. The concept is based on the consideration of the whole impedance function and the approximation of its frequency characteristics through a suitable curve-fitting-based algorithm, instead of separately approximating the intermediate terms of the function. In this way, the total impedance is implemented by a topology which is based on one transfer function, offering the benefit of reduced complexity. The impedance function that describes the electrical properties of edible drinks can be considered as a characteristic example and, therefore, is used for the verification of the proposed concept. Different samples of drinks, red wine from Bairrada, semi-skimmed and organic semi- skimmed milk, are considered with the behavior of the proposed schemes being evaluated through simulation and experimental results.
{"title":"On the Realization of Power-Law Based Impedance Functions: Application to Edible Drinks","authors":"S. Kapoulea, C. Psychalinos, A. Elwakil","doi":"10.1109/MOCAST52088.2021.9493343","DOIUrl":"https://doi.org/10.1109/MOCAST52088.2021.9493343","url":null,"abstract":"A novel procedure for compact realization of complex, multiple-parameter impedance functions is introduced in this paper. The concept is based on the consideration of the whole impedance function and the approximation of its frequency characteristics through a suitable curve-fitting-based algorithm, instead of separately approximating the intermediate terms of the function. In this way, the total impedance is implemented by a topology which is based on one transfer function, offering the benefit of reduced complexity. The impedance function that describes the electrical properties of edible drinks can be considered as a characteristic example and, therefore, is used for the verification of the proposed concept. Different samples of drinks, red wine from Bairrada, semi-skimmed and organic semi- skimmed milk, are considered with the behavior of the proposed schemes being evaluated through simulation and experimental results.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125143211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：