Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303915
S. Kundu, Suchismita Roy, S. Mukherjee
The Rectilinear Steiner Minimum Tree (RSMT) problem claims the minimum length interconnection among a given set of terminals within the rectilinear plane, is one of the basic problems in physical design automation, specifically in routing. Recently, the problem has drawn great attention due to the need for extremely scalable algorithms able to handle nets with large number of terminals. In this paper, a SAT based methodology is introduced for obtaining RSMTs for different nets with varying net degrees. But, the SAT based solutions degrades with the increasing number of Boolean variables. To overcome this scalability issue, a divide-and-conquer approach is proposed here to minimize the solution space. A k-d tree based nearest neighbor (NN) search algorithm is developed here for reducing the solution space and improving the solution quality. Experimental results indicates that the proposed approach are able to obtain a better run time and possess lesser wirelength.
{"title":"K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction","authors":"S. Kundu, Suchismita Roy, S. Mukherjee","doi":"10.1109/ISED.2017.8303915","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303915","url":null,"abstract":"The Rectilinear Steiner Minimum Tree (RSMT) problem claims the minimum length interconnection among a given set of terminals within the rectilinear plane, is one of the basic problems in physical design automation, specifically in routing. Recently, the problem has drawn great attention due to the need for extremely scalable algorithms able to handle nets with large number of terminals. In this paper, a SAT based methodology is introduced for obtaining RSMTs for different nets with varying net degrees. But, the SAT based solutions degrades with the increasing number of Boolean variables. To overcome this scalability issue, a divide-and-conquer approach is proposed here to minimize the solution space. A k-d tree based nearest neighbor (NN) search algorithm is developed here for reducing the solution space and improving the solution quality. Experimental results indicates that the proposed approach are able to obtain a better run time and possess lesser wirelength.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133488810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303930
Sabyasachee Banerjee, S. Majumder, Abhishek Varma, D. K. Das
This paper presents a placement algorithm for designing 3D Integrated Circuits (ICs). Typical 2D ICs are unable to provide the high connection speeds that are offered by its 3D variants at a lower cost, consuming less power and space. The algorithm proposed in this paper demonstrates that assigning blocks to each layer in a compact fashion can achieve substantial savings in the total wirelength along with a reduction in the number of TSVs in most of the cases. On the whole, our method helps to reduce the total wirelength, as well as number of TSVs, while satisfying the area-constraints.
{"title":"A placement optimization technique for 3D IC","authors":"Sabyasachee Banerjee, S. Majumder, Abhishek Varma, D. K. Das","doi":"10.1109/ISED.2017.8303930","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303930","url":null,"abstract":"This paper presents a placement algorithm for designing 3D Integrated Circuits (ICs). Typical 2D ICs are unable to provide the high connection speeds that are offered by its 3D variants at a lower cost, consuming less power and space. The algorithm proposed in this paper demonstrates that assigning blocks to each layer in a compact fashion can achieve substantial savings in the total wirelength along with a reduction in the number of TSVs in most of the cases. On the whole, our method helps to reduce the total wirelength, as well as number of TSVs, while satisfying the area-constraints.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129471569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303934
Sourav Das, Mayuree Shegaonkar, M. Gupta, P. Acharjee
Changing load in power system network might lead to the voltage collapse in critical situations. By providing the proper power compensation with respect to these changes, the stability of such system can be increased. This paper aims at optimal placement of a unified power flow controller (UPFC) across a transmission line to overcome such stability problems by injecting active and reactive power into the system. For the analysis we have chosen standard IEEE test systems of 14-bus, 30-bus and 57-bus network. The PQ buses are loaded randomly to simulate the unpredictability and challenges of a power system transmission network. By using Mi-Power 9.0 software newton raphson load flow (NRLF) is applied to get power flow solution with and without UPFC. UPFC is placed at receiving-end bus, mid-point or sending-end bus of the transmission line connecting the lowest voltage magnitude bus and any adjacent bus. The analysis is done based on voltage profile improvement index (VPII), active and reactive power losses, UPFC installation cost and power generation cost. The effectiveness and benefits of UPFC allocation is proved by results.
{"title":"Optimal placement of UPFC across a transmission line considering techno-economic aspects with physical limitation","authors":"Sourav Das, Mayuree Shegaonkar, M. Gupta, P. Acharjee","doi":"10.1109/ISED.2017.8303934","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303934","url":null,"abstract":"Changing load in power system network might lead to the voltage collapse in critical situations. By providing the proper power compensation with respect to these changes, the stability of such system can be increased. This paper aims at optimal placement of a unified power flow controller (UPFC) across a transmission line to overcome such stability problems by injecting active and reactive power into the system. For the analysis we have chosen standard IEEE test systems of 14-bus, 30-bus and 57-bus network. The PQ buses are loaded randomly to simulate the unpredictability and challenges of a power system transmission network. By using Mi-Power 9.0 software newton raphson load flow (NRLF) is applied to get power flow solution with and without UPFC. UPFC is placed at receiving-end bus, mid-point or sending-end bus of the transmission line connecting the lowest voltage magnitude bus and any adjacent bus. The analysis is done based on voltage profile improvement index (VPII), active and reactive power losses, UPFC installation cost and power generation cost. The effectiveness and benefits of UPFC allocation is proved by results.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303905
W. Banerjee, Ming Liu
Resistive random access memory (RRAM) is one of the most promising emerging nonvolatile memory candidates for the future application as high-density memory and also for neuromorphic computing. Here, we show the fabrication of three-dimensional (3D) emerging RRAM devices based on the TiOx/Al2O3 bilayer design. The devices are showing good resistive switching performances after going through the initial forming process. All devices of the 3D stack are able to execute symmetrical switching behavior. Moreover, the devices are showing continuous synaptic characteristics based on the pulse dependent measurements. All of the observed phenomena are showing the possibility of using the TiOx/Al2O3 bilayer RRAM devices for the high-density and neuromorphic applications.
{"title":"Three-dimensional emerging nonvolatile memory for the high-density and neuromorphic applications","authors":"W. Banerjee, Ming Liu","doi":"10.1109/ISED.2017.8303905","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303905","url":null,"abstract":"Resistive random access memory (RRAM) is one of the most promising emerging nonvolatile memory candidates for the future application as high-density memory and also for neuromorphic computing. Here, we show the fabrication of three-dimensional (3D) emerging RRAM devices based on the TiOx/Al2O3 bilayer design. The devices are showing good resistive switching performances after going through the initial forming process. All devices of the 3D stack are able to execute symmetrical switching behavior. Moreover, the devices are showing continuous synaptic characteristics based on the pulse dependent measurements. All of the observed phenomena are showing the possibility of using the TiOx/Al2O3 bilayer RRAM devices for the high-density and neuromorphic applications.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303949
Archana Bhat, V. Geetha
As Wireless Sensor Network nodes are ID based network, it would be difficult to monitor the status of the same when it is connected to Internet of Things. So gateway is required to connect the network with Internet. In order to access and manage the network remotely, it is good to have IP based devices connected with each other. As IPv4 is being depleted, IPv6 was a solution for much larger address space. IP connectivity in sensor networks mainly depend on two IETF standards: 6LoWPAN and RPL. Routing protocol in 6LoWPAN is very precise due to limited node's potential. Existing protocol of 6LoWPAN does not satisfy Low power Lossy networks. IETF came up with IPv6 routing protocol for low power Lossy networks called RPL.
{"title":"Survey on routing protocols for Internet of Things","authors":"Archana Bhat, V. Geetha","doi":"10.1109/ISED.2017.8303949","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303949","url":null,"abstract":"As Wireless Sensor Network nodes are ID based network, it would be difficult to monitor the status of the same when it is connected to Internet of Things. So gateway is required to connect the network with Internet. In order to access and manage the network remotely, it is good to have IP based devices connected with each other. As IPv4 is being depleted, IPv6 was a solution for much larger address space. IP connectivity in sensor networks mainly depend on two IETF standards: 6LoWPAN and RPL. Routing protocol in 6LoWPAN is very precise due to limited node's potential. Existing protocol of 6LoWPAN does not satisfy Low power Lossy networks. IETF came up with IPv6 routing protocol for low power Lossy networks called RPL.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129597578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303906
A. Chattopadhyay, Kwok-Yan Lam
Security of (semi)-autonomous vehicles is a growing concern due to, first, the growing reliance of car functionalities on diverse (semi)-autonomous systems; second, the increased exposure of the such functionalities to potential attackers; third, the interaction of a single vehicle with myriads of other smart systems in an modern urban traffic infrastructure. In this paper, we review the security objectives of Autonomous Vehicle (AV) and argue that AV is a kind of Cyber-Physical System (CPS) for control and operations of the vehicle. We attempt to identify the core issues of securing an AV by modeling an AV as a special kind of CPS, which tend to be implemented by a complex interconnected embedded system hardware. Subsequently, the technical challenges of AV security are identified.
{"title":"Security of autonomous vehicle as a cyber-physical system","authors":"A. Chattopadhyay, Kwok-Yan Lam","doi":"10.1109/ISED.2017.8303906","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303906","url":null,"abstract":"Security of (semi)-autonomous vehicles is a growing concern due to, first, the growing reliance of car functionalities on diverse (semi)-autonomous systems; second, the increased exposure of the such functionalities to potential attackers; third, the interaction of a single vehicle with myriads of other smart systems in an modern urban traffic infrastructure. In this paper, we review the security objectives of Autonomous Vehicle (AV) and argue that AV is a kind of Cyber-Physical System (CPS) for control and operations of the vehicle. We attempt to identify the core issues of securing an AV by modeling an AV as a special kind of CPS, which tend to be implemented by a complex interconnected embedded system hardware. Subsequently, the technical challenges of AV security are identified.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130461848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303937
Pushpita Roy, A. Banerjee
In this paper, we address the problem of security in the context of Digital Microfluidic Biochips (DMFB) realizations, more specifically, we take up the concern of security threats on a given actuation sequence. Given a bio-chemical reaction synthesized for actuation on a given DMF architecture, we propose an automated method for verifying whether the synthesized actuation sequence is secure against malicious dispense attacks, using droplets dispensed by an attacker when the desired reaction is in execution. The foundation of our method lies in symbolic encoding. We highlight the benefits of the proposed approach through simulations on some well-known assay benchmarks.
{"title":"Security assessment of synthesized actuation sequences for digital microfluidic biochips","authors":"Pushpita Roy, A. Banerjee","doi":"10.1109/ISED.2017.8303937","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303937","url":null,"abstract":"In this paper, we address the problem of security in the context of Digital Microfluidic Biochips (DMFB) realizations, more specifically, we take up the concern of security threats on a given actuation sequence. Given a bio-chemical reaction synthesized for actuation on a given DMF architecture, we propose an automated method for verifying whether the synthesized actuation sequence is secure against malicious dispense attacks, using droplets dispensed by an attacker when the desired reaction is in execution. The foundation of our method lies in symbolic encoding. We highlight the benefits of the proposed approach through simulations on some well-known assay benchmarks.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132509862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303917
Nikita Gupta, Pragati Thakur, S. Dubey, A. Islam
Although Moore's law has been the most pursued principle since ever; it has become troublesome to apply that on the traditional MOS structures in today's scenario. Striking increment in the subthreshold leakage current, and various other disadvantages like gate-dielectric leakage gate-induced drain leakage (GIDL) are the major factors which limit the scaling of the MOS devices. And so, researchers are in need of novel ideas and mechanizations. Of so many of the lately surfacing devices, Carbon Nanotube Field Effect Transistor (CNFET) is becoming the hopeful alternative of MOSFETs, owing to its enviable properties of electrical, physical and mechanical factors. In this paper, a circuit based technique to lessen the unfavorable effects on the design metrics such as margin for write and read operation of MTJ memory cell is proposed. The effects of process, voltage and temperature (PVT) variations are investigated. The study is based on Monte Carlo simulations in a HSPICE environment, using a Stanford CNFET model. In this work, 2-CNFETs, 1-MTJ based STT-MRAM bit cell based on power gating technique is suggested to improve its performance metrics.
{"title":"Design of nonvolatile MRAM bitcell","authors":"Nikita Gupta, Pragati Thakur, S. Dubey, A. Islam","doi":"10.1109/ISED.2017.8303917","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303917","url":null,"abstract":"Although Moore's law has been the most pursued principle since ever; it has become troublesome to apply that on the traditional MOS structures in today's scenario. Striking increment in the subthreshold leakage current, and various other disadvantages like gate-dielectric leakage gate-induced drain leakage (GIDL) are the major factors which limit the scaling of the MOS devices. And so, researchers are in need of novel ideas and mechanizations. Of so many of the lately surfacing devices, Carbon Nanotube Field Effect Transistor (CNFET) is becoming the hopeful alternative of MOSFETs, owing to its enviable properties of electrical, physical and mechanical factors. In this paper, a circuit based technique to lessen the unfavorable effects on the design metrics such as margin for write and read operation of MTJ memory cell is proposed. The effects of process, voltage and temperature (PVT) variations are investigated. The study is based on Monte Carlo simulations in a HSPICE environment, using a Stanford CNFET model. In this work, 2-CNFETs, 1-MTJ based STT-MRAM bit cell based on power gating technique is suggested to improve its performance metrics.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131007003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303933
Dr. Naween Kumar, D. Dash
Recently, mobile sink based data gathering has been getting popularity among researchers in Wireless Sensor Networks (WSNs. As, sink mobility achieves prolonged network lifetime of the network by distributing load among the sensors. In certain applications, a mobile sink has to be moved along a given fixed path. But, due to fixed path and relatively slower speed of mobile sink, data gathering is delayed. Which can be reduced through optimizing the motion of the mobile sink. In this paper, our focus is to find the speed-schedule of the path-constrained mobile sink along a fixed path such that, the mobile sink will collect maximum data from the network within a given time. We refer the proposed problem as maximum data gathering motion planning of a mobile sink within a fixed time deadline (MDMPMS). We propose a deterministic polynomial time algorithm for the problem. Furthermore, we evaluate the performance of the proposed algorithm using simulation in MATLAB.
{"title":"Maximum data gathering through speed control of path-constrained mobile sink in WSN","authors":"Dr. Naween Kumar, D. Dash","doi":"10.1109/ISED.2017.8303933","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303933","url":null,"abstract":"Recently, mobile sink based data gathering has been getting popularity among researchers in Wireless Sensor Networks (WSNs. As, sink mobility achieves prolonged network lifetime of the network by distributing load among the sensors. In certain applications, a mobile sink has to be moved along a given fixed path. But, due to fixed path and relatively slower speed of mobile sink, data gathering is delayed. Which can be reduced through optimizing the motion of the mobile sink. In this paper, our focus is to find the speed-schedule of the path-constrained mobile sink along a fixed path such that, the mobile sink will collect maximum data from the network within a given time. We refer the proposed problem as maximum data gathering motion planning of a mobile sink within a fixed time deadline (MDMPMS). We propose a deterministic polynomial time algorithm for the problem. Furthermore, we evaluate the performance of the proposed algorithm using simulation in MATLAB.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115871854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303916
Ankita Samaddar, Moumita Das, A. Banerjee
In this paper, we propose a new memory DRAM controller scheduling policy for scheduling tasks in real time systems. Our proposal involves a memory bank aware partitioning strategy to partition the requests across banks based on a cost function on some task parameters to schedule memory requests so that the number of deadline misses get reduced significantly in a real time system. We used the Malardalen Worst Case Execution Time (WCET) benchmark programs as our real time tasks. We generated traces of these benchmark programs by running them on an X86 processor. We have developed an end to end setup from processor to memory and our results have been compared with state of the art DRAM controllers. Experimental results on these benchmark programs show the efficiency of our proposed scheme.
{"title":"A new memory scheduling policy for real time systems","authors":"Ankita Samaddar, Moumita Das, A. Banerjee","doi":"10.1109/ISED.2017.8303916","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303916","url":null,"abstract":"In this paper, we propose a new memory DRAM controller scheduling policy for scheduling tasks in real time systems. Our proposal involves a memory bank aware partitioning strategy to partition the requests across banks based on a cost function on some task parameters to schedule memory requests so that the number of deadline misses get reduced significantly in a real time system. We used the Malardalen Worst Case Execution Time (WCET) benchmark programs as our real time tasks. We generated traces of these benchmark programs by running them on an X86 processor. We have developed an end to end setup from processor to memory and our results have been compared with state of the art DRAM controllers. Experimental results on these benchmark programs show the efficiency of our proposed scheme.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114291134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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