Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303912
K. Khade, Revati Naik, Amey Patil
The proposed system focusses on designing a Line Follower Sensor for various robotic based applications. Unlike the traditional line follower sensor which uses IR pair as transmitter and photodiodes as receiver and works well only for white line over black surface or vice versa, this paper discusses the designing of sensor array using RGB LED as transmitter and Phototransistor as receiver. This sensor can be used for any colored surface and line as it can switch automatically between Red, Green and Blue color LED depending on surface and line colors making it an all color line follower. Thus, it can be used in places where the robot has to follow a line drawn over changing colored background. The sensor along with the controller is used to form an algorithm that can detect the change in surface color and make a decision to switch to a specific colored LED depending on the color on which it has to navigate. Furthermore, the system is designed for self-adjustment of the threshold value used for the motor control of the robot eliminating the need for manual threshold calculation. The ATMEGA328 controller is used for processing the analog sensor signals and for controlling the motor movement via H-Bridge motor driver. The main purpose of this paper is to design a cost effective and robust sensor that it is capable of sensing the change in its background color as well as line color and switching to a LED color that would differentiate between the surface and the line, self — threshold value adjustment to send motor control signals which in turn would provide proper path to the robot and follow the line and control the locomotion of the robot.
{"title":"Design of all color line follower sensor with auto calibration ability","authors":"K. Khade, Revati Naik, Amey Patil","doi":"10.1109/ISED.2017.8303912","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303912","url":null,"abstract":"The proposed system focusses on designing a Line Follower Sensor for various robotic based applications. Unlike the traditional line follower sensor which uses IR pair as transmitter and photodiodes as receiver and works well only for white line over black surface or vice versa, this paper discusses the designing of sensor array using RGB LED as transmitter and Phototransistor as receiver. This sensor can be used for any colored surface and line as it can switch automatically between Red, Green and Blue color LED depending on surface and line colors making it an all color line follower. Thus, it can be used in places where the robot has to follow a line drawn over changing colored background. The sensor along with the controller is used to form an algorithm that can detect the change in surface color and make a decision to switch to a specific colored LED depending on the color on which it has to navigate. Furthermore, the system is designed for self-adjustment of the threshold value used for the motor control of the robot eliminating the need for manual threshold calculation. The ATMEGA328 controller is used for processing the analog sensor signals and for controlling the motor movement via H-Bridge motor driver. The main purpose of this paper is to design a cost effective and robust sensor that it is capable of sensing the change in its background color as well as line color and switching to a LED color that would differentiate between the surface and the line, self — threshold value adjustment to send motor control signals which in turn would provide proper path to the robot and follow the line and control the locomotion of the robot.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130901681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303951
Teressa Longjam, D. Kisku
Handwritten signature verification is one of the significant research area where writers are verified or identified by their signatures. Handwritten signatures can be found in many official documents in day to day applications where people are fond to use their own scripts for writing the signatures. Usually, human experts look for the pattern of a signature in order to verify an authenticated document. The same expertise or even better can be adopted into an algorithm and run on a computer system where handwritten signatures could be accurately verified with minimum effort and time. As it is a behavioural biometrics trait, therefore writing style would decide the complexity of signature patterns of individual writers. Manipuri or Meithei is one of the official languages of the Indian state Manipur where large number of native people speak Manipuri language. This paper proposes a supervised learning approach for verifying individuals using their handwritten offline signatures. To accomplish this task, a set of local and global features related to the structure of the signature is extracted from offline signature. Further, this set of features is used for matching and classification of signatures using Support Vector Machines. Evaluation is performed on an offline Manipuri signature database containing 630 genuine and 140 forged signatures contributed by 70 individuals. The experimental results are found to be encouraging and effective while a set of local and global features are used for capturing the overall pattern of a Manipuri signature.
{"title":"A supervised manipuri offline signature verification system with global and local features","authors":"Teressa Longjam, D. Kisku","doi":"10.1109/ISED.2017.8303951","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303951","url":null,"abstract":"Handwritten signature verification is one of the significant research area where writers are verified or identified by their signatures. Handwritten signatures can be found in many official documents in day to day applications where people are fond to use their own scripts for writing the signatures. Usually, human experts look for the pattern of a signature in order to verify an authenticated document. The same expertise or even better can be adopted into an algorithm and run on a computer system where handwritten signatures could be accurately verified with minimum effort and time. As it is a behavioural biometrics trait, therefore writing style would decide the complexity of signature patterns of individual writers. Manipuri or Meithei is one of the official languages of the Indian state Manipur where large number of native people speak Manipuri language. This paper proposes a supervised learning approach for verifying individuals using their handwritten offline signatures. To accomplish this task, a set of local and global features related to the structure of the signature is extracted from offline signature. Further, this set of features is used for matching and classification of signatures using Support Vector Machines. Evaluation is performed on an offline Manipuri signature database containing 630 genuine and 140 forged signatures contributed by 70 individuals. The experimental results are found to be encouraging and effective while a set of local and global features are used for capturing the overall pattern of a Manipuri signature.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303950
Mrinal Goswami, Mohit Kumar, B. Sen
Quantum-dot cellular automata (QCA) has emerged as a promising and efficient nanoscale technology overcoming the demerits of the CMOS technology. With the rapid development in the field of nanotechnology, there has been an exponential increase in the practice of designing efficient logic circuits in the nanoscale era. However, it has always been a challenge for the designers to design a circuit meeting the requirements of a fast signal transfer mechanism and hence minimizing the delay to the lowest possible value. In this paper, a 5-input majority voter has been proposed which is used to synthesize an efficient 3-input XOR gate and XNOR gate. To find the significance of the proposed XOR gate, an efficient full adder as well as an odd and an even bit parity generator have also been implemented which shows significant improvement in terms of area, cell count and latency in comparison to the other previously proposed circuits.
{"title":"Cost effective realization of XOR logic in QCA","authors":"Mrinal Goswami, Mohit Kumar, B. Sen","doi":"10.1109/ISED.2017.8303950","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303950","url":null,"abstract":"Quantum-dot cellular automata (QCA) has emerged as a promising and efficient nanoscale technology overcoming the demerits of the CMOS technology. With the rapid development in the field of nanotechnology, there has been an exponential increase in the practice of designing efficient logic circuits in the nanoscale era. However, it has always been a challenge for the designers to design a circuit meeting the requirements of a fast signal transfer mechanism and hence minimizing the delay to the lowest possible value. In this paper, a 5-input majority voter has been proposed which is used to synthesize an efficient 3-input XOR gate and XNOR gate. To find the significance of the proposed XOR gate, an efficient full adder as well as an odd and an even bit parity generator have also been implemented which shows significant improvement in terms of area, cell count and latency in comparison to the other previously proposed circuits.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124159225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303931
Jaishree Mayank, Arijit Mondal
Scheduling of a set of tasks in multiprocessor environment is a computationally intensive job. There are primarily two broad approaches for scheduling of tasks on multiprocessors. In one of the approaches tasks are allocated to processor in the beginning (partition based strategy) and the other approaches maintain a global scheduler. There exist a large volume of work in multiprocessor scheduling having different optimization objectives such as schedule length, response time, processor utilization, etc. However, most of these works focus only in preemptive scheduling. Very less attention has been given for scheduling of non-preemptive tasks. In this work, we present a methodology for scheduling of a set of non-preemptive real-time tasks using minimum number of processors. We consider that the tasks are allocated to the processors using bin-packing strategies such as firstfit or best-fit and non-preemptive Earliest Deadline First (npEDF) scheduling method is applied to each processor. We did extensive experiments by combining different partitioning strategies with the ordering of tasks (period, utilization, etc). We found that First-Fit Increasing Period, Best-Fit Increasing Period, First-Fit Decreasing Utilization and Best-Fit Decreasing Utilization give reasonably good results. The success ratio of decreasing utilization heuristics are 10%–30% more than increasing period heuristics. We observed that First-Fit Decreasing Utilization and BestFit Decreasing Utilization takes more time than First-Fit Increasing Period and Best-Fit Increasing Period. We also compared our results with the existing approach.
{"title":"Non-preemptive multiprocessor scheduling for periodic real-time tasks","authors":"Jaishree Mayank, Arijit Mondal","doi":"10.1109/ISED.2017.8303931","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303931","url":null,"abstract":"Scheduling of a set of tasks in multiprocessor environment is a computationally intensive job. There are primarily two broad approaches for scheduling of tasks on multiprocessors. In one of the approaches tasks are allocated to processor in the beginning (partition based strategy) and the other approaches maintain a global scheduler. There exist a large volume of work in multiprocessor scheduling having different optimization objectives such as schedule length, response time, processor utilization, etc. However, most of these works focus only in preemptive scheduling. Very less attention has been given for scheduling of non-preemptive tasks. In this work, we present a methodology for scheduling of a set of non-preemptive real-time tasks using minimum number of processors. We consider that the tasks are allocated to the processors using bin-packing strategies such as firstfit or best-fit and non-preemptive Earliest Deadline First (npEDF) scheduling method is applied to each processor. We did extensive experiments by combining different partitioning strategies with the ordering of tasks (period, utilization, etc). We found that First-Fit Increasing Period, Best-Fit Increasing Period, First-Fit Decreasing Utilization and Best-Fit Decreasing Utilization give reasonably good results. The success ratio of decreasing utilization heuristics are 10%–30% more than increasing period heuristics. We observed that First-Fit Decreasing Utilization and BestFit Decreasing Utilization takes more time than First-Fit Increasing Period and Best-Fit Increasing Period. We also compared our results with the existing approach.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133902159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303918
R. Mukherjee, Anupam Banerjee, I. Chakrabarti, P. Dutta, A. Ray
The widely used H.264 video coding standard has adopted Context-based Adaptive Variable Length Coding (CAVLC) as one of its techniques for entropy encoding. In this work, VLSI design for implementing CAVLC decoder has been proposed. The design considers the speed requirements for transmission of HD videos. The architecture efficiently mixes both tree-based method and bit-parallel variable length decoding (VLD) which enhances the speed without compromising the area. The design is able to process HD frames (1080p format) at a frame rate of 30fps while working at 131 MHz clock frequency. Efficient utilization of area has been taken care off. The implemented architecture can be integrated with other blocks of H.264 to form a complete video codec.
{"title":"Efficient VLSI design of CAVLC decoder of H.264 for HD videos","authors":"R. Mukherjee, Anupam Banerjee, I. Chakrabarti, P. Dutta, A. Ray","doi":"10.1109/ISED.2017.8303918","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303918","url":null,"abstract":"The widely used H.264 video coding standard has adopted Context-based Adaptive Variable Length Coding (CAVLC) as one of its techniques for entropy encoding. In this work, VLSI design for implementing CAVLC decoder has been proposed. The design considers the speed requirements for transmission of HD videos. The architecture efficiently mixes both tree-based method and bit-parallel variable length decoding (VLD) which enhances the speed without compromising the area. The design is able to process HD frames (1080p format) at a frame rate of 30fps while working at 131 MHz clock frequency. Efficient utilization of area has been taken care off. The implemented architecture can be integrated with other blocks of H.264 to form a complete video codec.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116906687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303914
S. Ghosh, S. Roy, H. Rahaman, C. Giri
Three dimensional integrated circuit (3D IC) based on through-silicon-via (TSV) is gaining significant importance in semiconductor industry. During manufacturing process there may have some faulty TSVs. Recovery of these faulty TSVs is necessary for a reliable TSV based system. Use of redundant TSVs to recover faulty TSVs is an attractive solution for repairing faulty TSV. Proper grouping of functional and redundant TSVs and efficient techniques of signal shifting through redundant TSVs can improve the recovery rate of faulty TSVs. In this paper, we propose a methodology to make connection between functional TSVs and redundant TSVs for re-route the signal using multiplexers (MUXs) in such a way that required number of MUXs will be minimum and dependency will be maximum.
{"title":"TSV repairing for 3D ICs using redundant TSV","authors":"S. Ghosh, S. Roy, H. Rahaman, C. Giri","doi":"10.1109/ISED.2017.8303914","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303914","url":null,"abstract":"Three dimensional integrated circuit (3D IC) based on through-silicon-via (TSV) is gaining significant importance in semiconductor industry. During manufacturing process there may have some faulty TSVs. Recovery of these faulty TSVs is necessary for a reliable TSV based system. Use of redundant TSVs to recover faulty TSVs is an attractive solution for repairing faulty TSV. Proper grouping of functional and redundant TSVs and efficient techniques of signal shifting through redundant TSVs can improve the recovery rate of faulty TSVs. In this paper, we propose a methodology to make connection between functional TSVs and redundant TSVs for re-route the signal using multiplexers (MUXs) in such a way that required number of MUXs will be minimum and dependency will be maximum.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132594703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303920
Parth Shah, K. Abhishek, J. Soumya
Network-on-Chip (NoC) has been introduced to address the communication problems associated with the traditional bus based System-on-Chip (SoC) architectures. NoC can be designed either using regular or irregular architectures. Even though many regular architectures have been proposed in the literature, there is a mismatch between the application requirements and the design. Application specific NoC designs have been proposed to match the requirements of the applications, which are irregular in nature. Due to the heavy integration of the components on the chip, designs that are vulnerable to faults in links can render the chip unusable. This paper first sets the benchmark of minimum possible communication cost and thereafter proposes a greedy algorithm to develop link fault-tolerant application specific topology for the given application core graph which meets that benchmark.
{"title":"Fault-tolerant application specific Network-on-Chip design","authors":"Parth Shah, K. Abhishek, J. Soumya","doi":"10.1109/ISED.2017.8303920","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303920","url":null,"abstract":"Network-on-Chip (NoC) has been introduced to address the communication problems associated with the traditional bus based System-on-Chip (SoC) architectures. NoC can be designed either using regular or irregular architectures. Even though many regular architectures have been proposed in the literature, there is a mismatch between the application requirements and the design. Application specific NoC designs have been proposed to match the requirements of the applications, which are irregular in nature. Due to the heavy integration of the components on the chip, designs that are vulnerable to faults in links can render the chip unusable. This paper first sets the benchmark of minimum possible communication cost and thereafter proposes a greedy algorithm to develop link fault-tolerant application specific topology for the given application core graph which meets that benchmark.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"7 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132792550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303948
Moumita Chakraborty, Debasri Saha, A. Chakrabarti
This paper addresses a CAD implementation for power-efficient power-distribution network (PDN) design for multi-voltage system-on-chip (SoC) in pre-layout stage. High power efficiency and significant reduction in supply noise are achieved through optimization of different stages in PDN design for multi-voltage SoCs. The stages are a) selection of appropriate tree topology based on the multiple supply voltage (MSV), b) proper Vdd allocation for different functional modules, c) appropriate decoupling capacitance (Decap) allocation at pre-layout stage. In this paper, each of these three criteria has been taken care of to achieve higher power efficiency and satisfactory noise reduction in the PDN. The proposed PDN design is implemented for 1024 point FFT core. Experimental results demonstrate the efficacy of our proposed technique. The power is maximally reduced by 90.29% and average peak noise has been maximally suppressed by 98.53% at the pre-layout stage after allocation of multiple Vdd in the functional modules of FFT.
{"title":"A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage","authors":"Moumita Chakraborty, Debasri Saha, A. Chakrabarti","doi":"10.1109/ISED.2017.8303948","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303948","url":null,"abstract":"This paper addresses a CAD implementation for power-efficient power-distribution network (PDN) design for multi-voltage system-on-chip (SoC) in pre-layout stage. High power efficiency and significant reduction in supply noise are achieved through optimization of different stages in PDN design for multi-voltage SoCs. The stages are a) selection of appropriate tree topology based on the multiple supply voltage (MSV), b) proper Vdd allocation for different functional modules, c) appropriate decoupling capacitance (Decap) allocation at pre-layout stage. In this paper, each of these three criteria has been taken care of to achieve higher power efficiency and satisfactory noise reduction in the PDN. The proposed PDN design is implemented for 1024 point FFT core. Experimental results demonstrate the efficacy of our proposed technique. The power is maximally reduced by 90.29% and average peak noise has been maximally suppressed by 98.53% at the pre-layout stage after allocation of multiple Vdd in the functional modules of FFT.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130323869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ISED.2017.8303946
Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman
This work presents a testing scheme for detection of two new type of faults (gate appearance and control appearance fault) in reversible circuit. The testing scheme not only efficiently detects the specified faults with minimum number of test vectors but localizes it simultaneously. Our developed approach only requires a single test vector to detect gate appearance fault while to find control appearance fault it needs n test vectors, where n is the number of input lines present in the circuit. The proposed technique can also work for very large circuits as well. In way to verify logical correctness of our developed technique, we have successfully tested different types of benchmark circuits over our proposed algorithms and obtained results are given at the end of this work.
{"title":"Detection and localization of appearance faults in reversible circuits","authors":"Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/ISED.2017.8303946","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303946","url":null,"abstract":"This work presents a testing scheme for detection of two new type of faults (gate appearance and control appearance fault) in reversible circuit. The testing scheme not only efficiently detects the specified faults with minimum number of test vectors but localizes it simultaneously. Our developed approach only requires a single test vector to detect gate appearance fault while to find control appearance fault it needs n test vectors, where n is the number of input lines present in the circuit. The proposed technique can also work for very large circuits as well. In way to verify logical correctness of our developed technique, we have successfully tested different types of benchmark circuits over our proposed algorithms and obtained results are given at the end of this work.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133581382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Phonocardiogram signal includes heart sound with murmurs gives valuable information for the detection of cardiac diseases. This paper focus for the detection of all the peaks of 300 Heart sound from using Variational Mode Decomposition. The starting and end of each heart sound is detected using the normalized envelogram of Shannon energy, the extraction of heart murmurs is thereafter accomplished by setting a threshold level for them and finding the peaks using Variational Mode Decomposition method. Finally, 250 peaks data are trained using Multi-Layer perceptron neural network with two and three hidden layers by changing the weightage of the hidden layer neuron and all the 300 peaks data are randomly tested for best results. The Multi-Layer Perceptron based neuron network has shown a best correct prediction rate of 93.685%. The technique indicates that a combination of signal processing, MLP classification and mathematical modelling can be used as a precise method for abnormality analysis of heart.
{"title":"Abnormality analysis of pcg signal using vmd and mlp neural network","authors":"Sinam Ajitkumar Singh, Abhishek Verma, Shuvam Chhetry, Swanirbhar Majumder","doi":"10.1109/ISED.2017.8303911","DOIUrl":"https://doi.org/10.1109/ISED.2017.8303911","url":null,"abstract":"Phonocardiogram signal includes heart sound with murmurs gives valuable information for the detection of cardiac diseases. This paper focus for the detection of all the peaks of 300 Heart sound from using Variational Mode Decomposition. The starting and end of each heart sound is detected using the normalized envelogram of Shannon energy, the extraction of heart murmurs is thereafter accomplished by setting a threshold level for them and finding the peaks using Variational Mode Decomposition method. Finally, 250 peaks data are trained using Multi-Layer perceptron neural network with two and three hidden layers by changing the weightage of the hidden layer neuron and all the 300 peaks data are randomly tested for best results. The Multi-Layer Perceptron based neuron network has shown a best correct prediction rate of 93.685%. The technique indicates that a combination of signal processing, MLP classification and mathematical modelling can be used as a precise method for abnormality analysis of heart.","PeriodicalId":147019,"journal":{"name":"2017 7th International Symposium on Embedded Computing and System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130947524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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