Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651727
W. Lai, Yi Wu
The proposed article introduces RF wireless integrated transceiver for Bluetooth wireless of medical biosensing applications. The proposed wireless integrated transceiver consists of two-stage power amplifier (PA) with predistorter, band-pass Gm-C filter, distributed single-pole double-throw (SPDT) radio frequency (RF) switching, low noise amplifier (LNA) and chip antenna. The presented PA design presents conversion gain of 13 dB, the output 1-dB compression point (OP1dB) of 2.7 dBm and power added efficiency (PAE) more than 20%, respectively. The presented LNA exhibits return loss of input more than 10.32 dB, return loss of output more than 10.77 dB, the produce gain between 8.16 dB and 13.1 dB, isolation more than 42 dB, the produce noise figure between 4.48 dB and 7.66 dB, the produce input 1-dB compression point (IP1dB) between -13.43 dB and -5.43 dB, respectively. The implemented integrated RF frontend using 0.18um CMOS technology has experimental outdoor/ indoor throughput base on channels, distance and concurrently complies with the Bluetooth wireless requirement.
{"title":"RF Front-end with Antenna for Bluetooh Wireless of Medical Biosensing","authors":"W. Lai, Yi Wu","doi":"10.1109/asid52932.2021.9651727","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651727","url":null,"abstract":"The proposed article introduces RF wireless integrated transceiver for Bluetooth wireless of medical biosensing applications. The proposed wireless integrated transceiver consists of two-stage power amplifier (PA) with predistorter, band-pass Gm-C filter, distributed single-pole double-throw (SPDT) radio frequency (RF) switching, low noise amplifier (LNA) and chip antenna. The presented PA design presents conversion gain of 13 dB, the output 1-dB compression point (OP1dB) of 2.7 dBm and power added efficiency (PAE) more than 20%, respectively. The presented LNA exhibits return loss of input more than 10.32 dB, return loss of output more than 10.77 dB, the produce gain between 8.16 dB and 13.1 dB, isolation more than 42 dB, the produce noise figure between 4.48 dB and 7.66 dB, the produce input 1-dB compression point (IP1dB) between -13.43 dB and -5.43 dB, respectively. The implemented integrated RF frontend using 0.18um CMOS technology has experimental outdoor/ indoor throughput base on channels, distance and concurrently complies with the Bluetooth wireless requirement.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126957578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651678
{"title":"[ASID 2021 Front cover]","authors":"","doi":"10.1109/asid52932.2021.9651678","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651678","url":null,"abstract":"","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651712
{"title":"ASID 2021 TOC","authors":"","doi":"10.1109/asid52932.2021.9651712","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651712","url":null,"abstract":"","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122013794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651687
Yufei Han, Yibo Li, Yao Li
As affine projection adaptive algorithm performance relates to the projection order, it is necessary to analyze the projection order. When the projection order increases, a high convergence speed will be acquired. Whereas, it also brings the huge computational cost and the large mean square error (MSE). It seems advisable to reduce the projection order when it is necessary. Therefore, a novel method which dynamically adjusts the projection order is presented. It changes the projection order by different convergence state. The goal is to find the optimized projection order which can balance the steady-state and convergence performance. Experiments demonstrate that the proposed algorithm equips good convergence ability and low MSE.
{"title":"A Novel Affine Projection Algorithm Based on Variable Projection Order","authors":"Yufei Han, Yibo Li, Yao Li","doi":"10.1109/asid52932.2021.9651687","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651687","url":null,"abstract":"As affine projection adaptive algorithm performance relates to the projection order, it is necessary to analyze the projection order. When the projection order increases, a high convergence speed will be acquired. Whereas, it also brings the huge computational cost and the large mean square error (MSE). It seems advisable to reduce the projection order when it is necessary. Therefore, a novel method which dynamically adjusts the projection order is presented. It changes the projection order by different convergence state. The goal is to find the optimized projection order which can balance the steady-state and convergence performance. Experiments demonstrate that the proposed algorithm equips good convergence ability and low MSE.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651696
Quanxiu Chen, Yi Liu, Zhenyu Wu, Jian Liao
For accurately assessing the reliability of space application toward soft errors, this paper proposed a method of Single Event Effect simulation method for Large Scale Integrated Circuits (LSI). This simulation method divided into three levels: fault model, fault injection and target system simulation, which consists of a variety of simulation tools, such as TCAD, SPICE circuit simulator and analyzing tools of gate-level netlist. A 4-stage in-order RISC-V soft processor is used as the simulation target system. The simulation method has the following advantages: 1. It is a universal method of testing any large-scale integrated circuit including its peripheral components. 2. By input the gate-level net-list of the circuit and add the simulation stimulus, the method can get the simulation report automatically. 3. The soft error can be traced: The faulty node and the voltage waveform of the node can be reported intuitively.
{"title":"A Single Event Effect Simulation Method for RISC-V Processor","authors":"Quanxiu Chen, Yi Liu, Zhenyu Wu, Jian Liao","doi":"10.1109/asid52932.2021.9651696","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651696","url":null,"abstract":"For accurately assessing the reliability of space application toward soft errors, this paper proposed a method of Single Event Effect simulation method for Large Scale Integrated Circuits (LSI). This simulation method divided into three levels: fault model, fault injection and target system simulation, which consists of a variety of simulation tools, such as TCAD, SPICE circuit simulator and analyzing tools of gate-level netlist. A 4-stage in-order RISC-V soft processor is used as the simulation target system. The simulation method has the following advantages: 1. It is a universal method of testing any large-scale integrated circuit including its peripheral components. 2. By input the gate-level net-list of the circuit and add the simulation stimulus, the method can get the simulation report automatically. 3. The soft error can be traced: The faulty node and the voltage waveform of the node can be reported intuitively.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114331616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651718
Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan
A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.
{"title":"Digital Decimation Filter Design for a 3rd-Order Sigma-Delta Modulator with Achieving 129 dB SNR","authors":"Dongyu Li, Zhijie Chen, Xu Liu, Zhiqi Shen, Y. Xing, Peiyuan Wan","doi":"10.1109/asid52932.2021.9651718","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651718","url":null,"abstract":"A digital decimation filter in a 3rd-order Sigma-Delta analog-to-digital converter (Σ-Δ ADC) is proposed in this paper. The digital filter consists of a cascaded integrator comb (CIC) filter, a compensation filter, a half-band filter, and a configurable decimation multiple module. CSD coding is used and the FIR filter structure is optimized in this paper to greatly reduce the area of the multiplier and the number of registers. The decimation factor can be configured from 512 to 4096, and the signal-to-noise ratio (SNR) performance increases with higher decimation factor. Cooperating with a 3rd-order 1-bit modulator, this design can achieve 129dB SNR with a 512 decimation factor. Simulation results shows that this design has realized the complete function of the digital sampling filter with configurable sampling multiples.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114788233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651690
Yunrui Zhang, Zichao Guo, Jian Li, Fan Cai, Jianyang Zhou
As the IoT industry continues to boom, the market demand for embedded IoT processors will steadily grow in the future. As a new streamlined instruction set architecture, RISC-V has received a lot of attention since its release, and its concise instruction coding and flexible modular extensions make it ideal for the implementation of embedded IoT processors. In this paper, we design a 3-stage pipelined scalar micro-out-of-order processor based on the RISC-V architecture. The processor is compatible with the RV32IMA instruction set and has been verified by simulation and FPGA prototype to be functionally correct with a Coremark performance of 2.93 Coremark/MHz. We finally implemented it using SMIC 180nm process with a main frequency of 50MHz. The final experimental results show that the core circuit of the processor is 35K gate and the power consumption is 0.20 mW/MHz.
{"title":"AnnikaCore: RISC-V Architecture Processor Design and Implementation for IoT","authors":"Yunrui Zhang, Zichao Guo, Jian Li, Fan Cai, Jianyang Zhou","doi":"10.1109/asid52932.2021.9651690","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651690","url":null,"abstract":"As the IoT industry continues to boom, the market demand for embedded IoT processors will steadily grow in the future. As a new streamlined instruction set architecture, RISC-V has received a lot of attention since its release, and its concise instruction coding and flexible modular extensions make it ideal for the implementation of embedded IoT processors. In this paper, we design a 3-stage pipelined scalar micro-out-of-order processor based on the RISC-V architecture. The processor is compatible with the RV32IMA instruction set and has been verified by simulation and FPGA prototype to be functionally correct with a Coremark performance of 2.93 Coremark/MHz. We finally implemented it using SMIC 180nm process with a main frequency of 50MHz. The final experimental results show that the core circuit of the processor is 35K gate and the power consumption is 0.20 mW/MHz.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651707
Xuanye Dai, Weikai Zhao, Lunyao Wang
Considering that the introduction of the DC product terms tends to minimize the logic function which helps for circuit area saving. This paper proposes the DC cover based approximate computing technique for logic function minimization and circuit area saving. The proposed area optimization algorithm mainly includes the DC cover search methods, error rate calculation, and error rate control. The optimization algorithm is implemented in C language and tested using the MCNC (Microelectronics Center of North Carolina) Benchmarks. Experimental results show that compared with those accurate solutions, the proposed algorithm has the average circuit area is reduced by 73.89% with an average error rate of 4.38%.
考虑到直流积项的引入倾向于最小化逻辑功能，从而有助于节省电路面积。从逻辑函数最小化和节省电路面积的角度出发，提出了一种基于直流覆盖的近似计算方法。提出的区域优化算法主要包括DC覆盖搜索方法、错误率计算和错误率控制。该优化算法用C语言实现，并在MCNC (North Carolina微电子中心)基准测试中进行了测试。实验结果表明，与那些精确解相比，本文算法的平均电路面积减少了73.89%，平均错误率为4.38%。
{"title":"Area Optimization Using DC Cover Based Approximate Computing Technique","authors":"Xuanye Dai, Weikai Zhao, Lunyao Wang","doi":"10.1109/asid52932.2021.9651707","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651707","url":null,"abstract":"Considering that the introduction of the DC product terms tends to minimize the logic function which helps for circuit area saving. This paper proposes the DC cover based approximate computing technique for logic function minimization and circuit area saving. The proposed area optimization algorithm mainly includes the DC cover search methods, error rate calculation, and error rate control. The optimization algorithm is implemented in C language and tested using the MCNC (Microelectronics Center of North Carolina) Benchmarks. Experimental results show that compared with those accurate solutions, the proposed algorithm has the average circuit area is reduced by 73.89% with an average error rate of 4.38%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126437560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651689
Wei Liu, Yongzhao Du
The ECG signal is a weak low-frequency signal from the human body. It is highly susceptible to noise interference from inside and outside the body during acquisition, affecting the clinician's diagnosis of heart disease. The ECG signal in an ideal state was first used as the raw data. By adding Gaussian white noise as the noise during routine ECG acquisition, each scale's estimated noise standard deviation was used as a natural condition to determine whether it was noisy or not. Experiments were conducted on ECG signals from the MIT-BIH database, and the results showed that the improved denoising algorithm method resulted in a 6.67% increase in the mean signal to noise ratio (SNR), a 0.01% reduction in the mean root mean square (RMS) error and a smooth ECG image signal. Compared with the traditional wavelet coefficient correlation denoising method, the improved wavelet coefficient correlation denoising method proposed in this paper has a better denoising effect.
{"title":"An Improved ECG Denoising Algorithm Based on Wavelet-scale Correlation Coefficients","authors":"Wei Liu, Yongzhao Du","doi":"10.1109/asid52932.2021.9651689","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651689","url":null,"abstract":"The ECG signal is a weak low-frequency signal from the human body. It is highly susceptible to noise interference from inside and outside the body during acquisition, affecting the clinician's diagnosis of heart disease. The ECG signal in an ideal state was first used as the raw data. By adding Gaussian white noise as the noise during routine ECG acquisition, each scale's estimated noise standard deviation was used as a natural condition to determine whether it was noisy or not. Experiments were conducted on ECG signals from the MIT-BIH database, and the results showed that the improved denoising algorithm method resulted in a 6.67% increase in the mean signal to noise ratio (SNR), a 0.01% reduction in the mean root mean square (RMS) error and a smooth ECG image signal. Compared with the traditional wavelet coefficient correlation denoising method, the improved wavelet coefficient correlation denoising method proposed in this paper has a better denoising effect.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128144844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651720
Hongji Wang, Gang Yao, Beizhan Wang
In quantum cryptography research area, quantum digital signature is an important research field. To provide a better privacy for users in constructing quantum digital signature, the stronger anonymity of quantum digital signatures is required. Quantum ring signature scheme focuses on anonymity in certain scenarios. Using quantum ring signature scheme, the quantum message signer hides his identity into a group. At the same time, there is no need for any centralized organization when the user uses the quantum ring signature scheme. The group used to hide the signer identity can be immediately selected by the signer himself, and no collaboration between users.Since the quantum finite automaton signature scheme is very efficient quantum digital signature scheme, based on it, we propose a new quantum ring signature scheme. We also showed that the new scheme we proposed is of feasibility, correctness, anonymity, and unforgeability. And furthermore, the new scheme can be implemented only by logical operations, so it is easy to implement.
{"title":"A Quantum Ring Signature Scheme Based on the Quantum Finite Automata Signature Scheme","authors":"Hongji Wang, Gang Yao, Beizhan Wang","doi":"10.1109/asid52932.2021.9651720","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651720","url":null,"abstract":"In quantum cryptography research area, quantum digital signature is an important research field. To provide a better privacy for users in constructing quantum digital signature, the stronger anonymity of quantum digital signatures is required. Quantum ring signature scheme focuses on anonymity in certain scenarios. Using quantum ring signature scheme, the quantum message signer hides his identity into a group. At the same time, there is no need for any centralized organization when the user uses the quantum ring signature scheme. The group used to hide the signer identity can be immediately selected by the signer himself, and no collaboration between users.Since the quantum finite automaton signature scheme is very efficient quantum digital signature scheme, based on it, we propose a new quantum ring signature scheme. We also showed that the new scheme we proposed is of feasibility, correctness, anonymity, and unforgeability. And furthermore, the new scheme can be implemented only by logical operations, so it is easy to implement.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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