Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651685
Furong Liu, Fengsui Wang, Jingang Chen, Qisheng Wang
For cross-modality person re-identiflcation, the intra-class difference between visible images and infrared images of the same identity is large, and how to reduce this intra-class difference has become the key of cross-modality person re-identification. Therefore, we proposed a multi-loss function for cross-modality person re-identification. Firstly, the global attention mechanism was embedded in the Resnet50 network to retain non-local feature information. Secondly, generalized-mean pooling is used to increase feature information extraction for different fine-grained regions by adjusting parameters. Finally, we design a new total loss function to supervise network learning and improve model accuracy. The proposed method achieves an average accuracy of 54.18% and 78.40% in the SYSU-MM01 and RegDB datasets. The experimental results show that the proposed method can effectively improve the accuracy of cross-modality person re-identiflcation.
{"title":"Multi Loss Function for Cross-Modality Person Re-Identification","authors":"Furong Liu, Fengsui Wang, Jingang Chen, Qisheng Wang","doi":"10.1109/asid52932.2021.9651685","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651685","url":null,"abstract":"For cross-modality person re-identiflcation, the intra-class difference between visible images and infrared images of the same identity is large, and how to reduce this intra-class difference has become the key of cross-modality person re-identification. Therefore, we proposed a multi-loss function for cross-modality person re-identification. Firstly, the global attention mechanism was embedded in the Resnet50 network to retain non-local feature information. Secondly, generalized-mean pooling is used to increase feature information extraction for different fine-grained regions by adjusting parameters. Finally, we design a new total loss function to supervise network learning and improve model accuracy. The proposed method achieves an average accuracy of 54.18% and 78.40% in the SYSU-MM01 and RegDB datasets. The experimental results show that the proposed method can effectively improve the accuracy of cross-modality person re-identiflcation.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124263074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651487
Bingzheng Wu, Huiling Wu, Yongzhao Du, Peizhong Liu
Congenital heart defect is one of the most common fetal congenital defects. Every year, about 1% of newborns in the world suffer from this disease, and the proportion in developing countries reaches up to 4%-5%. Automatic identification of standard fetal heart sections from 2D ultrasound scanning video is an important prerequisite for examining a fetus with congenital heart disease. In China, most areas belong to rural areas. In this difficult environment, it is extremely difficult to diagnose fetuses with congenital heart disease by prenatal sonographers, which requires sonographers with rich qualifications to make the diagnosis, but few sonographers meet this qualification in rural areas. In this study, a new method based on Fast-RCNN deep learning with Mobilenet as the backbone network is proposed to automatically identify the standard section of fetal heart. This model can not only help sonographers collect fetal ultrasound images in practice, but also provide a reliable basis for later analysis of the fetal images, save more time and enhance efficiency. And this method can not only help new ultrasound physicians, but also provide high-qualified sonographers enough auxiliary diagnosis effects. All the data sets used in this method collected from the cooperative hospitals of colleges and universities, and the data volume is 1839, which can be split into training set(1479) and test set(360). In three centuries of repeated trials, the Mean Average Precision (MAP) on the validation set reaches 92.49%, and the accuracy rate reaches 90%. In the later period, some comparative experiments of different neural networks have been carried out, which proves that the method in this study is superior to other neural networks and can bring enough benefits to ultrasound physicians.
先天性心脏缺陷是最常见的胎儿先天性缺陷之一。全世界每年约有1%的新生儿患有此病，发展中国家的这一比例高达4%-5%。从二维超声扫描视频中自动识别标准胎儿心脏切片是检查先天性心脏病胎儿的重要前提。在中国，大部分地区属于农村地区。在这种艰苦的环境下，通过产前超声诊断先天性心脏病胎儿的难度极大，这就需要具备丰富资质的超声医师进行诊断，而在农村地区，具备这一资质的超声医师却很少。本研究提出了一种以Mobilenet为骨干网络，基于Fast-RCNN深度学习的胎儿心脏标准切片自动识别方法。该模型不仅可以帮助超声医师在实践中采集胎儿超声图像，还可以为后期胎儿图像的分析提供可靠的依据，节省更多的时间，提高效率。该方法不仅可以帮助新的超声医师，而且可以为高素质的超声医师提供足够的辅助诊断效果。本方法使用的所有数据集均来自高校合作医院，数据量为1839，可分为训练集(1479)和测试集(360)。经过三个世纪的反复试验，验证集的Mean Average Precision (MAP)达到92.49%，正确率达到90%。后期进行了不同神经网络的对比实验，证明本研究方法优于其他神经网络，可以为超声医师带来足够的效益。
{"title":"Automatic Recognition of Fetal Heart Standard Section Based on Fast-RCNN","authors":"Bingzheng Wu, Huiling Wu, Yongzhao Du, Peizhong Liu","doi":"10.1109/asid52932.2021.9651487","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651487","url":null,"abstract":"Congenital heart defect is one of the most common fetal congenital defects. Every year, about 1% of newborns in the world suffer from this disease, and the proportion in developing countries reaches up to 4%-5%. Automatic identification of standard fetal heart sections from 2D ultrasound scanning video is an important prerequisite for examining a fetus with congenital heart disease. In China, most areas belong to rural areas. In this difficult environment, it is extremely difficult to diagnose fetuses with congenital heart disease by prenatal sonographers, which requires sonographers with rich qualifications to make the diagnosis, but few sonographers meet this qualification in rural areas. In this study, a new method based on Fast-RCNN deep learning with Mobilenet as the backbone network is proposed to automatically identify the standard section of fetal heart. This model can not only help sonographers collect fetal ultrasound images in practice, but also provide a reliable basis for later analysis of the fetal images, save more time and enhance efficiency. And this method can not only help new ultrasound physicians, but also provide high-qualified sonographers enough auxiliary diagnosis effects. All the data sets used in this method collected from the cooperative hospitals of colleges and universities, and the data volume is 1839, which can be split into training set(1479) and test set(360). In three centuries of repeated trials, the Mean Average Precision (MAP) on the validation set reaches 92.49%, and the accuracy rate reaches 90%. In the later period, some comparative experiments of different neural networks have been carried out, which proves that the method in this study is superior to other neural networks and can bring enough benefits to ultrasound physicians.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116089558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651700
Jiahao Fang, Liji Wu, Xiangmin Zhang
SM2 algorithm has been widely used in the field of financial IC cards. However, it is easy to be attacked by the side channel, and Simple Power Analysis (SPA) is the most common attack method. An atomic point addition and point doubling algorithms is proposed to be used in SM2 algorithm against SPA. Based on the software and hardware co-design with SAKURA-G FPGA board, the correctness of the algorithm is verified in the 256-bit SM2 digital signature algorithm, and the power consumption curves are collected. Experiments show that the atomic algorithm improves the ability to resist SPA in SM2.
{"title":"A Novel SPA Countermeasure for SM2 Hardware Implementation with FPGA","authors":"Jiahao Fang, Liji Wu, Xiangmin Zhang","doi":"10.1109/asid52932.2021.9651700","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651700","url":null,"abstract":"SM2 algorithm has been widely used in the field of financial IC cards. However, it is easy to be attacked by the side channel, and Simple Power Analysis (SPA) is the most common attack method. An atomic point addition and point doubling algorithms is proposed to be used in SM2 algorithm against SPA. Based on the software and hardware co-design with SAKURA-G FPGA board, the correctness of the algorithm is verified in the 256-bit SM2 digital signature algorithm, and the power consumption curves are collected. Experiments show that the atomic algorithm improves the ability to resist SPA in SM2.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116146190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651714
Boyong Jin, Zhijie Chen, Xu Liu, Zhiqi Shen, Yucheng Bao, Y. Xing, Peiyuan Wan
This paper presents a 3-th order active-RC complex filter with fast automatic frequency tuning circuit. The bandwidth and center frequency of a complex filter are mainly related to the absolute time constant value of resistors and capacitors. Due to the process variation, the value may vary even over ±40%. A frequency tuning circuit for active-RC complex filter can avoid the affect of process variation and provide ideal frequency response. This paper proposed an on-chip fast frequency tuning circuit with successive approximation register (SAR) logic. Compared with the conventional counter-based logic, the proposed circuit can exhibit high tuning speed. This 3-th order active-RC complex filter with 5-bit fast automatic tuning circuit is designed in SMIC 55nm process.
{"title":"A SAR-based Fast Automatic Frequency Tuning Circuit in a 3-th Order Active-RC Complex Filter","authors":"Boyong Jin, Zhijie Chen, Xu Liu, Zhiqi Shen, Yucheng Bao, Y. Xing, Peiyuan Wan","doi":"10.1109/asid52932.2021.9651714","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651714","url":null,"abstract":"This paper presents a 3-th order active-RC complex filter with fast automatic frequency tuning circuit. The bandwidth and center frequency of a complex filter are mainly related to the absolute time constant value of resistors and capacitors. Due to the process variation, the value may vary even over ±40%. A frequency tuning circuit for active-RC complex filter can avoid the affect of process variation and provide ideal frequency response. This paper proposed an on-chip fast frequency tuning circuit with successive approximation register (SAR) logic. Compared with the conventional counter-based logic, the proposed circuit can exhibit high tuning speed. This 3-th order active-RC complex filter with 5-bit fast automatic tuning circuit is designed in SMIC 55nm process.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.
{"title":"VLSI Architecture Design for Adder Convolution Neural Network Accelerator","authors":"Mingyong Zhuang, Xinhui Liao, Huhong Wu, Jianyang Zhou, Zichao Guo","doi":"10.1109/asid52932.2021.9651682","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651682","url":null,"abstract":"Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114854988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper calibrates an inductorless LNA’s NF and S11 based on non-intrusive self-calibration. Since the NF and S11 of the inductorless LNA depend on transconductance and channel resistance of transistors which have a relationship with the transistors’ port voltage, we use measured dc voltage from the LNA to estimate its NF and S11. Also, we choose the LNA’s bias current and the ratio of the current mirror providing current for PMOS bias transistor as tuning knobs to adjust the LNA’s S11 and NF. To realize non-intrusive self-calibration, measured dc voltage and currents from dummy circuits are used to estimate the LNA’s S11 and NF. Different dummy sizes are used, and we find that there is a trade-off between dummy size and calibration results. The circuits are implemented in 22-nm ultra-low leakage CMOS technology and the calibration algorithm was implemented with Matlab. The simulation results show that a 15.5% yield improvement could be obtained when dc voltages are measured from the primary LNA with current from a 1/2 scaled current mirror and a yield improvement from 11% to 16.5% could be obtained when dc voltages and currents are measured from different sets of dummy circuits.
{"title":"A Non-Intrusive Self-Calibration Method for the Circuit Design of Inductorless Low Noise Amplifier","authors":"Wenrun Xiao, Weikang Wu, Yin-Wei Chang, Jidong Diao, Yanping Qiao, Xianming Liu, Shan He, Xiaojie Liu, Donghui Guo","doi":"10.1109/asid52932.2021.9651692","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651692","url":null,"abstract":"This paper calibrates an inductorless LNA’s NF and S11 based on non-intrusive self-calibration. Since the NF and S11 of the inductorless LNA depend on transconductance and channel resistance of transistors which have a relationship with the transistors’ port voltage, we use measured dc voltage from the LNA to estimate its NF and S11. Also, we choose the LNA’s bias current and the ratio of the current mirror providing current for PMOS bias transistor as tuning knobs to adjust the LNA’s S11 and NF. To realize non-intrusive self-calibration, measured dc voltage and currents from dummy circuits are used to estimate the LNA’s S11 and NF. Different dummy sizes are used, and we find that there is a trade-off between dummy size and calibration results. The circuits are implemented in 22-nm ultra-low leakage CMOS technology and the calibration algorithm was implemented with Matlab. The simulation results show that a 15.5% yield improvement could be obtained when dc voltages are measured from the primary LNA with current from a 1/2 scaled current mirror and a yield improvement from 11% to 16.5% could be obtained when dc voltages and currents are measured from different sets of dummy circuits.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130376383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651721
Xiaohong Peng, Xuefeng Li, Shuqin Geng, Jie Wang, Fengjun Nie
This paper studies FPGA image processing, and proposes two methods to improve FPGA image processing acceleration, data reorganization and multi-processing modules. Both methods use ARM as the data control module. Data reorganization improves the transmission efficiency of the AXI bus by merging data, and the multiprocessing module improves the parallelism of the processing system by adding processing modules. Finally, these two methods are used to realize the low- light image enhancement algorithm combining wavelet transform and Retinex algorithm, and compared with the processing effect on matlab, and good results are obtained.
{"title":"Low-light image enhancement based on FPGA","authors":"Xiaohong Peng, Xuefeng Li, Shuqin Geng, Jie Wang, Fengjun Nie","doi":"10.1109/asid52932.2021.9651721","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651721","url":null,"abstract":"This paper studies FPGA image processing, and proposes two methods to improve FPGA image processing acceleration, data reorganization and multi-processing modules. Both methods use ARM as the data control module. Data reorganization improves the transmission efficiency of the AXI bus by merging data, and the multiprocessing module improves the parallelism of the processing system by adding processing modules. Finally, these two methods are used to realize the low- light image enhancement algorithm combining wavelet transform and Retinex algorithm, and compared with the processing effect on matlab, and good results are obtained.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129479120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651681
Ruiqian Ye, Peng Zheng, Yun Gao, Chun Lin, Zili Zhang, Fanchang Meng
The coplanarity of the bump height is the guarantee of packaging quality. Optical triangulation is a widely used method to measure the bump height. However, it is not easy to accurately measure the bump height due to its small size, curved and highly reflective surface. In order to solve the problem of poor stability in triangulation measurement when using light strip center extraction, we analyzed the error reasons in a white light triangulation based bump height measurement. Then, an improved gray centroid method was applied to extract the light strip center on the base wafer and the light spot on the bump top. Next, the calibration results was combined to calculate the initial bump height. Finally, two features of the light strip and light spot were detected to train a multilayer perceptron to obtain an intelligent compensation for the bump height. It was proved that the standard deviation and the extreme difference of bump height are reduced to at least 1/2 after using our compensation method. The average standard deviation was reduced from 0.651um to 0.281um, as well as the average extreme difference was reduced from 1.790um to 0.689um. The result can meet the requirements of most of the bump package.
{"title":"An Intelligent Error Compensation Method for Height Measurement of Bump Package","authors":"Ruiqian Ye, Peng Zheng, Yun Gao, Chun Lin, Zili Zhang, Fanchang Meng","doi":"10.1109/asid52932.2021.9651681","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651681","url":null,"abstract":"The coplanarity of the bump height is the guarantee of packaging quality. Optical triangulation is a widely used method to measure the bump height. However, it is not easy to accurately measure the bump height due to its small size, curved and highly reflective surface. In order to solve the problem of poor stability in triangulation measurement when using light strip center extraction, we analyzed the error reasons in a white light triangulation based bump height measurement. Then, an improved gray centroid method was applied to extract the light strip center on the base wafer and the light spot on the bump top. Next, the calibration results was combined to calculate the initial bump height. Finally, two features of the light strip and light spot were detected to train a multilayer perceptron to obtain an intelligent compensation for the bump height. It was proved that the standard deviation and the extreme difference of bump height are reduced to at least 1/2 after using our compensation method. The average standard deviation was reduced from 0.651um to 0.281um, as well as the average extreme difference was reduced from 1.790um to 0.689um. The result can meet the requirements of most of the bump package.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129967560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651698
Ting Li, Yabo Ni, Yong Zhang, Chao Chen
This paper presents an LMS(Least Mean Square) based nonlinear error extraction and calibration algorithm for pipeline ADC(analog-to-digital converter ). In this algorithm, the nonlinear error of ADC is treated as the internal error of each stage and the gain error between stages. When testing, a known high quality signal is sent to the ADC and the error parameters are calculated using the digital output codes. Compared to traditional histogram testing, this method using much fewer samples. During calibration, the method proposed in this paper is used to eliminate the nonlinear error digitally from the digital output code of ADC. Only 4000 samples were used, the non linearity of the 14-bit high speed high resolution pipeline ADC can be extracted and removed so that the ADC can achieve less than 1.5 least significant bit (LSB) integral nonlinearity (INL) which is reduced by 78%. The measurement results illustrates the effectiveness of the method, after calibration, the ADC signal to noise and distortion ratio (SINAD) is improved from 65dBFS to 69dBFS and the spurious-free dynamic range (SFDR) is improved from 75dBFS to 92dBFS. The algorithm proposed in this paper is especially suitable for multistage ADC and can also be used for all types of ADCs.
{"title":"LMS Based Ultra-Fast Non Linearity Test and Calibration Method for High-speed and High-Resolution ADC","authors":"Ting Li, Yabo Ni, Yong Zhang, Chao Chen","doi":"10.1109/asid52932.2021.9651698","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651698","url":null,"abstract":"This paper presents an LMS(Least Mean Square) based nonlinear error extraction and calibration algorithm for pipeline ADC(analog-to-digital converter ). In this algorithm, the nonlinear error of ADC is treated as the internal error of each stage and the gain error between stages. When testing, a known high quality signal is sent to the ADC and the error parameters are calculated using the digital output codes. Compared to traditional histogram testing, this method using much fewer samples. During calibration, the method proposed in this paper is used to eliminate the nonlinear error digitally from the digital output code of ADC. Only 4000 samples were used, the non linearity of the 14-bit high speed high resolution pipeline ADC can be extracted and removed so that the ADC can achieve less than 1.5 least significant bit (LSB) integral nonlinearity (INL) which is reduced by 78%. The measurement results illustrates the effectiveness of the method, after calibration, the ADC signal to noise and distortion ratio (SINAD) is improved from 65dBFS to 69dBFS and the spurious-free dynamic range (SFDR) is improved from 75dBFS to 92dBFS. The algorithm proposed in this paper is especially suitable for multistage ADC and can also be used for all types of ADCs.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130651584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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