Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651693
Xin Zhou, Liji Wu, Xiangmin Zhang
As the computing power of quantum computers continues to improve, the security of the mathematical problems on current-used cryptographic algorithm are facing more and more serious challenge. It is necessary to formulate the standard of post-quantum cryptographic algorithm. Classic McEliece is one of the 7 candidates entering the Round 3 of NIST PQC contest. In the decryption module of Classic McEliece, H module uses the SHA-3 algorithm. As a new generation of hash algorithm, SHA-3 algorithm uses the Keccak sponge function, which has the advantages of higher speed, higher throughput and stronger security. Keccak truly realizes the processing of input information of any length, and can also generate hash values of any length. In the future, SHA-3 will be applied to more fields, so the high-performance and flexible implementation of the SHA-3 is especially important. This paper analyzed the four SHA-3 algorithms, and integrated the four algorithm standards into one implementation for Classic McEliece. The Xilinx Zynq-7000 series FPGA is chosen as the implementation and verification platform, and the performance are compared with the algorithm implementation of Keccak official team.
{"title":"Hardware Design of SHA-3 for PQC Classic McEliece","authors":"Xin Zhou, Liji Wu, Xiangmin Zhang","doi":"10.1109/asid52932.2021.9651693","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651693","url":null,"abstract":"As the computing power of quantum computers continues to improve, the security of the mathematical problems on current-used cryptographic algorithm are facing more and more serious challenge. It is necessary to formulate the standard of post-quantum cryptographic algorithm. Classic McEliece is one of the 7 candidates entering the Round 3 of NIST PQC contest. In the decryption module of Classic McEliece, H module uses the SHA-3 algorithm. As a new generation of hash algorithm, SHA-3 algorithm uses the Keccak sponge function, which has the advantages of higher speed, higher throughput and stronger security. Keccak truly realizes the processing of input information of any length, and can also generate hash values of any length. In the future, SHA-3 will be applied to more fields, so the high-performance and flexible implementation of the SHA-3 is especially important. This paper analyzed the four SHA-3 algorithms, and integrated the four algorithm standards into one implementation for Classic McEliece. The Xilinx Zynq-7000 series FPGA is chosen as the implementation and verification platform, and the performance are compared with the algorithm implementation of Keccak official team.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120844742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651728
Luyao Ma, Lijun Zhang
Both polar code and Low-Density Parity-Check (LDPC) code have been adopted in 3GPP eMBB scenario. Some scholars have proposed a serial concatenation structure combining these two codes. However, the inner code needs to add redundant bits to protect the redundant bits of the outer code in the serial concatenation. In this paper, we propose a parallel concatenation code combining polar code and LDPC code on the AWGN channel, which does not distinguish the inner code from the outer code. In the proposed concatenated structure, the BP algorithm is used to decode polar code, and the output soft information of BP decoder is logarithmically processed before LDPC decoding. According to the simulation results, compared with the serial concatenated code with the same code rate and code length, the parallel concatenated code has better BER(Bit-Error-Rate) performance.
{"title":"Parallel Concatenated Code Combining Polar Code and LDPC Code on AWGN Channel","authors":"Luyao Ma, Lijun Zhang","doi":"10.1109/asid52932.2021.9651728","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651728","url":null,"abstract":"Both polar code and Low-Density Parity-Check (LDPC) code have been adopted in 3GPP eMBB scenario. Some scholars have proposed a serial concatenation structure combining these two codes. However, the inner code needs to add redundant bits to protect the redundant bits of the outer code in the serial concatenation. In this paper, we propose a parallel concatenation code combining polar code and LDPC code on the AWGN channel, which does not distinguish the inner code from the outer code. In the proposed concatenated structure, the BP algorithm is used to decode polar code, and the output soft information of BP decoder is logarithmically processed before LDPC decoding. According to the simulation results, compared with the serial concatenated code with the same code rate and code length, the parallel concatenated code has better BER(Bit-Error-Rate) performance.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114863298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651719
Yanbu Hu, C. Shao, Huiyun Li
In recent years, with the rapid development of DNN, the algorithm complexity in a series of fields such as computer vision and natural language processing is increasing rapidly. FPGA-based DNN accelerators have demonstrated superior flexibility and performance, with higher energy efficiency compared to high-performance devices such as GPU. However, the computing resources of a single FPGA are limited and it is difficult to flexibly meet the requirements of high throughput and high energy efficiency of different computing scales. Therefore, this paper proposes a DNN implementation method based on the scalable heterogeneous FPGA cluster to adapt to different tasks and achieve high throughput and energy efficiency. Firstly, the method divides a single enormous task into multiple modules and running each module on different FPGA as the pipeline structure between multiple boards. Secondly, a task deployment method based on dichotomy is proposed to maximize the balance of task execution time of different pipeline stages to improve throughput and energy efficiency. Thirdly, optimize DNN computing module according to the relationship between computing power and bandwidth, and improve energy efficiency by reducing waste of ineffective resources and improving resource utilization. The experiment results on Alexnet and VGG-16 demonstrate that we use Zynq 7035 cluster can at most achieves ×25.23 energy efficiency of optimized AMD AIO processor. Compared with previous works of single FPGA and FPGA cluster, the energy efficiency is improved by 59.5% and 18.8%, respectively.
{"title":"Energy-Efficient Deep Neural Networks Implementation on a Scalable Heterogeneous FPGA Cluster","authors":"Yanbu Hu, C. Shao, Huiyun Li","doi":"10.1109/asid52932.2021.9651719","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651719","url":null,"abstract":"In recent years, with the rapid development of DNN, the algorithm complexity in a series of fields such as computer vision and natural language processing is increasing rapidly. FPGA-based DNN accelerators have demonstrated superior flexibility and performance, with higher energy efficiency compared to high-performance devices such as GPU. However, the computing resources of a single FPGA are limited and it is difficult to flexibly meet the requirements of high throughput and high energy efficiency of different computing scales. Therefore, this paper proposes a DNN implementation method based on the scalable heterogeneous FPGA cluster to adapt to different tasks and achieve high throughput and energy efficiency. Firstly, the method divides a single enormous task into multiple modules and running each module on different FPGA as the pipeline structure between multiple boards. Secondly, a task deployment method based on dichotomy is proposed to maximize the balance of task execution time of different pipeline stages to improve throughput and energy efficiency. Thirdly, optimize DNN computing module according to the relationship between computing power and bandwidth, and improve energy efficiency by reducing waste of ineffective resources and improving resource utilization. The experiment results on Alexnet and VGG-16 demonstrate that we use Zynq 7035 cluster can at most achieves ×25.23 energy efficiency of optimized AMD AIO processor. Compared with previous works of single FPGA and FPGA cluster, the energy efficiency is improved by 59.5% and 18.8%, respectively.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125572861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651725
{"title":"[ASID 2021 Copyright notice]","authors":"","doi":"10.1109/asid52932.2021.9651725","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651725","url":null,"abstract":"","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126398987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651485
Zhenyu Wang, Junping Wang, Nan Wang
Moving object detection is an important branch of video image processing technology. It is widely used in military, transportation, aviation and other fields. However, there are still gaps in the field of teaching. In this paper, moving object detection is applied to the field of teaching video. The train algorithm is designed to mark the unconnected areas. Then a moving object detection and marking system is realized to assist teachers in managing the classroom. Firstly, the system uses the frame difference method to detect the moving object. Secondly, the custom threshold is used for binarization. Then the median filter and open operation is used to denoise and morphological processing. After that, the obtained unconnected region is segmented and located by the processing of the train algorithm. Finally, the moving region greater than the threshold is marked according to the set pixels and threshold in the block. The system results show the effectiveness of the algorithm and the accuracy of moving object detection in teaching video.
{"title":"Moving Object Detection and Marking Based on Frame Difference and Train Algorithm for Teaching Video","authors":"Zhenyu Wang, Junping Wang, Nan Wang","doi":"10.1109/asid52932.2021.9651485","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651485","url":null,"abstract":"Moving object detection is an important branch of video image processing technology. It is widely used in military, transportation, aviation and other fields. However, there are still gaps in the field of teaching. In this paper, moving object detection is applied to the field of teaching video. The train algorithm is designed to mark the unconnected areas. Then a moving object detection and marking system is realized to assist teachers in managing the classroom. Firstly, the system uses the frame difference method to detect the moving object. Secondly, the custom threshold is used for binarization. Then the median filter and open operation is used to denoise and morphological processing. After that, the obtained unconnected region is segmented and located by the processing of the train algorithm. Finally, the moving region greater than the threshold is marked according to the set pixels and threshold in the block. The system results show the effectiveness of the algorithm and the accuracy of moving object detection in teaching video.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128312017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651705
Guang-Chong Zhu, Deyuan Chen, Can Zhang, Yongzhi Qi
Based on the structure of turbo-polar codes, a secure symmetric encryption scheme is proposed to enhance information transmission security in this paper. This scheme utilizes interleaving at information bits and puncturing at parity bits for several times in the encoder. Correspondingly, we need to do the converse interleaving and fill zeros accurately at punctured position. The way of interleaving and puncturing is controlled by the private key of symmetric encryption, making sure the security of the system. The security of Secure Turbo-Polar Codes (STPC) is analyzed at the end of this paper. Simulation results are given to shown that the performance and complexity of Turbo-Polar Codes have little change after symmetric encryption. We also investigate in depth the influence of different remaining parity bit ratios on Frame Error Rate (FER). At low Signal to Noise Rate (SNR), we find it have about 0.6dB advantage when remaining parity bit ratio is between 1/20 and 1/4.
{"title":"Secure Turbo-Polar Codes Information Transmission on Wireless Channel","authors":"Guang-Chong Zhu, Deyuan Chen, Can Zhang, Yongzhi Qi","doi":"10.1109/asid52932.2021.9651705","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651705","url":null,"abstract":"Based on the structure of turbo-polar codes, a secure symmetric encryption scheme is proposed to enhance information transmission security in this paper. This scheme utilizes interleaving at information bits and puncturing at parity bits for several times in the encoder. Correspondingly, we need to do the converse interleaving and fill zeros accurately at punctured position. The way of interleaving and puncturing is controlled by the private key of symmetric encryption, making sure the security of the system. The security of Secure Turbo-Polar Codes (STPC) is analyzed at the end of this paper. Simulation results are given to shown that the performance and complexity of Turbo-Polar Codes have little change after symmetric encryption. We also investigate in depth the influence of different remaining parity bit ratios on Frame Error Rate (FER). At low Signal to Noise Rate (SNR), we find it have about 0.6dB advantage when remaining parity bit ratio is between 1/20 and 1/4.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651699
Yanian Shao, Xuefei Bai, Zhe Yang
In this paper, two LC-DCO designs with three-stage frequency tuning circuits in 40-nm CMOS technology are presented, and the post-layout simulations are performed. The first design is a small-area cross-coupling LC-DCO suitable for low-cost applications. Its frequency range is 15.56-24.57 GHz, and the average power is 7.1 mW. When the output frequency is 24.57 GHz, the phase noise is –101.47 dBc/Hz at 1-MHz offset, and the FoM is –180.8 dBc/Hz. The second design is a low-power complementary differential LC-DCO suitable for low-power applications. Its frequency range is 15.7-23.0 GHz, and the average power is 1.76 mW. When the output frequency is 23 GHz, the phase noise is –102.12 dBc/Hz at 1-MHz offset, and the FoM is –186.9 dBc/Hz.
{"title":"Designs of 16-to-24-GHz Inductor-Capacitor Digitally-Controlled Oscillators in 40-nm CMOS","authors":"Yanian Shao, Xuefei Bai, Zhe Yang","doi":"10.1109/asid52932.2021.9651699","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651699","url":null,"abstract":"In this paper, two LC-DCO designs with three-stage frequency tuning circuits in 40-nm CMOS technology are presented, and the post-layout simulations are performed. The first design is a small-area cross-coupling LC-DCO suitable for low-cost applications. Its frequency range is 15.56-24.57 GHz, and the average power is 7.1 mW. When the output frequency is 24.57 GHz, the phase noise is –101.47 dBc/Hz at 1-MHz offset, and the FoM is –180.8 dBc/Hz. The second design is a low-power complementary differential LC-DCO suitable for low-power applications. Its frequency range is 15.7-23.0 GHz, and the average power is 1.76 mW. When the output frequency is 23 GHz, the phase noise is –102.12 dBc/Hz at 1-MHz offset, and the FoM is –186.9 dBc/Hz.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128545079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651674
Yamei Xu, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yan Liang, Ziteng Cai
A novel Active Inductor (AI) is presented that its inductance values L and the peak values of quality factor Q can be kept almost constant at different frequencies, and the Q factor can be independently tuned with respect to the inductance value L. The external voltage tuning terminal of the positive transconductor in the feedback loop of positive and negative transconductors building block is configured to compensate for the variation of inductance with frequency. And the external voltages of two building blocks, namely the multi-regulated cascode structure circuit and RC feedback network are jointly tuned to compensate for the variation of Q value with frequency. In addition, the variable capacitance in the RC feedback network is employed to tune the Q factor without affecting the inductance value, thus the independent tuning of the Q with respect to the inductance value is realized. Based on TSMC 0.18ȝm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that under the frequencies of 0.75GHz, 1.85GHz, 3.00GHz, 4.10GHz, the novel AI achieves the peak Q values of 999, 1003, 999 and 1001 respectively with the peak Q variation of only 0.40%. At the same time, the corresponding inductance values are 316.0nH, 310.2nH, 309.6nH and 303.1nH respectively with the inductance variation of only 4.17%. Moreover, the Q factor can be tuned from 610 to 1500 at each of the above four frequencies with negligible variation of inductance.
{"title":"A Novel Active Inductor with Almost Simultaneously Constant L and Peak Q at Different Frequencies and Independent Q Tunability","authors":"Yamei Xu, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yan Liang, Ziteng Cai","doi":"10.1109/asid52932.2021.9651674","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651674","url":null,"abstract":"A novel Active Inductor (AI) is presented that its inductance values L and the peak values of quality factor Q can be kept almost constant at different frequencies, and the Q factor can be independently tuned with respect to the inductance value L. The external voltage tuning terminal of the positive transconductor in the feedback loop of positive and negative transconductors building block is configured to compensate for the variation of inductance with frequency. And the external voltages of two building blocks, namely the multi-regulated cascode structure circuit and RC feedback network are jointly tuned to compensate for the variation of Q value with frequency. In addition, the variable capacitance in the RC feedback network is employed to tune the Q factor without affecting the inductance value, thus the independent tuning of the Q with respect to the inductance value is realized. Based on TSMC 0.18ȝm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that under the frequencies of 0.75GHz, 1.85GHz, 3.00GHz, 4.10GHz, the novel AI achieves the peak Q values of 999, 1003, 999 and 1001 respectively with the peak Q variation of only 0.40%. At the same time, the corresponding inductance values are 316.0nH, 310.2nH, 309.6nH and 303.1nH respectively with the inductance variation of only 4.17%. Moreover, the Q factor can be tuned from 610 to 1500 at each of the above four frequencies with negligible variation of inductance.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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