This paper implements porting RT-Thread OS to RISC-V based AnnikaSoC MCU, whose work includes modifying linker script, writing startup file, adapting interrupt and exception interface, porting UART and Timer drivers, adapting thread context switch interface and BSP entry. We did variety of tests after porting, whose result shows that all parts of RT-Thread our porting work involves can work properly.
{"title":"Porting RT-Thread to AnnikaSoC","authors":"Zhirui Li, Jian Li, Yunrui Zhang, Jianyang Zhou, Zichao Guo","doi":"10.1109/asid52932.2021.9651703","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651703","url":null,"abstract":"This paper implements porting RT-Thread OS to RISC-V based AnnikaSoC MCU, whose work includes modifying linker script, writing startup file, adapting interrupt and exception interface, porting UART and Timer drivers, adapting thread context switch interface and BSP entry. We did variety of tests after porting, whose result shows that all parts of RT-Thread our porting work involves can work properly.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126071313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In modern information society, data security has become more and more critical. Homomorphic encryption is one of the best choice to solve the security problem of user data on the server because of its unique characteristics of allowing operations in the ciphertext. A homomorphic encryption scheme based on R-LWE is a hotspot in research and application. Polynomial multiplication in ℤp[x]/(xn+1) has brought significant attention recently. The key to accelerating the FV homomorphic encryption scheme is to accelerate the polynomial multiplication [1]. Traditional accelerators use the NTT algorithm. However, the conventional NTT scheme will cause the expansion of the number of terms after the operation, requiring additional modular reduction calculations. This paper presents a hardware accelerator for polynomial multiplication based on Discrete Galois Transform. Compared with traditional NTT, DGT cuts the length of the polynomial by half [2]. At the same time, a negative loop convolution is added to avoid additional modular reduction calculations. We designs a DGT-based hardware accelerator for polynomial multiplication on the ring. At the same time, a particular improvement is made to the DGT algorithm to make it friendly to hardware design and save some cycles. Experimental results show that our accelerator via DGT can effectively improve the multiplication speed of polynomials.
{"title":"A Polynomial Multiplication Accelerator for Homomorphic Encryption using DGT","authors":"Jigang Yang, Zhenmin Li, Jingwei Ren, Xiaolei Wang, Wei Ni, Gaoming Du","doi":"10.1109/asid52932.2021.9651679","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651679","url":null,"abstract":"In modern information society, data security has become more and more critical. Homomorphic encryption is one of the best choice to solve the security problem of user data on the server because of its unique characteristics of allowing operations in the ciphertext. A homomorphic encryption scheme based on R-LWE is a hotspot in research and application. Polynomial multiplication in ℤp[x]/(xn+1) has brought significant attention recently. The key to accelerating the FV homomorphic encryption scheme is to accelerate the polynomial multiplication [1]. Traditional accelerators use the NTT algorithm. However, the conventional NTT scheme will cause the expansion of the number of terms after the operation, requiring additional modular reduction calculations. This paper presents a hardware accelerator for polynomial multiplication based on Discrete Galois Transform. Compared with traditional NTT, DGT cuts the length of the polynomial by half [2]. At the same time, a negative loop convolution is added to avoid additional modular reduction calculations. We designs a DGT-based hardware accelerator for polynomial multiplication on the ring. At the same time, a particular improvement is made to the DGT algorithm to make it friendly to hardware design and save some cycles. Experimental results show that our accelerator via DGT can effectively improve the multiplication speed of polynomials.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130437178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651686
Li Yidan, Chen Yanli, Chen Runze, Yin Lan, Ruan Fangming
Encryption traffic classification technology classifies traffic data according to different applications or different traffic types. It is one of the most important technologies to monitor network traffic security and collect network traffic information. In view of this, this paper proposes an encrypted traffic classification method based on the ResNeXt network. Ethernet headers and payloads in the traffic are removed in data preprocessing, and then the improved and simplified ResNeXt model is used to identify encrypted traffic data. The preprocessing method can greatly reduce the size of input data, save time, and achieve higher accuracy. The experimental results show that the classification accuracy of the proposed method for 12 types of encrypted traffic in "ICSX VPN-NonVPN" data set is 98.58%, and the average accuracy rate, recall rate and F1 score are 98.70%, 98.49%, and 0.9859, respectively.
{"title":"An Encryption Traffic Classification Method Based on ResNeXt","authors":"Li Yidan, Chen Yanli, Chen Runze, Yin Lan, Ruan Fangming","doi":"10.1109/asid52932.2021.9651686","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651686","url":null,"abstract":"Encryption traffic classification technology classifies traffic data according to different applications or different traffic types. It is one of the most important technologies to monitor network traffic security and collect network traffic information. In view of this, this paper proposes an encrypted traffic classification method based on the ResNeXt network. Ethernet headers and payloads in the traffic are removed in data preprocessing, and then the improved and simplified ResNeXt model is used to identify encrypted traffic data. The preprocessing method can greatly reduce the size of input data, save time, and achieve higher accuracy. The experimental results show that the classification accuracy of the proposed method for 12 types of encrypted traffic in \"ICSX VPN-NonVPN\" data set is 98.58%, and the average accuracy rate, recall rate and F1 score are 98.70%, 98.49%, and 0.9859, respectively.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651491
{"title":"[ASID 2021 Front matter]","authors":"","doi":"10.1109/asid52932.2021.9651491","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651491","url":null,"abstract":"","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129940164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651673
Yan Liang, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yamei Xu, Ziteng Cai
In this paper, a novel Active Inductor (AI) with high quality factor Q, high inductance L and mutually independent tuning characteristic is presented. It is mainly composed of three circuit blocks, and each circuit block is configured with an external voltage tunable terminal respectively. The high Q factor is achieved through the multiple MOSTETs negative resistance generation network connected between the positive and negative transconductors. Meanwhile, the high inductance is realized by the MOSFET variable capacitance block and the negative transconductor of the gyrator-C network in parallel. Additionally, the mutually independent tuning of Q and L each other is accomplished by coordinately varying three external tunable terminal voltages in three circuit blocks. Based on TSMC 0.18μm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that at 4.8GHz, the peak Q factor can reach high up to 4086.06, and the inductance is as high as 273.62nH; at 4.5GHz, 4.8GHz and 5.1GHz, the Q value can be tuned greatly from 341.90 to 433.80, from 800.11 to 4086.06 and from 210.23 to 305.71 respectively, whereas the variation of L value is only 0.59%, 0.66% and 0.73%; Furthermore, under 4GHz, 4.8GHz and 5.4GHz, the L value can be tuned noticeably from 220.95nH to 247.72nH, from 298.00nH to 344.90nH and from 418.88nH to 511.34nH respectively, while the variation of the Q value is only 0.54%, 0.65% and 0.83%.
{"title":"A Novel Active Inductor with High Q Factor and Inductance and Mutually Independent Tuning Characteristic","authors":"Yan Liang, Wanrong Zhang, Hongyun Xie, D. Jin, W. Na, Yamei Xu, Ziteng Cai","doi":"10.1109/asid52932.2021.9651673","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651673","url":null,"abstract":"In this paper, a novel Active Inductor (AI) with high quality factor Q, high inductance L and mutually independent tuning characteristic is presented. It is mainly composed of three circuit blocks, and each circuit block is configured with an external voltage tunable terminal respectively. The high Q factor is achieved through the multiple MOSTETs negative resistance generation network connected between the positive and negative transconductors. Meanwhile, the high inductance is realized by the MOSFET variable capacitance block and the negative transconductor of the gyrator-C network in parallel. Additionally, the mutually independent tuning of Q and L each other is accomplished by coordinately varying three external tunable terminal voltages in three circuit blocks. Based on TSMC 0.18μm CMOS process, the novel AI is verified by Advanced Design System (ADS). The results show that at 4.8GHz, the peak Q factor can reach high up to 4086.06, and the inductance is as high as 273.62nH; at 4.5GHz, 4.8GHz and 5.1GHz, the Q value can be tuned greatly from 341.90 to 433.80, from 800.11 to 4086.06 and from 210.23 to 305.71 respectively, whereas the variation of L value is only 0.59%, 0.66% and 0.73%; Furthermore, under 4GHz, 4.8GHz and 5.4GHz, the L value can be tuned noticeably from 220.95nH to 247.72nH, from 298.00nH to 344.90nH and from 418.88nH to 511.34nH respectively, while the variation of the Q value is only 0.54%, 0.65% and 0.83%.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125747507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651711
Jianyang Cui, Ying Cai, Shaocheng Yang, Yu Zhang
Vehicle Ad Hoc Networks (VANETs) leverage wireless communication technology to enable vehicles to continuously exchange entertainment information, traffic conditions, weather information, etc., so as to enhance traffic safety management and provide drivers with a safe and comfortable driving environment. However, due to the open access and wireless communication characteristics of VANETs, malicious node attacks may cause privacy leakage. Therefore, privacy protection is crucial to the research of VANETs. We introduced the privacy threats in VANETs from the perspective of privacy attacks in this paper. Then, we overview the existing privacy-preserving schemes in VANETs, and divided the schemes into three categories, including location privacy-preserving schemes, identity privacy-preserving schemes and data privacy¬preserving schemes according to the different types of attacks they resist. Finally, we point out some challenge for the design of Privacy-preserving Schemes forVANETs.
{"title":"A Survey on Privacy-preserving Schemes for Vehicular Ad Hoc Networks","authors":"Jianyang Cui, Ying Cai, Shaocheng Yang, Yu Zhang","doi":"10.1109/asid52932.2021.9651711","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651711","url":null,"abstract":"Vehicle Ad Hoc Networks (VANETs) leverage wireless communication technology to enable vehicles to continuously exchange entertainment information, traffic conditions, weather information, etc., so as to enhance traffic safety management and provide drivers with a safe and comfortable driving environment. However, due to the open access and wireless communication characteristics of VANETs, malicious node attacks may cause privacy leakage. Therefore, privacy protection is crucial to the research of VANETs. We introduced the privacy threats in VANETs from the perspective of privacy attacks in this paper. Then, we overview the existing privacy-preserving schemes in VANETs, and divided the schemes into three categories, including location privacy-preserving schemes, identity privacy-preserving schemes and data privacy¬preserving schemes according to the different types of attacks they resist. Finally, we point out some challenge for the design of Privacy-preserving Schemes forVANETs.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133944011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651717
Ze-Xian Chen, Zhiquan Wang, Guo Peng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu
In this paper, an FPGA chip of Cyclone II is employed to investigate the delay characteristics of two TDC delay chains. In this study, the delay elements implemented by the L cell with different input channels were investigated by timing analysis in Chip Planner and by gate level simulation by ModelSim. According to our results, the time resolution of a single delay path can be 580 ps for LUTs configured with the D channel input. For the delay chain with two paths, the time resolution was about 490 ps with a combination of C- and D-channel assignments. It’s promising to further refine the time resolution of a TDC even in a Cyclone II chip.
本文采用Cyclone II FPGA芯片对两种TDC延迟链的延迟特性进行了研究。在本研究中，通过Chip Planner中的时序分析和ModelSim的门级仿真，研究了L cell在不同输入通道下实现的延迟元件。根据我们的结果，对于配置了D通道输入的lut，单个延迟路径的时间分辨率可以达到580 ps。对于具有两条路径的延迟链，结合C通道和d通道分配，时间分辨率约为490 ps。即使在Cyclone II芯片中，也有望进一步改进TDC的时间分辨率。
{"title":"Delay Cells for the Time-to-Digital Converter Implemented in FPGA","authors":"Ze-Xian Chen, Zhiquan Wang, Guo Peng, M. Shiau, Hong-Chong Wu, Ching-Hwa Cheng, Don-Gey Liu","doi":"10.1109/asid52932.2021.9651717","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651717","url":null,"abstract":"In this paper, an FPGA chip of Cyclone II is employed to investigate the delay characteristics of two TDC delay chains. In this study, the delay elements implemented by the L cell with different input channels were investigated by timing analysis in Chip Planner and by gate level simulation by ModelSim. According to our results, the time resolution of a single delay path can be 580 ps for LUTs configured with the D channel input. For the delay chain with two paths, the time resolution was about 490 ps with a combination of C- and D-channel assignments. It’s promising to further refine the time resolution of a TDC even in a Cyclone II chip.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651483
Arthur Silitonga, Yigit Kiyak, J. Becker
Asymmetric cryptography is frequently used for key exchanges and signatures in today's secure data transmissions, for instance, Elliptic Curve Cryptography (ECC). This paper describes our ECC-based cryptographic algorithms implementation on a low-end All Programmable System-on-Chip (APSoC) imposed upon its Dynamic Partial Reconfiguration (DPR) due to the target platform's limited resource. Our asymmetric cryptosystem is based on elliptic curves defined over prime fields and utilizes a dynamic change of multiple key lengths. High-Level Synthesis (HLS) is the basis of our Design Space Exploration (DSE) and hardware implementation. The design is adapted to be algorithmically robust against numerous existing types of attacks. Referring to various possible key lengths, the provided modes are 192, 256, 384, and 512 bits during the design time. An optimized result in design time shows an implementation of the key length of 512 bits is inapplicable due to FPGA resources' plethora in our targeted APSoC. An optimized design is implemented and compared to particularly related works. Indeed, DPR usage brings an advantage that resources can be reused for ECC with various key lengths, other implementable crypto algorithms, or non-crypto designs.
{"title":"HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)","authors":"Arthur Silitonga, Yigit Kiyak, J. Becker","doi":"10.1109/asid52932.2021.9651483","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651483","url":null,"abstract":"Asymmetric cryptography is frequently used for key exchanges and signatures in today's secure data transmissions, for instance, Elliptic Curve Cryptography (ECC). This paper describes our ECC-based cryptographic algorithms implementation on a low-end All Programmable System-on-Chip (APSoC) imposed upon its Dynamic Partial Reconfiguration (DPR) due to the target platform's limited resource. Our asymmetric cryptosystem is based on elliptic curves defined over prime fields and utilizes a dynamic change of multiple key lengths. High-Level Synthesis (HLS) is the basis of our Design Space Exploration (DSE) and hardware implementation. The design is adapted to be algorithmically robust against numerous existing types of attacks. Referring to various possible key lengths, the provided modes are 192, 256, 384, and 512 bits during the design time. An optimized result in design time shows an implementation of the key length of 512 bits is inapplicable due to FPGA resources' plethora in our targeted APSoC. An optimized design is implemented and compared to particularly related works. Indeed, DPR usage brings an advantage that resources can be reused for ECC with various key lengths, other implementable crypto algorithms, or non-crypto designs.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128556698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651675
Mijing Sun, Li Xu, Zhenmin Li, Wei Ni, Gaoming Du, Xiaolei Wang, Yong-Sheng Yin
The rapid development of machine learning techniques, especially deep learning, has led to a drastic increase of research attention for domain-specific processors such as deep neural networks (DNN) accelerators. The surge in scale and complexity of DNN accelerators poses great design challenge. Simulators with high simulation speed and accurate performance evaluation capability are pivotal for DNN accelerator design. A number of simulators targeting DNN accelerators have emerged, yet they are not summarized and classified. This paper presents a systematic review of state-of-the-art DNN accelerator simulator from the perspective of simulator performance, target platform, evaluation indicators, input/output characteristics, and implementation details.
{"title":"Simulators for Deep Neural Network Accelerator Design and Analysis: A Brief Review","authors":"Mijing Sun, Li Xu, Zhenmin Li, Wei Ni, Gaoming Du, Xiaolei Wang, Yong-Sheng Yin","doi":"10.1109/asid52932.2021.9651675","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651675","url":null,"abstract":"The rapid development of machine learning techniques, especially deep learning, has led to a drastic increase of research attention for domain-specific processors such as deep neural networks (DNN) accelerators. The surge in scale and complexity of DNN accelerators poses great design challenge. Simulators with high simulation speed and accurate performance evaluation capability are pivotal for DNN accelerator design. A number of simulators targeting DNN accelerators have emerged, yet they are not summarized and classified. This paper presents a systematic review of state-of-the-art DNN accelerator simulator from the perspective of simulator performance, target platform, evaluation indicators, input/output characteristics, and implementation details.","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133819417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-29DOI: 10.1109/asid52932.2021.9651724
Chen Runze, Ruan Fangming, Li Yidan, Yin Lan, Chen Yanli
DDoS attacks have been one of the major threats to the Internet since their emergence. With the rapid development of the Internet, the number of network users is increasing rapidly. Thus, the existing network based on TCPIP protocol is increasingly complex and rigid; it is difficult to add new functions, which greatly restricts the development of network technology. The emergence of SDN provides a feasible solution to the severe problems faced by the existing network. At the same time, it also provides a new technology to solve the problem of DDoS attack in the traditional network. In this paper, a simple SDN architecture was built on the network simulation platform of Mininet. The host launched ping flood attack, and the controller was used to control the delivery flow meter to suppress DDoS attack traffic, which achieved a good defense effect. Keywords–Network security; DDoS attack; Software defined network; The controller
{"title":"A Simple DDoS Defense Method Based SDN","authors":"Chen Runze, Ruan Fangming, Li Yidan, Yin Lan, Chen Yanli","doi":"10.1109/asid52932.2021.9651724","DOIUrl":"https://doi.org/10.1109/asid52932.2021.9651724","url":null,"abstract":"DDoS attacks have been one of the major threats to the Internet since their emergence. With the rapid development of the Internet, the number of network users is increasing rapidly. Thus, the existing network based on TCPIP protocol is increasingly complex and rigid; it is difficult to add new functions, which greatly restricts the development of network technology. The emergence of SDN provides a feasible solution to the severe problems faced by the existing network. At the same time, it also provides a new technology to solve the problem of DDoS attack in the traditional network. In this paper, a simple SDN architecture was built on the network simulation platform of Mininet. The host launched ping flood attack, and the controller was used to control the delivery flow meter to suppress DDoS attack traffic, which achieved a good defense effect. Keywords–Network security; DDoS attack; Software defined network; The controller","PeriodicalId":150884,"journal":{"name":"2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134322864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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