Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419836
Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan
Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0–1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.
{"title":"Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating","authors":"Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan","doi":"10.1109/ASPDAC.2010.5419836","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419836","url":null,"abstract":"Due to clock gating, the PMOS transistors in the clock tree often have different active probabilities, which lead to different NBTI delay degradations. To ensure that the clock skew is always zero, there is a demand to eliminate the degradation difference. In this paper, we present a critical-PMOS-aware clock tree design methodology to deal with this problem. First, we prove that, under the same tree topology, the NAND-type-matching clock tree has the minimum number of critical PMOS transistors. Then, we propose a 0–1 ILP (integer linear programming) approach to minimize the power consumption overhead while eliminating the degradation difference. Benchmark data consistently show that our design methodology can achieve very good results in terms of both the clock skew (due to the degradation difference) and the power consumption overhead.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419906
Kuen-Huei Lin, S. Cai, Chung-Yang Huang
In this paper, we proposed a novel simulation scheme, called data-dependency-aware synchronization and scheduling, for SoC virtual platform simulation. In contrast to the conventional clock-or transaction-based synchronization, our simulation scheme can work with the clock decoupling and direct-data-access techniques to implement the trace-driven virtual synchronization methodology. In addition, we further extend the virtual synchronization concept to handle the interrupt signals in the system. This enables the porting of operating system (uCLinux) in our virtual platform. The experimental results show that our virtual platform can achieve 3 to 5 million-instructions-per-second simulation speed, or 44 times speed-up over the conventional cycle accurate approach, while still maintaining the same cycle-count accuracy.
{"title":"Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling","authors":"Kuen-Huei Lin, S. Cai, Chung-Yang Huang","doi":"10.1109/ASPDAC.2010.5419906","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419906","url":null,"abstract":"In this paper, we proposed a novel simulation scheme, called data-dependency-aware synchronization and scheduling, for SoC virtual platform simulation. In contrast to the conventional clock-or transaction-based synchronization, our simulation scheme can work with the clock decoupling and direct-data-access techniques to implement the trace-driven virtual synchronization methodology. In addition, we further extend the virtual synchronization concept to handle the interrupt signals in the system. This enables the porting of operating system (uCLinux) in our virtual platform. The experimental results show that our virtual platform can achieve 3 to 5 million-instructions-per-second simulation speed, or 44 times speed-up over the conventional cycle accurate approach, while still maintaining the same cycle-count accuracy.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"51 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120854749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419810
Lakshmi N. Chakrapani, K. Palem
We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (pbl). By combining the properties of pbl with the properties of noise susceptible cmos devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs.
{"title":"A Probabilistic Boolean Logic for energy efficient circuit and system design","authors":"Lakshmi N. Chakrapani, K. Palem","doi":"10.1109/ASPDAC.2010.5419810","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419810","url":null,"abstract":"We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (pbl). By combining the properties of pbl with the properties of noise susceptible cmos devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133769204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419814
Hu-Hsi Yeh, Chung-Yang Huang
In this paper, we proposed an Automatic Target Constraint Generation (ATCG) technique to automatically generate compact and high-quality constraints for the guided random simulation environment. Our objective is to tackle the biggest bottleneck of the entire constrained random simulation process — the time-consuming and error-prone manual testbench composition process. By taking only the design under verification and simulation coverage as our inputs, our automatic constraint generation technique can successfully generate just a few key constraints while achieving very high simulation coverage. Our experimental results show that the proposed approach can outperform both directed and random simulations in both coverage and simulation runtime for a variety of designs
{"title":"Automatic Constraint Generation for guided random simulation","authors":"Hu-Hsi Yeh, Chung-Yang Huang","doi":"10.1109/ASPDAC.2010.5419814","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419814","url":null,"abstract":"In this paper, we proposed an Automatic Target Constraint Generation (ATCG) technique to automatically generate compact and high-quality constraints for the guided random simulation environment. Our objective is to tackle the biggest bottleneck of the entire constrained random simulation process — the time-consuming and error-prone manual testbench composition process. By taking only the design under verification and simulation coverage as our inputs, our automatic constraint generation technique can successfully generate just a few key constraints while achieving very high simulation coverage. Our experimental results show that the proposed approach can outperform both directed and random simulations in both coverage and simulation runtime for a variety of designs","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133848189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419867
R. Takashima, Yuya Hanai, Y. Hori, T. Kuroda
A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.
{"title":"A versatile recognition processor for sensor network applications","authors":"R. Takashima, Yuya Hanai, Y. Hori, T. Kuroda","doi":"10.1109/ASPDAC.2010.5419867","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419867","url":null,"abstract":"A versatile recognition processor is presented that comprises 2.1M transistors using a 90nm CMOS technology. It performs detection and recognition from image/video, sound and acceleration signals with energy consumption of sub-mJ/frame. The versatility and the power efficiency are attributed to optimal architecture design employing Haar-like Feature and Cascaded Classifier.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"509 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419895
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast access, non-volatility, and good scalability. The physical characteristics of a PRAM cell mainly depend on the material characteristic and the fabrication process. However, the access device and the operating voltage have significant impact on the PRAM performance, energy dissipation, and lifetime. In this paper, we study the design constraints for PRAM memory array, and propose design optimizations of the access device and the circuit operational voltage. The important features of PRAM memory, such as power consumption, read/write stability, speed, as well as lifetime are all considered as the constrained conditions in the proposed optimizations. Experimental results showed that the proposed methodology can provide a reliable design space for the access device and the operating voltage.
{"title":"Energy and performance driven circuit design for emerging Phase-Change Memory","authors":"Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie","doi":"10.1109/ASPDAC.2010.5419895","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419895","url":null,"abstract":"Phase-Change Random Access Memory (PRAM) has become one of the most promising emerging memory technologies, due to its attractive features such as high density, fast access, non-volatility, and good scalability. The physical characteristics of a PRAM cell mainly depend on the material characteristic and the fabrication process. However, the access device and the operating voltage have significant impact on the PRAM performance, energy dissipation, and lifetime. In this paper, we study the design constraints for PRAM memory array, and propose design optimizations of the access device and the circuit operational voltage. The important features of PRAM memory, such as power consumption, read/write stability, speed, as well as lifetime are all considered as the constrained conditions in the proposed optimizations. Experimental results showed that the proposed methodology can provide a reliable design space for the access device and the operating voltage.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134433596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419831
Zijian He, Tao Lv, Huawei Li, Xiaowei Li
Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.
{"title":"Graph partition based path selection for testing of small delay defects","authors":"Zijian He, Tao Lv, Huawei Li, Xiaowei Li","doi":"10.1109/ASPDAC.2010.5419831","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419831","url":null,"abstract":"Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133290064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419870
Shun Kawada, Shin Sakai, Y. Tashiro, S. Sugawa
We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1/3.3-inch optical format, 1280H × 480V pixels, 4.2-µm effective pixel pitch along with 45° direction was designed and fabricated through 0.18-µm 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image sensor has achieved about 108-µV/ē high conversion gain and about 102-dB dynamic range (DR) performance in one exposure.
{"title":"Checkered White-RGB Color LOFIC CMOS image sensor","authors":"Shun Kawada, Shin Sakai, Y. Tashiro, S. Sugawa","doi":"10.1109/ASPDAC.2010.5419870","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419870","url":null,"abstract":"We succeeded in developing a checkered White-RGB color CMOS image sensor based on a lateral overflow integration capacitor (LOFIC) architecture. The LOFIC CMOS image sensor with a 1/3.3-inch optical format, 1280<sup>H</sup> × 480<sup>V</sup> pixels, 4.2-µm effective pixel pitch along with 45° direction was designed and fabricated through 0.18-µm 2-Poly 3-Metal CMOS technology with buried pinned photodiode (PD) process. The image sensor has achieved about 108-µV/ē high conversion gain and about 102-dB dynamic range (DR) performance in one exposure.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133731224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419868
D. Imanishi, JeeYoung Hong, K. Okada, A. Matsuzawa
A tunable power amplifier (PA) from 2.1 GHz to 6.0 GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 µm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −8 dB, power gain of larger than 12 dB, output 1-dB compression point of larger than 15 dBm.
{"title":"A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters","authors":"D. Imanishi, JeeYoung Hong, K. Okada, A. Matsuzawa","doi":"10.1109/ASPDAC.2010.5419868","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419868","url":null,"abstract":"A tunable power amplifier (PA) from 2.1 GHz to 6.0 GHz is presented for multi-standard radios. The proposed multi-band PA can tune the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 µm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −8 dB, power gain of larger than 12 dB, output 1-dB compression point of larger than 15 dBm.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116306954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419918
N. Chang, Jueun Seo, Donghwa Shin, Younghyun Kim
Direct methanol fuel cells (DMFCs) are a promising next-generation energy source for portable applications, due to their high energy density and the ease of handling of the liquid fuel. However, the limited range of output power obtainable from a fuel cell requires hybridization the introduction of a battery to form a stand-alone portable power source. Furthermore, the stringent operating conditions to be met by active DMFC systems mandate complicated balance of plant (BOP) control. We present a complete hybrid active DMFC system design and implementation in which a DMFC stack and a li-ion battery are linked by a hybridization circuit to share the applied load to exploit high energy density of the fuel cell and high power density of the battery. We describe systems for fuel delivery, air supply, temperature management, current and voltage measurement, DC-DC conversion and power distribution, motor driving, battery charge management, DMFC and circuit protection, and control of the DMFC and battery as a hybrid. We have designed and implemented an embedded system controller that consists of a 32-bit microcontroller, running under a real-time operating system, that incorporating multiple cascaded feedback control loops which manage the dynamics of BOP control. We demonstrate reliable and efficient maintenance of a constant fuel cell output current in spite of severe fluctuation of the load current.
{"title":"Room-temperature fuel cells and their integration into portable and embedded systems","authors":"N. Chang, Jueun Seo, Donghwa Shin, Younghyun Kim","doi":"10.1109/ASPDAC.2010.5419918","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419918","url":null,"abstract":"Direct methanol fuel cells (DMFCs) are a promising next-generation energy source for portable applications, due to their high energy density and the ease of handling of the liquid fuel. However, the limited range of output power obtainable from a fuel cell requires hybridization the introduction of a battery to form a stand-alone portable power source. Furthermore, the stringent operating conditions to be met by active DMFC systems mandate complicated balance of plant (BOP) control. We present a complete hybrid active DMFC system design and implementation in which a DMFC stack and a li-ion battery are linked by a hybridization circuit to share the applied load to exploit high energy density of the fuel cell and high power density of the battery. We describe systems for fuel delivery, air supply, temperature management, current and voltage measurement, DC-DC conversion and power distribution, motor driving, battery charge management, DMFC and circuit protection, and control of the DMFC and battery as a hybrid. We have designed and implemented an embedded system controller that consists of a 32-bit microcontroller, running under a real-time operating system, that incorporating multiple cascaded feedback control loops which manage the dynamics of BOP control. We demonstrate reliable and efficient maintenance of a constant fuel cell output current in spite of severe fluctuation of the load current.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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