Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419879
Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen
As the clock frequency increases, signal propagation delays on PCBs are requested to meet the timing specifications with very high accuracy. Generally speaking, the length controllability of a net decides the routing delay of the net. If a routing result has the higher length controllability, the routing delay will be obtained with higher accuracy. In this paper, given a start terminal, S, and a target terminal, T, in mxn routing grids with obstacles, based on the rectangular partition in routing grids and the analysis of unreachable grids in rectangular pattern detouring, an efficient O(mnlog(mn)) algorithm is proposed to generate the longest path in routing grids from S to T. Compared with the US routing[5], our proposed routing approach can achieve longer paths for tested examples in less CPU time.
{"title":"Obstacle-aware longest path using rectangular pattern detouring in routing grids","authors":"Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen","doi":"10.1109/ASPDAC.2010.5419879","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419879","url":null,"abstract":"As the clock frequency increases, signal propagation delays on PCBs are requested to meet the timing specifications with very high accuracy. Generally speaking, the length controllability of a net decides the routing delay of the net. If a routing result has the higher length controllability, the routing delay will be obtained with higher accuracy. In this paper, given a start terminal, S, and a target terminal, T, in mxn routing grids with obstacles, based on the rectangular partition in routing grids and the analysis of unreachable grids in rectangular pattern detouring, an efficient O(mnlog(mn)) algorithm is proposed to generate the longest path in routing grids from S to T. Compared with the US routing[5], our proposed routing approach can achieve longer paths for tested examples in less CPU time.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419808
Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, M. Tsai
A robust pixel-based optimization algorithm is proposed for mask synthesis of inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. Result shows that the final image fidelity is almost independent of the initial condition. To demonstrate the robustness of the algorithm, six typical desired mask patterns and two mask technologies are applied in mask synthesis optimization using 100 randomly generated initial conditions. The critical dimension (CD) is 60nm and the partial-coherence image system is applied. It is found that the final edge placement error (EPE) and iteration number are quite weakly dependent on the initial conditions. Good final image fidelity can be acquired using arbitrary initial conditions. This algorithm is about several orders of magnitude faster and more effective than other gradient-based algorithm and simulated annealing algorithm.
{"title":"A robust pixel-based RET optimization algorithm independent of initial conditions","authors":"Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, M. Tsai","doi":"10.1109/ASPDAC.2010.5419808","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419808","url":null,"abstract":"A robust pixel-based optimization algorithm is proposed for mask synthesis of inverse lithography technology (ILT) to improve the resolution and pattern fidelity in optical lithography. Result shows that the final image fidelity is almost independent of the initial condition. To demonstrate the robustness of the algorithm, six typical desired mask patterns and two mask technologies are applied in mask synthesis optimization using 100 randomly generated initial conditions. The critical dimension (CD) is 60nm and the partial-coherence image system is applied. It is found that the final edge placement error (EPE) and iteration number are quite weakly dependent on the initial conditions. Good final image fidelity can be acquired using arbitrary initial conditions. This algorithm is about several orders of magnitude faster and more effective than other gradient-based algorithm and simulated annealing algorithm.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133313585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419798
L. Lavagno, A. Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, M. Tatesawa, Noriyasu Nakayama
The widespread acceptance of High-level synthesis as a mainstream tool mostly depends on its tight integration with the following RTL-to-GDSII design flow. A key aspect is the handling of so-called Engineering Change Orders (ECOs), i.e. minor changes required to fix small functional bugs or meet performance requirements late in the design cycle. Traditional high-level synthesis has attempted to optimize at best the output logic. However, in the ECO scenario the goal is to implement the required change with as few modifications as possible to the RTL, logic netlist, placed netlist and layout. In this paper we show how, by judiciously changing the internal databases used by the tool to match as much as possible the original design, one can achieve minimal impact and implement ECOs in truly incremental mode, while full-blow re-synthesis would lead to massive unnecessary downstream changes. The tool essentially matches source constructs between the original and the ECO design, and copies as many synthesis decisions as possible from the original design to the ECO design.
{"title":"Incremental high-level synthesis","authors":"L. Lavagno, A. Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, M. Tatesawa, Noriyasu Nakayama","doi":"10.1109/ASPDAC.2010.5419798","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419798","url":null,"abstract":"The widespread acceptance of High-level synthesis as a mainstream tool mostly depends on its tight integration with the following RTL-to-GDSII design flow. A key aspect is the handling of so-called Engineering Change Orders (ECOs), i.e. minor changes required to fix small functional bugs or meet performance requirements late in the design cycle. Traditional high-level synthesis has attempted to optimize at best the output logic. However, in the ECO scenario the goal is to implement the required change with as few modifications as possible to the RTL, logic netlist, placed netlist and layout. In this paper we show how, by judiciously changing the internal databases used by the tool to match as much as possible the original design, one can achieve minimal impact and implement ECOs in truly incremental mode, while full-blow re-synthesis would lead to massive unnecessary downstream changes. The tool essentially matches source constructs between the original and the ECO design, and copies as many synthesis decisions as possible from the original design to the ECO design.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419779
K. Yamashita
The embedded systems for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process, especially multi-core based SoC. But it can be difficult to estimate system performance of actual target by employing only simple estimation methods.
{"title":"Possibility of ESL: A software centric system design for multicore SoC in the upstream phase","authors":"K. Yamashita","doi":"10.1109/ASPDAC.2010.5419779","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419779","url":null,"abstract":"The embedded systems for which both hardware and software are rapidly advancing and expanding, there is a growing need to be able to comprehensively and quantitatively estimate system performance at an early stage in the design process, especially multi-core based SoC. But it can be difficult to estimate system performance of actual target by employing only simple estimation methods.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"611 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133633407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419882
Y. Kohira, A. Takahashi
In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a pin to the other pin greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.
{"title":"CAFE router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles","authors":"Y. Kohira, A. Takahashi","doi":"10.1109/ASPDAC.2010.5419882","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419882","url":null,"abstract":"In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a pin to the other pin greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419854
Steve C. L. Yuen, Yanqing Ai, B.P.L.S. Chan, T. Chau, S. M. H. Ho, Oscar K. L. Lau, K. Pun, P. Leong, O. Choy
We describe the architecture of a structured ASIC fabric in which the logic and routing can be customized using three masks. A standard Cadence based design flow is employed, and using an active dynamic backlight controller as an example, performance is compared to that of an ASIC implementation in the same technology.
{"title":"Rapid prototyping on a structured ASIC fabric","authors":"Steve C. L. Yuen, Yanqing Ai, B.P.L.S. Chan, T. Chau, S. M. H. Ho, Oscar K. L. Lau, K. Pun, P. Leong, O. Choy","doi":"10.1109/ASPDAC.2010.5419854","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419854","url":null,"abstract":"We describe the architecture of a structured ASIC fabric in which the logic and routing can be customized using three masks. A standard Cadence based design flow is employed, and using an active dynamic backlight controller as an example, performance is compared to that of an ASIC implementation in the same technology.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115704861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419805
K. Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu
Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved.
{"title":"A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects","authors":"K. Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu","doi":"10.1109/ASPDAC.2010.5419805","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419805","url":null,"abstract":"Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419919
Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
With the challenges of growing functionality and scaling chip size, the possible performance improvements should be considered in the earlier IC design stages, which gives more freedom to the later optimization. Potential slack as an effective metric of possible performance improvements is considered in this work which, as far as we known, is the first work that maximizes the potential slack by retiming for synchronous sequential circuit. A simultaneous slack budgeting and incremental retiming algorithm is proposed for maximizing potential slack. The overall slack budget is optimized by relocating the FFs iteratively with the MIS-based slack estimation. Compared with the potential slack of a well-known min-period retiming, our algorithm improves potential slack averagely 19.6% without degrading the circuit performance in reasonable runtime. Furthermore, at the expense of a small amount of timing performance, 0.52% and 2.08%, the potential slack is increased averagely by 19.89% and 28.16% separately, which give a hint of the tradeoff between the timing performance and the slack budget.
{"title":"Simultaneous slack budgeting and retiming for synchronous circuits optimization","authors":"Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang","doi":"10.1109/ASPDAC.2010.5419919","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419919","url":null,"abstract":"With the challenges of growing functionality and scaling chip size, the possible performance improvements should be considered in the earlier IC design stages, which gives more freedom to the later optimization. Potential slack as an effective metric of possible performance improvements is considered in this work which, as far as we known, is the first work that maximizes the potential slack by retiming for synchronous sequential circuit. A simultaneous slack budgeting and incremental retiming algorithm is proposed for maximizing potential slack. The overall slack budget is optimized by relocating the FFs iteratively with the MIS-based slack estimation. Compared with the potential slack of a well-known min-period retiming, our algorithm improves potential slack averagely 19.6% without degrading the circuit performance in reasonable runtime. Furthermore, at the expense of a small amount of timing performance, 0.52% and 2.08%, the potential slack is increased averagely by 19.89% and 28.16% separately, which give a hint of the tradeoff between the timing performance and the slack budget.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122758900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419844
A. Yanamandra, S. Eachempati, N. Soundararajan, N. Vijaykrishnan, M. J. Irwin, R. Krishnan
We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off reliability. To further increase the power savings, we bound the vulnerability of a router by throttling the traffic into the router. In order to minimize the throughput loss due to throttling, we propose dividing the die into domains and using multiple vulnerability bounds across these domains. We explore both static and dynamic selection of vulnerability bounds. We find that for applications with an error tolerance of 10% of the raw error rate, the dynamic multiple vulnerability bound scheme can save up to 44% of power expended for error correction at a marginal network throughput loss of 3%.
{"title":"Optimizing power and performance for reliable on-chip networks","authors":"A. Yanamandra, S. Eachempati, N. Soundararajan, N. Vijaykrishnan, M. J. Irwin, R. Krishnan","doi":"10.1109/ASPDAC.2010.5419844","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419844","url":null,"abstract":"We propose novel techniques to minimize the power and performance penalties in protecting the NoC against soft errors, while giving desired reliability guarantees. Some applications have inherent error tolerance which can be exploited to save power, by turning off the error correction mechanisms for a fraction of the total time without trading off reliability. To further increase the power savings, we bound the vulnerability of a router by throttling the traffic into the router. In order to minimize the throughput loss due to throttling, we propose dividing the die into domains and using multiple vulnerability bounds across these domains. We explore both static and dynamic selection of vulnerability bounds. We find that for applications with an error tolerance of 10% of the raw error rate, the dynamic multiple vulnerability bound scheme can save up to 44% of power expended for error correction at a marginal network throughput loss of 3%.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123863943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-01-18DOI: 10.1109/ASPDAC.2010.5419899
P. Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang
Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC's effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC.
{"title":"Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis","authors":"P. Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang","doi":"10.1109/ASPDAC.2010.5419899","DOIUrl":"https://doi.org/10.1109/ASPDAC.2010.5419899","url":null,"abstract":"Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC's effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC.","PeriodicalId":152569,"journal":{"name":"2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129987453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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