Abstract Thermal energy is a renewable energy source to generate electrical energy that is not fully developed. One device that converts thermal energy into electrical power is a thermoelectric generator (TEG). TEGs are available as modules of various sizes and voltage levels. This paper is about the design of a battery charging system powered by a TEG panel. The TEG panel is implemented using 150 TEG modules interconnected in series and parallel. Its power is transferred to a battery using two stages of DC/DC converters. The 1 st stage is a Lou converter that is used for maximum power point tracking (MPPT) by a referenced perturb and observe (referenced P&O) algorithm. The 2 nd stage is a bidirectional converter based on buck-boost modes of operation. The system is used to charge a 9 V 1.2 Ah battery. The proposed MPPT algorithm’s performance is compared with a traditional P&O algorithm. The TEG panel provided 27.5 W at a Δ T of 30 0 C. The designed system is simulated in MATLAB SIMULINK.
热能是一种可再生能源，用以产生尚未充分开发的电能。一种将热能转化为电能的装置是热电发电机(TEG)。teg可作为各种尺寸和电压等级的模块。本文设计了一种由TEG面板供电的电池充电系统。TEG面板由150个TEG模块串联和并联实现。它的电力通过两级DC/DC转换器传输到电池。第一级是一个低电平转换器，通过参考摄动和观察(参考P&O)算法用于最大功率点跟踪(MPPT)。第二级是基于降压-升压工作模式的双向变换器。该系统用于充电9 V 1.2 Ah电池。将该算法的性能与传统的P&O算法进行了比较。TEG面板在Δ温度为30℃时提供27.5 W的功率，并在MATLAB SIMULINK中进行了系统仿真。
{"title":"Design of a battery charging system fed by thermoelectric generator panels using MPPT techniques","authors":"Mustafa F. Mohammed, Mohammed A. Qasim","doi":"10.2478/jee-2023-0043","DOIUrl":"https://doi.org/10.2478/jee-2023-0043","url":null,"abstract":"Abstract Thermal energy is a renewable energy source to generate electrical energy that is not fully developed. One device that converts thermal energy into electrical power is a thermoelectric generator (TEG). TEGs are available as modules of various sizes and voltage levels. This paper is about the design of a battery charging system powered by a TEG panel. The TEG panel is implemented using 150 TEG modules interconnected in series and parallel. Its power is transferred to a battery using two stages of DC/DC converters. The 1 st stage is a Lou converter that is used for maximum power point tracking (MPPT) by a referenced perturb and observe (referenced P&O) algorithm. The 2 nd stage is a bidirectional converter based on buck-boost modes of operation. The system is used to charge a 9 V 1.2 Ah battery. The proposed MPPT algorithm’s performance is compared with a traditional P&O algorithm. The TEG panel provided 27.5 W at a Δ T of 30 0 C. The designed system is simulated in MATLAB SIMULINK.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.
{"title":"Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider","authors":"Premananda Belegehalli Siddaiah, Sahithi Narsepalli, Sanya Mittal, Abdur Rehman","doi":"10.2478/jee-2023-0048","DOIUrl":"https://doi.org/10.2478/jee-2023-0048","url":null,"abstract":"Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract This research paper delves into a comprehensive investigation concerning the impact of additive noise and quantization error on the precision of amplitude, offset, and phase estimates of a sine wave fitted to a set of data points acquired by a waveform digitizer. Simulation results are used to validate the expressions presented.
{"title":"Precision of sinewave amplitude estimation in the presence of additive noise and quantization error","authors":"Francisco André Corrêa Alegria","doi":"10.2478/jee-2023-0045","DOIUrl":"https://doi.org/10.2478/jee-2023-0045","url":null,"abstract":"Abstract This research paper delves into a comprehensive investigation concerning the impact of additive noise and quantization error on the precision of amplitude, offset, and phase estimates of a sine wave fitted to a set of data points acquired by a waveform digitizer. Simulation results are used to validate the expressions presented.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract This work presents a new T-flipflop design based on quantum-dot cellular automata technology, with the standard two inputs ( T and clock) and two outputs ( Q and Q̄ ). It adheres to the typical QCA layout design approach, which consists of two majority voters and one inverter (to produce the complementary output, Q̄ ). It is a single-layered design with no crossover. A memory loop is used to retain previous values and aid the toggling operation of the T-flipflop. This design achieves improved functionality and reduced area requirement compared to existing designs. In addition, the study investigated energy loss and cost functions. In particular, the total energy loss is reduced by 10% and 22% compared to the best design when analyzed with the QCAPro and QCADesigner-E (QDE) tools, respectively. The area-delay and energy-delay cost functions outperform the best current design by 1.3 and 1.07 times, respectively. Overall, this work advances QCA-based flipflop (QTFF) designs and emphasizes the potential of QCA technology for creating effective QCA circuits.
本文提出了一种基于量子点元胞自动机技术的新型T触发器设计，具有标准的两个输入(T和时钟)和两个输出(Q和Q)。它遵循典型的QCA布局设计方法，由两个多数选民和一个逆变器(产生互补输出，Q)组成。这是一个单层的设计，没有交叉。记忆循环用于保留先前的值并帮助t触发器的切换操作。与现有设计相比，该设计实现了功能的改进和面积的减少。此外，研究了能量损失和成本函数。特别是，当使用QCAPro和qcaddesigner - e (QDE)工具进行分析时，与最佳设计相比，总能量损失分别减少了10%和22%。区域延迟和能量延迟成本函数分别比最佳电流设计高1.3倍和1.07倍。总的来说，这项工作推进了基于QCA的触发器(QTFF)设计，并强调了QCA技术在创建有效QCA电路方面的潜力。
{"title":"Elementary design and analysis of QCA-based T-flipflop for nanocomputing","authors":"Angshuman Khan","doi":"10.2478/jee-2023-0041","DOIUrl":"https://doi.org/10.2478/jee-2023-0041","url":null,"abstract":"Abstract This work presents a new T-flipflop design based on quantum-dot cellular automata technology, with the standard two inputs ( T and clock) and two outputs ( Q and Q̄ ). It adheres to the typical QCA layout design approach, which consists of two majority voters and one inverter (to produce the complementary output, Q̄ ). It is a single-layered design with no crossover. A memory loop is used to retain previous values and aid the toggling operation of the T-flipflop. This design achieves improved functionality and reduced area requirement compared to existing designs. In addition, the study investigated energy loss and cost functions. In particular, the total energy loss is reduced by 10% and 22% compared to the best design when analyzed with the QCAPro and QCADesigner-E (QDE) tools, respectively. The area-delay and energy-delay cost functions outperform the best current design by 1.3 and 1.07 times, respectively. Overall, this work advances QCA-based flipflop (QTFF) designs and emphasizes the potential of QCA technology for creating effective QCA circuits.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136009932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohamed Essalih Boussouar, Abdelghani Chelihi, Khaled Yahia, Antonio J. Marques Cardoso
Abstract This paper investigates an optimal model-free control design for a synchronous reluctance motor (Syn-RM) with unknown nonlinear dynamic functions, parameter variations, and disturbances. The idea is to combine a predictive control with a time-delay estimation technique (TDE) in order to successfully deal with the system’s uncertainties and make the Syn-RM control scheme easy to implement in real-time. This model-free control strategy comprises two cascade control loops namely outer and inner loops. The outer loop is designed for the mechanical part of Syn-RM to ensure the convergence of the speed dynamics by using a proportional-integral controller while the inner loop is developed to control the uncertain dynamics of currents via an optimal robust controller. In the proposed current loop, the predictive control is enhanced by the inclusion of ultra-local model theory where dynamic functions and disturbances are estimated by instantaneous input-output measurements of the Syn-RM using the TDE approach. Moreover, a particle swarm optimization (PSO) algorithm is also proposed to find the optimal design parameters to improve the dynamic performances of the closed-loop control system. Numerical validation tests of the proposed TDE-based model-free predictive current control (TDE-MFPCC) method are performed in the simulation environment of the Syn-RM system, and the results show the robustness and the effectiveness of the proposed TDE-MFPCC compared to the conventional model-based PCC.
{"title":"Model-free predictive current control of Syn-RM based on time delay estimation approach","authors":"Mohamed Essalih Boussouar, Abdelghani Chelihi, Khaled Yahia, Antonio J. Marques Cardoso","doi":"10.2478/jee-2023-0042","DOIUrl":"https://doi.org/10.2478/jee-2023-0042","url":null,"abstract":"Abstract This paper investigates an optimal model-free control design for a synchronous reluctance motor (Syn-RM) with unknown nonlinear dynamic functions, parameter variations, and disturbances. The idea is to combine a predictive control with a time-delay estimation technique (TDE) in order to successfully deal with the system’s uncertainties and make the Syn-RM control scheme easy to implement in real-time. This model-free control strategy comprises two cascade control loops namely outer and inner loops. The outer loop is designed for the mechanical part of Syn-RM to ensure the convergence of the speed dynamics by using a proportional-integral controller while the inner loop is developed to control the uncertain dynamics of currents via an optimal robust controller. In the proposed current loop, the predictive control is enhanced by the inclusion of ultra-local model theory where dynamic functions and disturbances are estimated by instantaneous input-output measurements of the Syn-RM using the TDE approach. Moreover, a particle swarm optimization (PSO) algorithm is also proposed to find the optimal design parameters to improve the dynamic performances of the closed-loop control system. Numerical validation tests of the proposed TDE-based model-free predictive current control (TDE-MFPCC) method are performed in the simulation environment of the Syn-RM system, and the results show the robustness and the effectiveness of the proposed TDE-MFPCC compared to the conventional model-based PCC.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract In this paper, the design methodology of a high-linearity wide-band transimpedance amplifier (TIA) for cable television (CATV) application is addressed. A simple four-stage topology is proposed to maintain a well-balanced linearity over a wide operating band. The regulated cascode (RGC) input stage is used to match an input impedance of 75 Ω, followed by a gain stage with enhanced bandwidth. The high-linearity output stage is able to drive the 75 Ω load directly with high output swing under a high supply voltage. The prototype is implemented with a standard 0.11μm CMOS process while occupying the silicon area of 0.034 mm 2 . The measurement results for the prototype show a peak gain of 76.6 dBΩ over a 3-dB bandwidth of 1.1 GHz with a considerably small gain ripple and an OIP 3 of 20.4 dBm. The whole test chip consumes 447 mW DC power and the measured average input-referred noise current spectral density is 7.9 pA Hz −1/2 up to 1 GHz.
介绍了一种用于有线电视(CATV)的高线性宽带跨阻放大器(TIA)的设计方法。提出了一种简单的四级拓扑结构，以在宽工作频带内保持良好的平衡线性。调节级联码(RGC)输入级用于匹配75 Ω的输入阻抗，然后是带宽增强的增益级。高线性输出级能够在高电源电压下以高输出摆幅直接驱动75 Ω负载。该原型机采用标准的0.11μm CMOS工艺，占据0.034 mm 2的硅面积。测量结果表明，在1.1 GHz的3db带宽下，样机的峰值增益为76.6 dBΩ，增益纹波相当小，OIP 3为20.4 dBm。整个测试芯片的直流功耗为447 mW，测量到的平均输入参考噪声电流谱密度为7.9 pA Hz−1/2至1 GHz。
{"title":"Design of wide-band high-linearity transimpedance amplifier using standard CMOS technology","authors":"Zheng Gu, Siqi Wang, Chungang Lu, Lei Song, Zhenghao Lu, Yonghua Chu, Xiaopeng Yu","doi":"10.2478/jee-2023-0049","DOIUrl":"https://doi.org/10.2478/jee-2023-0049","url":null,"abstract":"Abstract In this paper, the design methodology of a high-linearity wide-band transimpedance amplifier (TIA) for cable television (CATV) application is addressed. A simple four-stage topology is proposed to maintain a well-balanced linearity over a wide operating band. The regulated cascode (RGC) input stage is used to match an input impedance of 75 Ω, followed by a gain stage with enhanced bandwidth. The high-linearity output stage is able to drive the 75 Ω load directly with high output swing under a high supply voltage. The prototype is implemented with a standard 0.11μm CMOS process while occupying the silicon area of 0.034 mm 2 . The measurement results for the prototype show a peak gain of 76.6 dBΩ over a 3-dB bandwidth of 1.1 GHz with a considerably small gain ripple and an OIP 3 of 20.4 dBm. The whole test chip consumes 447 mW DC power and the measured average input-referred noise current spectral density is 7.9 pA Hz −1/2 up to 1 GHz.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Many speech processing systems’ crucial frontends include speech enhancement. Single-channel speech enhancement experiences a number of technological challenges. Due to the advent of cloud-based technology and the use of deep learning systems in big data, deep neural networks in particular have recently been seen as a potent means for complex classification and regression. In this work, spectral gating noise filter is combined with deep neural network U-Net to enhance the performance of speech enhancement network. Further, for performance analysis three distinct objective functions namely, Mean Square Error, Huber Loss and Mean Absolute Error are considered as loss functions. In addition, comparison of three different optimizers Adam, Adagrad and Stochastic Gradient Descent is presented. Proposed system is tested and evaluated on LibriSpeech and NOIZEUS datasets and compared to other state-of-the-art systems. It demonstrates that, in comparison to other state-of-the-art models, the proposed network outperformed them with PESQ scores of 2.737420 for training and 2.67857 for testing, along with better generalization ability.
{"title":"Performance analysis of speech enhancement using spectral gating with U-Net","authors":"Jharna Agrawal, Manish Gupta, Hitendra Garg","doi":"10.2478/jee-2023-0044","DOIUrl":"https://doi.org/10.2478/jee-2023-0044","url":null,"abstract":"Abstract Many speech processing systems’ crucial frontends include speech enhancement. Single-channel speech enhancement experiences a number of technological challenges. Due to the advent of cloud-based technology and the use of deep learning systems in big data, deep neural networks in particular have recently been seen as a potent means for complex classification and regression. In this work, spectral gating noise filter is combined with deep neural network U-Net to enhance the performance of speech enhancement network. Further, for performance analysis three distinct objective functions namely, Mean Square Error, Huber Loss and Mean Absolute Error are considered as loss functions. In addition, comparison of three different optimizers Adam, Adagrad and Stochastic Gradient Descent is presented. Proposed system is tested and evaluated on LibriSpeech and NOIZEUS datasets and compared to other state-of-the-art systems. It demonstrates that, in comparison to other state-of-the-art models, the proposed network outperformed them with PESQ scores of 2.737420 for training and 2.67857 for testing, along with better generalization ability.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Antonino Caracciolo, Samuele Ollio, Alessio Pizzi, Leonardo Romeo, Antonio Enrico Serranò, Giuseppe Vasily Tringali, Antonino Greco, Mario Versaci
Abstract Over the years, the Italian Government has taken significant strides in promoting road safety awareness among the students in high schools to create an awareness of prevention and a consciousness of road safety in the student population. In this context, an agreement was signed between the DICEAM Department of the “Mediterranea” University of Reggio Calabria (Italy) and the “Euclide” Higher Education Institute Bova Marina (Italy) to combine road safety with research science in the Science, Technology, Engineering, and Mathematics (STEM) area. With the primary aim of “knowing in order to act”, the students focused on the multi-physics design of magnetorheological fluid dampers as high-performance devices (simple to design and requiring reduced maintenance) for vehicle suspensions, especially class B vehicles. By combining road safety considerations with multi-physics scientific disciplines, the project seeks to emphasize the importance of prevention and knowledge-based action. The study explores the use of magnetorheological fluid dampers, powered by electric current and magnetic induction distribution with thermal loads, to provide appropriate yield stress for developing damping action with repercussions on the quality of road safety. The paper delves into the basic principles of FEM (Finite Element Method) techniques for analyzing an MR damper from both magnetostatic (the main cause generating the damping effect) and thermal perspectives (thermal effects are strongly influenced by environmental conditions). The analysis of an asymmetrical device, where the damping action relies on an MR fluid strip, reveals the significant influence of magnetic and thermal stresses on the magnetization of individual particles and the overall viscosity of the MR fluid.
{"title":"Thermal-magnetic performance analysis for smart fluid dampers","authors":"Antonino Caracciolo, Samuele Ollio, Alessio Pizzi, Leonardo Romeo, Antonio Enrico Serranò, Giuseppe Vasily Tringali, Antonino Greco, Mario Versaci","doi":"10.2478/jee-2023-0046","DOIUrl":"https://doi.org/10.2478/jee-2023-0046","url":null,"abstract":"Abstract Over the years, the Italian Government has taken significant strides in promoting road safety awareness among the students in high schools to create an awareness of prevention and a consciousness of road safety in the student population. In this context, an agreement was signed between the DICEAM Department of the “Mediterranea” University of Reggio Calabria (Italy) and the “Euclide” Higher Education Institute Bova Marina (Italy) to combine road safety with research science in the Science, Technology, Engineering, and Mathematics (STEM) area. With the primary aim of “knowing in order to act”, the students focused on the multi-physics design of magnetorheological fluid dampers as high-performance devices (simple to design and requiring reduced maintenance) for vehicle suspensions, especially class B vehicles. By combining road safety considerations with multi-physics scientific disciplines, the project seeks to emphasize the importance of prevention and knowledge-based action. The study explores the use of magnetorheological fluid dampers, powered by electric current and magnetic induction distribution with thermal loads, to provide appropriate yield stress for developing damping action with repercussions on the quality of road safety. The paper delves into the basic principles of FEM (Finite Element Method) techniques for analyzing an MR damper from both magnetostatic (the main cause generating the damping effect) and thermal perspectives (thermal effects are strongly influenced by environmental conditions). The analysis of an asymmetrical device, where the damping action relies on an MR fluid strip, reveals the significant influence of magnetic and thermal stresses on the magnetization of individual particles and the overall viscosity of the MR fluid.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract The paper investigates software solutions to simulate radio waves propagation in urban environment, specifically for the context of the Internet of Things (IoT). The purpose of the study is to provide a comprehensive guide for utilizing the Altair Feko software to obtain a detailed representation of the IoT network, its associated parameters and how they relate to the modeling of electromagnetic fields. It is beneficial to simulate the network during the design stage to obtain valuable data and make necessary adjustments. The key features of a Sigfox or other low power IoT network can be obtained by simulation, enabling an evaluation of the network design prior to its actual implementation. Given the growing demand for IoT devices and networks, researching the optimal design and performance of such networks is of great importance. This underscores the need for continuous exploration of effective methods to achieve efficient design and performance of IoT networks.
{"title":"Methods of computer modeling of electromagnetic field propagation in urban scenarios for Internet of Things","authors":"Anatolii Kliuchka, René Harťanský, Ján Halgoš","doi":"10.2478/jee-2023-0050","DOIUrl":"https://doi.org/10.2478/jee-2023-0050","url":null,"abstract":"Abstract The paper investigates software solutions to simulate radio waves propagation in urban environment, specifically for the context of the Internet of Things (IoT). The purpose of the study is to provide a comprehensive guide for utilizing the Altair Feko software to obtain a detailed representation of the IoT network, its associated parameters and how they relate to the modeling of electromagnetic fields. It is beneficial to simulate the network during the design stage to obtain valuable data and make necessary adjustments. The key features of a Sigfox or other low power IoT network can be obtained by simulation, enabling an evaluation of the network design prior to its actual implementation. Given the growing demand for IoT devices and networks, researching the optimal design and performance of such networks is of great importance. This underscores the need for continuous exploration of effective methods to achieve efficient design and performance of IoT networks.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract This paper introduces a novel circuit design for a memcapacitance emulator, employing a single Voltage Differencing Current Conveyor (VDCC) as its core element. The emulator circuit has been intricately designed, employing only capacitors as grounded passive components. One remarkable aspect of these circuits is their inherent electronic tunability, allowing for precise control of the achieved inverse memcapacitance. The theoretical analysis of the emulator includes a comprehensive examination of potential non-idealities and parasitic influences. Careful selection of passive circuit elements has been made to minimize the impact of these undesirable effects. In contrast to extant designs cataloged in the existing literature, the presented circuitry manifests remarkable simplicity in its configuration. Furthermore, it exhibits a wide operational frequency range, extending up to 50MHz, and effectively clears the non-volatility criterion. To substantiate the efficacy of the devised circuits, comprehensive LTSpice simulations have been conducted, employing a 0.18 μm TSMC process parameter and a power supply of ±0.9 V. These simulations provide robust evidence of the emulator’s performance, reaffirming the feasibility and practicality of the proposed approach in the domain of memcapacitance emulation.
{"title":"Realization of a memcapacitance emulator utilizing a singular current-mode active block","authors":"Mihajlo Tatović, Predrag B. Petrović","doi":"10.2478/jee-2023-0047","DOIUrl":"https://doi.org/10.2478/jee-2023-0047","url":null,"abstract":"Abstract This paper introduces a novel circuit design for a memcapacitance emulator, employing a single Voltage Differencing Current Conveyor (VDCC) as its core element. The emulator circuit has been intricately designed, employing only capacitors as grounded passive components. One remarkable aspect of these circuits is their inherent electronic tunability, allowing for precise control of the achieved inverse memcapacitance. The theoretical analysis of the emulator includes a comprehensive examination of potential non-idealities and parasitic influences. Careful selection of passive circuit elements has been made to minimize the impact of these undesirable effects. In contrast to extant designs cataloged in the existing literature, the presented circuitry manifests remarkable simplicity in its configuration. Furthermore, it exhibits a wide operational frequency range, extending up to 50MHz, and effectively clears the non-volatility criterion. To substantiate the efficacy of the devised circuits, comprehensive LTSpice simulations have been conducted, employing a 0.18 μm TSMC process parameter and a power supply of ±0.9 V. These simulations provide robust evidence of the emulator’s performance, reaffirming the feasibility and practicality of the proposed approach in the domain of memcapacitance emulation.","PeriodicalId":15661,"journal":{"name":"Journal of Electrical Engineering-elektrotechnicky Casopis","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136010215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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