Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208174
F. Ferguson, T. Larrabee
Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. May of these defects may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper the authors consider the probable manufacturing defects and compare the costs of detecting them by the resulting excess IDDQ versus the cost of traditional testing methods.<>
{"title":"Test pattern generation for current testable faults in static CMOS circuits","authors":"F. Ferguson, T. Larrabee","doi":"10.1109/VTEST.1991.208174","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208174","url":null,"abstract":"Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. May of these defects may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper the authors consider the probable manufacturing defects and compare the costs of detecting them by the resulting excess IDDQ versus the cost of traditional testing methods.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117107852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208157
S. Midkiff, S. Bollinger
The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.<>
{"title":"Circuit-level classification and testability analysis for CMOS faults","authors":"S. Midkiff, S. Bollinger","doi":"10.1109/VTEST.1991.208157","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208157","url":null,"abstract":"The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115216048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208156
P. Ryan, S. Rawat, W. Fuchs
Fault dictionaries are examined as a tool for automated diagnosis of VLSI failures. A compressed fault dictionary format and diagnosis algorithms are presented. Both combinational and sequential circuits are considered. Dictionaries are created, for example ISCAS circuits and simulated errors diagnosed.<>
{"title":"Automated diagnosis of VLSI failures","authors":"P. Ryan, S. Rawat, W. Fuchs","doi":"10.1109/VTEST.1991.208156","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208156","url":null,"abstract":"Fault dictionaries are examined as a tool for automated diagnosis of VLSI failures. A compressed fault dictionary format and diagnosis algorithms are presented. Both combinational and sequential circuits are considered. Dictionaries are created, for example ISCAS circuits and simulated errors diagnosed.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126349218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208171
P. Nagvajara, M. Karpovsky, L. Levitin
An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r>
{"title":"Efficient test generation for built-in self-test boundary-scan template","authors":"P. Nagvajara, M. Karpovsky, L. Levitin","doi":"10.1109/VTEST.1991.208171","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208171","url":null,"abstract":"An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r<s, the expected number N(T) of PRPG clock pulses required for generating T<or=2/sup r/ distinct r-bit patterns and the expected number T(N) of distinct patterns given a number N of clock pulses were presented. The proposed theoretical average N(T) was shown to be close to the experimental average values N/sub ex/(T). Hence, the value N(T) or T(N) can be used as a benchmark for evaluating the efficiency of a BIST boundary scan test generation.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123074276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208173
Y. Malaiya, A. Jayasumana, C. Tong, S. Menon
Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest as logical faults, and would not be detected by traditional IC test techniques. In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to normal parameter variations. A statistical characterisation of the problem is presented. This can be used to determine the optimal size of partitions. A new information compression scheme is presented which can significantly enhance resolution.<>
{"title":"Enhancement of resolution in supply current based testing for large ICs","authors":"Y. Malaiya, A. Jayasumana, C. Tong, S. Menon","doi":"10.1109/VTEST.1991.208173","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208173","url":null,"abstract":"Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest as logical faults, and would not be detected by traditional IC test techniques. In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to normal parameter variations. A statistical characterisation of the problem is presented. This can be used to determine the optimal size of partitions. A new information compression scheme is presented which can significantly enhance resolution.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123440832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208127
S. Devadas, K. Keutzer, Abhijit Ghosh
Describes recent work involving the automatic synthesis of VLSI circuits with testability considerations. The first put of this paper explores the potential for logic synthesis to allow designers to more comprehensively test circuits while simultaneously diminishing the need for fault simulation and automatic test pattern generation. Logic optimization procedures can be used to produce circuits that are completely testable for single stuck-at faults. Testing for faults such as multiple stuck-at faults, gate delay faults and path delay faults is a greater challenge, but logic synthesis and optimization procedures can produce circuits that have high degrees of testability under these models as well. For each of these fault models test vectors can be produced as a by-product of the synthesis process and vector minimization algorithms can be used in the place of fault simulation to reduce the size of the test vector sets. The second part of the paper considers the difficult problem of synthesizing sequential circuits with high degrees of single stuck-at fault coverage without incurring the area and performance penalty of scan registers. Initial results at combining synthesis for testability approaches with register-transfer level automatic test-pattern generation to produce vector sets that give complete single stuck-at fault coverage without the use of scan.<>
{"title":"Recent progress in synthesis for testability","authors":"S. Devadas, K. Keutzer, Abhijit Ghosh","doi":"10.1109/VTEST.1991.208127","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208127","url":null,"abstract":"Describes recent work involving the automatic synthesis of VLSI circuits with testability considerations. The first put of this paper explores the potential for logic synthesis to allow designers to more comprehensively test circuits while simultaneously diminishing the need for fault simulation and automatic test pattern generation. Logic optimization procedures can be used to produce circuits that are completely testable for single stuck-at faults. Testing for faults such as multiple stuck-at faults, gate delay faults and path delay faults is a greater challenge, but logic synthesis and optimization procedures can produce circuits that have high degrees of testability under these models as well. For each of these fault models test vectors can be produced as a by-product of the synthesis process and vector minimization algorithms can be used in the place of fault simulation to reduce the size of the test vector sets. The second part of the paper considers the difficult problem of synthesizing sequential circuits with high degrees of single stuck-at fault coverage without incurring the area and performance penalty of scan registers. Initial results at combining synthesis for testability approaches with register-transfer level automatic test-pattern generation to produce vector sets that give complete single stuck-at fault coverage without the use of scan.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208126
S. Chandra, T. Gheewala, H. Sucar, G. Swan
The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.<>
{"title":"Use of CrossCheck test technology in practical applications","authors":"S. Chandra, T. Gheewala, H. Sucar, G. Swan","doi":"10.1109/VTEST.1991.208126","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208126","url":null,"abstract":"The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130695799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208143
Ashok K. Sharma
Describes the VLSI parts quality and reliability issued for NASA space flight use, particularly from a NASA/Goddard Space Flight Center (GSFC) perspective. A case history of four chip set gate arrays planned for use on a high speed flight data recorder, qualification effort based on MIL-M-38510 requirements, is discussed.<>
{"title":"VLSI procurement and qualification: NASA/GSFC experience, issues and concerns","authors":"Ashok K. Sharma","doi":"10.1109/VTEST.1991.208143","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208143","url":null,"abstract":"Describes the VLSI parts quality and reliability issued for NASA space flight use, particularly from a NASA/Goddard Space Flight Center (GSFC) perspective. A case history of four chip set gate arrays planned for use on a high speed flight data recorder, qualification effort based on MIL-M-38510 requirements, is discussed.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134098454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208150
H.-D. Oberle, M. Maue, P. Muhmenthaler
For typical physical DRAM cell array defects, logical fault models are derived. These models completely and unambiguously describe all coupling faults and pattern sensitivities. Thus, test patterns are developed for production tests and fault analyses with high fault coverage.<>
{"title":"Enhanced fault modeling for DRAM test and analysis","authors":"H.-D. Oberle, M. Maue, P. Muhmenthaler","doi":"10.1109/VTEST.1991.208150","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208150","url":null,"abstract":"For typical physical DRAM cell array defects, logical fault models are derived. These models completely and unambiguously describe all coupling faults and pattern sensitivities. Thus, test patterns are developed for production tests and fault analyses with high fault coverage.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116496020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208169
W. Hartmann, C. Starke
The authors describe the design for testability (DFT) and testing methodology for the S/390 processor being part of IBM's low-end ES/9000 systems. The design incorporates built-in pseudo-random pattern self test and the boundary scan technique. Self test permits the migration of tests generated for the component level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages has been drastically reduced and the card test equipment can be simplified. In addition, the applied strategy offers economical diagnostic capability.<>
{"title":"Testing of VLSI CMOS System/390 processor at card and system level","authors":"W. Hartmann, C. Starke","doi":"10.1109/VTEST.1991.208169","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208169","url":null,"abstract":"The authors describe the design for testability (DFT) and testing methodology for the S/390 processor being part of IBM's low-end ES/9000 systems. The design incorporates built-in pseudo-random pattern self test and the boundary scan technique. Self test permits the migration of tests generated for the component level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages has been drastically reduced and the card test equipment can be simplified. In addition, the applied strategy offers economical diagnostic capability.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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