Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208172
Steven D. McEuen
The author discusses many different aspects of IDDq, quality, reliability, and test being the major three. A description of IDDq is presented with different pragmatic methods of implementing it. Employing IDDq testing on digital CMOS technology, the user obtains a product with greater reliability. These benefits are introduced, which clearly support IDDq's implementation.<>
{"title":"IDDq benefits (digital CMOS testing)","authors":"Steven D. McEuen","doi":"10.1109/VTEST.1991.208172","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208172","url":null,"abstract":"The author discusses many different aspects of IDDq, quality, reliability, and test being the major three. A description of IDDq is presented with different pragmatic methods of implementing it. Employing IDDq testing on digital CMOS technology, the user obtains a product with greater reliability. These benefits are introduced, which clearly support IDDq's implementation.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208137
S. F. Oakland
This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<>
{"title":"Combining IEEE Standard 1149.1 with reduced-pin-count component test","authors":"S. F. Oakland","doi":"10.1109/VTEST.1991.208137","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208137","url":null,"abstract":"This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208175
Kuen-Jong Lee, M. Breuer
Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.<>
{"title":"Constraints for using IDDQ testing to detect CMOS bridging faults","authors":"Kuen-Jong Lee, M. Breuer","doi":"10.1109/VTEST.1991.208175","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208175","url":null,"abstract":"Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208160
M. A. Heap, W. A. Rogers, William B. Burns
The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<>
{"title":"STarS: a target switching algorithm for sequential test generation","authors":"M. A. Heap, W. A. Rogers, William B. Burns","doi":"10.1109/VTEST.1991.208160","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208160","url":null,"abstract":"The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208153
P. Lala, F. Busaba, K. Yarlagadda
It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.<>
{"title":"An approach for designing self-checking logic using residue codes","authors":"P. Lala, F. Busaba, K. Yarlagadda","doi":"10.1109/VTEST.1991.208153","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208153","url":null,"abstract":"It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208134
Stanford S. Guillory, D. Saab, A. Yang
The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<>
{"title":"Fault modeling and testing of self-timed circuits","authors":"Stanford S. Guillory, D. Saab, A. Yang","doi":"10.1109/VTEST.1991.208134","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208134","url":null,"abstract":"The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130341351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208162
Nikolaus Gouders, Reinhard Kaibel
The authors present several methods to enhance the performance of sequential test generation algorithms. Among the innovations proposed are a new circuit model, a novel learning technique, new methods to deal with testability measures and a powerful procedure to identify untestable faults. They use an enhanced implementation of the BACK algorithm together with a set of published benchmark circuits to demonstrate the efficiency of the proposed techniques. The results show that the overall performance of the BACK algorithm is greatly improved. For many of the benchmark circuits, test generation time is reduced by more than one order of magnitude.<>
{"title":"Test generation techniques for sequential circuits","authors":"Nikolaus Gouders, Reinhard Kaibel","doi":"10.1109/VTEST.1991.208162","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208162","url":null,"abstract":"The authors present several methods to enhance the performance of sequential test generation algorithms. Among the innovations proposed are a new circuit model, a novel learning technique, new methods to deal with testability measures and a powerful procedure to identify untestable faults. They use an enhanced implementation of the BACK algorithm together with a set of published benchmark circuits to demonstrate the efficiency of the proposed techniques. The results show that the overall performance of the BACK algorithm is greatly improved. For many of the benchmark circuits, test generation time is reduced by more than one order of magnitude.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131016748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208125
R. V. Riessen, H. Kerkhoff, Johan Janssen
This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<>
{"title":"A design-for-testability expert system for silicon compilers","authors":"R. V. Riessen, H. Kerkhoff, Johan Janssen","doi":"10.1109/VTEST.1991.208125","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208125","url":null,"abstract":"This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208165
David M. Wu
In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<>
{"title":"An optimized delay testing technique for LSSD-based VLSI logic circuits","authors":"David M. Wu","doi":"10.1109/VTEST.1991.208165","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208165","url":null,"abstract":"In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208140
N. Bourbakis, C. Ramamoorthy
Deals with the specifications for the development of an expert tool for the automatic optical detection and recognition of the connectivity among devices in digital electronic circuits and the understanding of the circuits functionality. In particular, the proposed tool, called ANTISTROFEAS, uses expert knowledge recognizing and understanding electronic circuits without the use of their associated database. The ANTISTROFEAS tool will use classical picture processing methods in combination with heuristics and knowledge acquisition schemes. The expert tool proposed is used for understanding of 'unknown' electronic circuits, or where the complexity of the circuit is too great, so that any human searching effort requires long time for reliable results.<>
{"title":"Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering","authors":"N. Bourbakis, C. Ramamoorthy","doi":"10.1109/VTEST.1991.208140","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208140","url":null,"abstract":"Deals with the specifications for the development of an expert tool for the automatic optical detection and recognition of the connectivity among devices in digital electronic circuits and the understanding of the circuits functionality. In particular, the proposed tool, called ANTISTROFEAS, uses expert knowledge recognizing and understanding electronic circuits without the use of their associated database. The ANTISTROFEAS tool will use classical picture processing methods in combination with heuristics and knowledge acquisition schemes. The expert tool proposed is used for understanding of 'unknown' electronic circuits, or where the complexity of the circuit is too great, so that any human searching effort requires long time for reliable results.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129113542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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