Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208147
R. M. Smyczynski, K. Brennan
Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<>
{"title":"A software system architecture for testing multiple part number wafers","authors":"R. M. Smyczynski, K. Brennan","doi":"10.1109/VTEST.1991.208147","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208147","url":null,"abstract":"Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208149
B. Ciciani
An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<>
{"title":"Modeling the effects of imperfect production testing on reconfigurable VLSI chips","authors":"B. Ciciani","doi":"10.1109/VTEST.1991.208149","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208149","url":null,"abstract":"An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115202657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208151
D. Sweetman
The test and guardband philosophy is essential in the manufacturing of integrated circuits. The philosophy integrates the general rules for test sequences, hardware, and software. The data sheet and philosophy determine the values and methodology for parameter and functional tests. Guardbanding is the off-setting of a test parameter, condition, or attribute acceptance level from the specified value. Variability in equipment and device performance necessitate machine guardbands. Device and test program guardbands improve test productivity. Changing the applied, measured, or external conditions from those specified implements the guardbands for attribute testing. The author addresses the use of guardbands for an MOS VLSI EEPROM, i.e. a nonvolatile reprogrammable memory.<>
{"title":"Guardbanding VLSI EEPROM test programs","authors":"D. Sweetman","doi":"10.1109/VTEST.1991.208151","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208151","url":null,"abstract":"The test and guardband philosophy is essential in the manufacturing of integrated circuits. The philosophy integrates the general rules for test sequences, hardware, and software. The data sheet and philosophy determine the values and methodology for parameter and functional tests. Guardbanding is the off-setting of a test parameter, condition, or attribute acceptance level from the specified value. Variability in equipment and device performance necessitate machine guardbands. Device and test program guardbands improve test productivity. Changing the applied, measured, or external conditions from those specified implements the guardbands for attribute testing. The author addresses the use of guardbands for an MOS VLSI EEPROM, i.e. a nonvolatile reprogrammable memory.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115634900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208172
Steven D. McEuen
The author discusses many different aspects of IDDq, quality, reliability, and test being the major three. A description of IDDq is presented with different pragmatic methods of implementing it. Employing IDDq testing on digital CMOS technology, the user obtains a product with greater reliability. These benefits are introduced, which clearly support IDDq's implementation.<>
{"title":"IDDq benefits (digital CMOS testing)","authors":"Steven D. McEuen","doi":"10.1109/VTEST.1991.208172","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208172","url":null,"abstract":"The author discusses many different aspects of IDDq, quality, reliability, and test being the major three. A description of IDDq is presented with different pragmatic methods of implementing it. Employing IDDq testing on digital CMOS technology, the user obtains a product with greater reliability. These benefits are introduced, which clearly support IDDq's implementation.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208175
Kuen-Jong Lee, M. Breuer
Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.<>
{"title":"Constraints for using IDDQ testing to detect CMOS bridging faults","authors":"Kuen-Jong Lee, M. Breuer","doi":"10.1109/VTEST.1991.208175","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208175","url":null,"abstract":"Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208134
Stanford S. Guillory, D. Saab, A. Yang
The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<>
{"title":"Fault modeling and testing of self-timed circuits","authors":"Stanford S. Guillory, D. Saab, A. Yang","doi":"10.1109/VTEST.1991.208134","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208134","url":null,"abstract":"The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130341351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208162
Nikolaus Gouders, Reinhard Kaibel
The authors present several methods to enhance the performance of sequential test generation algorithms. Among the innovations proposed are a new circuit model, a novel learning technique, new methods to deal with testability measures and a powerful procedure to identify untestable faults. They use an enhanced implementation of the BACK algorithm together with a set of published benchmark circuits to demonstrate the efficiency of the proposed techniques. The results show that the overall performance of the BACK algorithm is greatly improved. For many of the benchmark circuits, test generation time is reduced by more than one order of magnitude.<>
{"title":"Test generation techniques for sequential circuits","authors":"Nikolaus Gouders, Reinhard Kaibel","doi":"10.1109/VTEST.1991.208162","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208162","url":null,"abstract":"The authors present several methods to enhance the performance of sequential test generation algorithms. Among the innovations proposed are a new circuit model, a novel learning technique, new methods to deal with testability measures and a powerful procedure to identify untestable faults. They use an enhanced implementation of the BACK algorithm together with a set of published benchmark circuits to demonstrate the efficiency of the proposed techniques. The results show that the overall performance of the BACK algorithm is greatly improved. For many of the benchmark circuits, test generation time is reduced by more than one order of magnitude.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131016748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208148
R. Rajsuman, A. Jayasumana, Y. Malaiya, Juney Park
The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<>
{"title":"An analysis and testing of operation induced faults in MOS VLSI","authors":"R. Rajsuman, A. Jayasumana, Y. Malaiya, Juney Park","doi":"10.1109/VTEST.1991.208148","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208148","url":null,"abstract":"The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122834650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208160
M. A. Heap, W. A. Rogers, William B. Burns
The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<>
{"title":"STarS: a target switching algorithm for sequential test generation","authors":"M. A. Heap, W. A. Rogers, William B. Burns","doi":"10.1109/VTEST.1991.208160","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208160","url":null,"abstract":"The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127551381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208140
N. Bourbakis, C. Ramamoorthy
Deals with the specifications for the development of an expert tool for the automatic optical detection and recognition of the connectivity among devices in digital electronic circuits and the understanding of the circuits functionality. In particular, the proposed tool, called ANTISTROFEAS, uses expert knowledge recognizing and understanding electronic circuits without the use of their associated database. The ANTISTROFEAS tool will use classical picture processing methods in combination with heuristics and knowledge acquisition schemes. The expert tool proposed is used for understanding of 'unknown' electronic circuits, or where the complexity of the circuit is too great, so that any human searching effort requires long time for reliable results.<>
{"title":"Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering","authors":"N. Bourbakis, C. Ramamoorthy","doi":"10.1109/VTEST.1991.208140","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208140","url":null,"abstract":"Deals with the specifications for the development of an expert tool for the automatic optical detection and recognition of the connectivity among devices in digital electronic circuits and the understanding of the circuits functionality. In particular, the proposed tool, called ANTISTROFEAS, uses expert knowledge recognizing and understanding electronic circuits without the use of their associated database. The ANTISTROFEAS tool will use classical picture processing methods in combination with heuristics and knowledge acquisition schemes. The expert tool proposed is used for understanding of 'unknown' electronic circuits, or where the complexity of the circuit is too great, so that any human searching effort requires long time for reliable results.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129113542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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