Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208136
S. L. Dingle, Luke D. Lacroix, Peter A. Twombly
Boundary scan has been used extensively by IBM in custom logic, standard cell, and gate array logic chips. Actual implementations of boundary-scan methods used in testing these chips are discussed. The benefits of this approach are reviewed, and an economic analysis of the cost savings attributable to boundary scan are presented.<>
{"title":"The advantages of boundary-scan testing","authors":"S. L. Dingle, Luke D. Lacroix, Peter A. Twombly","doi":"10.1109/VTEST.1991.208136","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208136","url":null,"abstract":"Boundary scan has been used extensively by IBM in custom logic, standard cell, and gate array logic chips. Actual implementations of boundary-scan methods used in testing these chips are discussed. The benefits of this approach are reviewed, and an economic analysis of the cost savings attributable to boundary scan are presented.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116834098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208133
B. R. Epstein, Steven R. Miller, M. Czigler, David R. Gray
Classical discrimination analysis and neural network techniques are used to detect and classify possible faults in linear microcircuits. The success rates of simulated fault detection and classification are described for various types of analog and mixed-mode circuits.<>
{"title":"Linear microcircuit fault modeling and detection","authors":"B. R. Epstein, Steven R. Miller, M. Czigler, David R. Gray","doi":"10.1109/VTEST.1991.208133","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208133","url":null,"abstract":"Classical discrimination analysis and neural network techniques are used to detect and classify possible faults in linear microcircuits. The success rates of simulated fault detection and classification are described for various types of analog and mixed-mode circuits.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208142
M. Chowanetz, C. Kuntzsch, W. Wolz
The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<>
{"title":"Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems","authors":"M. Chowanetz, C. Kuntzsch, W. Wolz","doi":"10.1109/VTEST.1991.208142","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208142","url":null,"abstract":"The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208135
M. Soma
A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<>
{"title":"Probabilistic measures of fault equivalence in mixed-signal systems","authors":"M. Soma","doi":"10.1109/VTEST.1991.208135","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208135","url":null,"abstract":"A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"375 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208138
David S. Karpenske
Certainly one of the key factors in the manufacture of multichip modules (MCM) is the verification and fault diagnosis of an MCM's structural interconnects. High performance MCM products, which are clearly an expensive technology, will incur additional costs unless appropriate diagnostic tools are made available for fast failure analysis during production test. Boundary scan implementation is key in making these tools feasible.<>
{"title":"Interconnect verification of multichip modules using boundary scan","authors":"David S. Karpenske","doi":"10.1109/VTEST.1991.208138","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208138","url":null,"abstract":"Certainly one of the key factors in the manufacture of multichip modules (MCM) is the verification and fault diagnosis of an MCM's structural interconnects. High performance MCM products, which are clearly an expensive technology, will incur additional costs unless appropriate diagnostic tools are made available for fast failure analysis during production test. Boundary scan implementation is key in making these tools feasible.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128357973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208154
N. Rao, S. Toida
The problem of test generation for detecting stuck-at faults in combinational circuits is computationally intractable. Consequently, the identification of classes of circuits that support polynomial-time test generation algorithms is very important from testing and design viewpoints. The authors discuss several classes of polynomially-time testable circuits. First, they consider the existing polynomial classes obtained by using decompositions of the circuits. Another type of decomposition is proposed, based on fanout-reconvergent pairs, which also lead to classes of polynomial-time testable circuits. Then, the authors present the classes of polynomial-time testable circuits that are formed by the Boolean formulae belonging to the classes of weakly positive, weakly negative, bijunctive and affine.<>
{"title":"On polynomial-time testable classes of combinational circuits","authors":"N. Rao, S. Toida","doi":"10.1109/VTEST.1991.208154","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208154","url":null,"abstract":"The problem of test generation for detecting stuck-at faults in combinational circuits is computationally intractable. Consequently, the identification of classes of circuits that support polynomial-time test generation algorithms is very important from testing and design viewpoints. The authors discuss several classes of polynomially-time testable circuits. First, they consider the existing polynomial classes obtained by using decompositions of the circuits. Another type of decomposition is proposed, based on fanout-reconvergent pairs, which also lead to classes of polynomial-time testable circuits. Then, the authors present the classes of polynomial-time testable circuits that are formed by the Boolean formulae belonging to the classes of weakly positive, weakly negative, bijunctive and affine.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114902513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208144
E. Weis, E. Kinsbron, G. Chanoch, M. Snyder
As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<>
{"title":"High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification","authors":"E. Weis, E. Kinsbron, G. Chanoch, M. Snyder","doi":"10.1109/VTEST.1991.208144","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208144","url":null,"abstract":"As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"638 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116084416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208146
M. C. Kohalmy
Test engineers have been frustrated in their efforts to perform accurate functional testing of high speed VLSI devices on commercial ATE because of the impedance mismatch between the device and the ATE pin electronics. This mismatch between the low device output impedance and high ATE test station impedance causes signal reflections ('ringing') that interfere with testing. This paper will describe a circuit that effectively eliminates the problem of signal reflections. In contrast to earlier proposed solutions, this circuit is simple to understand and use.<>
{"title":"An adaptive device impedance matching circuit","authors":"M. C. Kohalmy","doi":"10.1109/VTEST.1991.208146","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208146","url":null,"abstract":"Test engineers have been frustrated in their efforts to perform accurate functional testing of high speed VLSI devices on commercial ATE because of the impedance mismatch between the device and the ATE pin electronics. This mismatch between the low device output impedance and high ATE test station impedance causes signal reflections ('ringing') that interfere with testing. This paper will describe a circuit that effectively eliminates the problem of signal reflections. In contrast to earlier proposed solutions, this circuit is simple to understand and use.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129430855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208155
M. Cutler, S. Su, Mingshien Wang
A distributed self-diagnosis algorithm for VLSI mesh arrays with small clusters of faults is presented. It allows only fault-free cells to make decisions and to propagate diagnosis results. Its time complexity is constant with respect to the number of processors. The diagnosability is proportional to the array size.<>
{"title":"Distributed self-diagnosis of VLSI mesh array processors","authors":"M. Cutler, S. Su, Mingshien Wang","doi":"10.1109/VTEST.1991.208155","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208155","url":null,"abstract":"A distributed self-diagnosis algorithm for VLSI mesh arrays with small clusters of faults is presented. It allows only fault-free cells to make decisions and to propagate diagnosis results. Its time complexity is constant with respect to the number of processors. The diagnosability is proportional to the array size.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208163
C. Chen, N. Soong
The authors present a statistical model for the evaluation of test coverage for both single-stuck-at and multiple-stuck-at faults. The model parameters are the node fault complexity and test frequency. For multiple fault detection, the model is applied to calculate the defect level of a production test.<>
{"title":"A statistical model for fault coverage analysis","authors":"C. Chen, N. Soong","doi":"10.1109/VTEST.1991.208163","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208163","url":null,"abstract":"The authors present a statistical model for the evaluation of test coverage for both single-stuck-at and multiple-stuck-at faults. The model parameters are the node fault complexity and test frequency. For multiple fault detection, the model is applied to calculate the defect level of a production test.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"1099 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113982026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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