Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208161
W. Debany
A method is presented that determines the coverage of shorts (bridging failures) by internal access techniques that provide node observability such as CMOS I/sub DD/ monitoring, CrossCheck, and voltage contrast. This method requires neither fault simulation nor listing of faults, and it is exact.<>
{"title":"Measuring the coverage of node shorts by internal access methods","authors":"W. Debany","doi":"10.1109/VTEST.1991.208161","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208161","url":null,"abstract":"A method is presented that determines the coverage of shorts (bridging failures) by internal access techniques that provide node observability such as CMOS I/sub DD/ monitoring, CrossCheck, and voltage contrast. This method requires neither fault simulation nor listing of faults, and it is exact.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123593444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208131
H. Youn
Among a number of techniques for efficiently testing VLSI circuits, the BIST using compression technique is recognized as reliable and cost effective. While compact testing using signature analysis allows an efficient test, some faulty responses cannot be detected due to aliasing. This paper shows how the aliasing probability can be significantly reduced by a factor of 2/sup (k+1)/ when k intermediate signatures are checked. The proposed scheme can also quickly detect the fault using fewer hardware resources.<>
{"title":"Compact testing with intermediate signature analysis","authors":"H. Youn","doi":"10.1109/VTEST.1991.208131","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208131","url":null,"abstract":"Among a number of techniques for efficiently testing VLSI circuits, the BIST using compression technique is recognized as reliable and cost effective. While compact testing using signature analysis allows an efficient test, some faulty responses cannot be detected due to aliasing. This paper shows how the aliasing probability can be significantly reduced by a factor of 2/sup (k+1)/ when k intermediate signatures are checked. The proposed scheme can also quickly detect the fault using fewer hardware resources.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130061050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208145
George M. Belansek, P. Loomis, F. Towler, Charles Warner, D. Wheeler
A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<>
{"title":"A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)","authors":"George M. Belansek, P. Loomis, F. Towler, Charles Warner, D. Wheeler","doi":"10.1109/VTEST.1991.208145","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208145","url":null,"abstract":"A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116472550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208167
Kyle G. Welch, J. Monzel, D. Kent, Donald W. Joseph
Two delay testing techniques, 'weighted random pattern' (WRP) test for logic and 'algorithmic pattern generation at the tester' (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<>
{"title":"Delay testing and failure analysis of ECL logic with embedded memories","authors":"Kyle G. Welch, J. Monzel, D. Kent, Donald W. Joseph","doi":"10.1109/VTEST.1991.208167","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208167","url":null,"abstract":"Two delay testing techniques, 'weighted random pattern' (WRP) test for logic and 'algorithmic pattern generation at the tester' (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115639264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208128
P. S. Levy
Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<>
{"title":"Power-down integrated circuit built-in self-test structures","authors":"P. S. Levy","doi":"10.1109/VTEST.1991.208128","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208128","url":null,"abstract":"Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208132
R. Rajsuman
The feedback bridging faults are examined in detail for MOS digital circuits. A necessary condition is obtained which needs to be satisfied for oscillations in the circuit. Expression are given to predict the frequency and amplitude of oscillations. It is shown that when a feedback bridging fault does not cause oscillations, it creates an anomalous output. Such faults may not be detected by logic testing: the authors recommend measurement of power supply current to detect such faults in CMOS circuit.<>
{"title":"An analysis of feedback bridging faults in MOS VLSI","authors":"R. Rajsuman","doi":"10.1109/VTEST.1991.208132","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208132","url":null,"abstract":"The feedback bridging faults are examined in detail for MOS digital circuits. A necessary condition is obtained which needs to be satisfied for oscillations in the circuit. Expression are given to predict the frequency and amplitude of oscillations. It is shown that when a feedback bridging fault does not cause oscillations, it creates an anomalous output. Such faults may not be detected by logic testing: the authors recommend measurement of power supply current to detect such faults in CMOS circuit.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126443017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208158
A. Wu, T. Lin, C. Tseng, J. Meador
The authors present experimental results which show that feedforward neural networks are well suited for analog IC fault diagnosis. Their results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production environment. They specifically compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network is found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy. This makes the feedforward network classifier an excellent candidate for production line diagnosis of IC faults, where circuit verification time greatly influences total cost per part.<>
{"title":"Neural network diagnosis of IC faults","authors":"A. Wu, T. Lin, C. Tseng, J. Meador","doi":"10.1109/VTEST.1991.208158","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208158","url":null,"abstract":"The authors present experimental results which show that feedforward neural networks are well suited for analog IC fault diagnosis. Their results suggest that feedforward networks provide a cost efficient method for IC fault diagnosis in a large scale production environment. They specifically compare the diagnostic accuracy and the computational requirements of a simple feedforward network against that of Gaussian maximum likelihood and K-nearest neighbors classifiers. The feedforward network is found to provide an order-of-magnitude improvement in diagnostic speed while consistently performing as well as or better than any of the other classifiers in terms of accuracy. This makes the feedforward network classifier an excellent candidate for production line diagnosis of IC faults, where circuit verification time greatly influences total cost per part.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208129
R. Srinivasan, C. Njinda, M. Breuer
Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<>
{"title":"A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing","authors":"R. Srinivasan, C. Njinda, M. Breuer","doi":"10.1109/VTEST.1991.208129","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208129","url":null,"abstract":"Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116169982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208139
Robert Cortez, R. Dandapani, Mike Yeager
Use of boundary-scan to test systems at the production and field levels has taken on a greater importance due to the development of surface mount technology. The IEEE Standard 1149.1 offers a documented approach to the implementation of boundary-scan. United Technologies Microelectronics Center (UTMC) integrated the standard into an ASIC gate array; this paper presents that implementation and addresses issues arising from the integration not covered specifically in the standard.<>
{"title":"Issues of integrating the IEEE Std 1149.1 into a gate array","authors":"Robert Cortez, R. Dandapani, Mike Yeager","doi":"10.1109/VTEST.1991.208139","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208139","url":null,"abstract":"Use of boundary-scan to test systems at the production and field levels has taken on a greater importance due to the development of surface mount technology. The IEEE Standard 1149.1 offers a documented approach to the implementation of boundary-scan. United Technologies Microelectronics Center (UTMC) integrated the standard into an ASIC gate array; this paper presents that implementation and addresses issues arising from the integration not covered specifically in the standard.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133395712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208170
Sheng Feng, Y. Malaiya
Built-in self-test (BIST) technique is now widely applied. How to estimate its testing capabilities is an important problem. BIST detectability is defined as the probability of that a fault set of the circuit-under-test is detected. It depends on the properties of the test at, circuit-under-test, as well as the signature analyser as a data compressor. The detectability of a signature analyzer is evaluated. The random and pseudorandom testing techniques are examined for their BIST detectability and several results are derived.<>
{"title":"Evaluation of detectability in BIST environment","authors":"Sheng Feng, Y. Malaiya","doi":"10.1109/VTEST.1991.208170","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208170","url":null,"abstract":"Built-in self-test (BIST) technique is now widely applied. How to estimate its testing capabilities is an important problem. BIST detectability is defined as the probability of that a fault set of the circuit-under-test is detected. It depends on the properties of the test at, circuit-under-test, as well as the signature analyser as a data compressor. The detectability of a signature analyzer is evaluated. The random and pseudorandom testing techniques are examined for their BIST detectability and several results are derived.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121357130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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