Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378204
Shraphalya B. Nalawade, Dhanashri H. Gawali
Security is an important issue during communication and data transmission. There are many ways to provide security. One method to ensure security is the use of cryptographic algorithms such as DES, AES, RC5, Blowfish etc. Cryptography is a method used for encoding the data which may be hacked by the unauthorized person. In this paper FPGA based design and implementation of Blowfish algorithm has been proposed. For RTL coding VHDL has been used and Virtex-5XC5VLX50T FPGA device used as a reconfigurable platform for implementation of Blowfish algorithm. The aim of this system is to evaluate performance of Blowfish algorithm on reconfigurable platform in terms of power consumption and throughput. For testing purpose image data and ECG data has been used as plaintext.
{"title":"Design and implementation of blowfish algorithm using reconfigurable platform","authors":"Shraphalya B. Nalawade, Dhanashri H. Gawali","doi":"10.1109/RISE.2017.8378204","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378204","url":null,"abstract":"Security is an important issue during communication and data transmission. There are many ways to provide security. One method to ensure security is the use of cryptographic algorithms such as DES, AES, RC5, Blowfish etc. Cryptography is a method used for encoding the data which may be hacked by the unauthorized person. In this paper FPGA based design and implementation of Blowfish algorithm has been proposed. For RTL coding VHDL has been used and Virtex-5XC5VLX50T FPGA device used as a reconfigurable platform for implementation of Blowfish algorithm. The aim of this system is to evaluate performance of Blowfish algorithm on reconfigurable platform in terms of power consumption and throughput. For testing purpose image data and ECG data has been used as plaintext.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378127
D. Punniamoorthy, G. K. Reddy, Vikram S. Kamadal, G. Gopal, K. Poornachary
Antennas with circularly polarization are largely used in present wireless communication systems because of their opposition to multipath distortion and polarization losses. On the other side, omnidirectional radiation patterns are mainly used since they can provide wide signal coverage and stabilize the signal transmission. As a result number of omnidirectional circularly polarized antennas have been designed and investigated over the past few years. The antenna design consist of modified ground plane connects to circular patch having two monopole modes by a set of conductive pins, to produce high impedance matching. The curved branches are designed at circumference of circular ground plane for producing a degenerate mode and producing circular polarization. The antenna prototype should be fabricated which is operating at 2.4GHz-WLAN band and measured radiation pattern, reflection coefficient, VSWR and antenna gain should well match with simulation results. In this paper simulation is done by using arlonAD320A in place of RogersRT/duroid 5880 because the cost of Rogers material is compare to arlon. But losses in arlon material are more, and these losses are reducing by decreasing number of shorting (or) conductive pins and increase the shorting pins radius. The prototype as a low profile 0.024 A a return loss value −30dB and gain of antenna is 4.68dB. To further characterize the design concept, and the antenna simulation is carried out using high frequency simulation software.
{"title":"Design of patch antenna with omni directional radiation pattern for wireless LAN applications","authors":"D. Punniamoorthy, G. K. Reddy, Vikram S. Kamadal, G. Gopal, K. Poornachary","doi":"10.1109/RISE.2017.8378127","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378127","url":null,"abstract":"Antennas with circularly polarization are largely used in present wireless communication systems because of their opposition to multipath distortion and polarization losses. On the other side, omnidirectional radiation patterns are mainly used since they can provide wide signal coverage and stabilize the signal transmission. As a result number of omnidirectional circularly polarized antennas have been designed and investigated over the past few years. The antenna design consist of modified ground plane connects to circular patch having two monopole modes by a set of conductive pins, to produce high impedance matching. The curved branches are designed at circumference of circular ground plane for producing a degenerate mode and producing circular polarization. The antenna prototype should be fabricated which is operating at 2.4GHz-WLAN band and measured radiation pattern, reflection coefficient, VSWR and antenna gain should well match with simulation results. In this paper simulation is done by using arlonAD320A in place of RogersRT/duroid 5880 because the cost of Rogers material is compare to arlon. But losses in arlon material are more, and these losses are reducing by decreasing number of shorting (or) conductive pins and increase the shorting pins radius. The prototype as a low profile 0.024 A a return loss value −30dB and gain of antenna is 4.68dB. To further characterize the design concept, and the antenna simulation is carried out using high frequency simulation software.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134359698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378189
Bharti Moryani, D. Mishra
As technology progresses, the growing demands of long life batteries in battery operated devices have set ways for new ideas that reduce the power consumed in these devices. As we know that during testing when the device's normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. So a method is proposed to minimize the concerned power at testing mode itself in the very beginning. This paper proposes a new design of “Test Pattern generator” for testing the circuits. The author has proposed a design which is quite different from the LFSR used till now. The test pattern generator proposed here has involved the use of a gray code generator together with a modified clock scheme. The circuit as a whole will generate exhaustive set of test patterns with hamming distance of one in between two consecutive sets. The idea behind this logic is to minimize dynamic power consumption which occurs because of increase in switching activity of the transistors at gate level. The modified clock will activate the clock only for that flip-flop where the logic changes from 0 to 1 or from 1 to 0. The power obtained using this design is about 36 mw.
{"title":"Low power test pattern generator with modified clock for BIST","authors":"Bharti Moryani, D. Mishra","doi":"10.1109/RISE.2017.8378189","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378189","url":null,"abstract":"As technology progresses, the growing demands of long life batteries in battery operated devices have set ways for new ideas that reduce the power consumed in these devices. As we know that during testing when the device's normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. So a method is proposed to minimize the concerned power at testing mode itself in the very beginning. This paper proposes a new design of “Test Pattern generator” for testing the circuits. The author has proposed a design which is quite different from the LFSR used till now. The test pattern generator proposed here has involved the use of a gray code generator together with a modified clock scheme. The circuit as a whole will generate exhaustive set of test patterns with hamming distance of one in between two consecutive sets. The idea behind this logic is to minimize dynamic power consumption which occurs because of increase in switching activity of the transistors at gate level. The modified clock will activate the clock only for that flip-flop where the logic changes from 0 to 1 or from 1 to 0. The power obtained using this design is about 36 mw.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115907719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378170
M. Ahmed
Installed Onboard cameras considering cases of off road unmanned navigating ground vehicles experience severe jitter and vibration. This leads to the prerequisite that the video images acquired from these platforms need to be heavily preprocessed to eliminate the jitter induced variations before human analysis. Digital Video stabilization system is the process of using electronic processing to control the image stability. That is, only software algorithms are used rather than hardware components such as motion sensors, actuators or floating lenses to compensate the disturbances. This makes digital stabilization more portable and cost effective among other methods. Digital stabilization can be used for real time and offline applications if the algorithms are optimized. This literature discusses the state of the art in the field of DVS with an implementation aspect of its use in challenging environment of unmanned ground vehicles where due to the dynamic nature of the vehicle, vibrations and oscillations are affect the camera resulting in a shaky and unstable video feed.
{"title":"Digital video stabilization-review with a perspective of real time implemention","authors":"M. Ahmed","doi":"10.1109/RISE.2017.8378170","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378170","url":null,"abstract":"Installed Onboard cameras considering cases of off road unmanned navigating ground vehicles experience severe jitter and vibration. This leads to the prerequisite that the video images acquired from these platforms need to be heavily preprocessed to eliminate the jitter induced variations before human analysis. Digital Video stabilization system is the process of using electronic processing to control the image stability. That is, only software algorithms are used rather than hardware components such as motion sensors, actuators or floating lenses to compensate the disturbances. This makes digital stabilization more portable and cost effective among other methods. Digital stabilization can be used for real time and offline applications if the algorithms are optimized. This literature discusses the state of the art in the field of DVS with an implementation aspect of its use in challenging environment of unmanned ground vehicles where due to the dynamic nature of the vehicle, vibrations and oscillations are affect the camera resulting in a shaky and unstable video feed.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132316816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378156
Arshi Khan, P. Agrawal, Himanshu Sainthiya
The image fusion plays a crucial role in many fields such as remote sensing, medical and robotics applications. This paper is focused on image fusion of images of different focus depth. The aim is to study these concepts and provide simulations and evaluations on various implementations. When performing image fusion the images are decomposed by bi-dimensional Empirical mode decomposition (BEMD) to obtain high frequency coefficients which is used to determine which parts of the input images that makes it into the fused image. The same technique is tested on images of different modality. In this thesis, a novel bi-dimensional Empirical mode decomposition (BEMD) based image fusion scheme is proposed. The BEMD decomposes the source images into intrinsic mode functions (IMFs) and residual components. IMF components of the first signal in the decomposition of the source images are used to generate the fused images using appropriate fusion rule. Performance evaluation of fused images is done by computing fusion quality metrics and the fusion results are compared with other existing fusion schemes. It is seen that the performance of the proposed scheme is better as compared with the existing fusion schemes.
{"title":"Bidimentional emphirical mode decomposition based image fusion","authors":"Arshi Khan, P. Agrawal, Himanshu Sainthiya","doi":"10.1109/RISE.2017.8378156","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378156","url":null,"abstract":"The image fusion plays a crucial role in many fields such as remote sensing, medical and robotics applications. This paper is focused on image fusion of images of different focus depth. The aim is to study these concepts and provide simulations and evaluations on various implementations. When performing image fusion the images are decomposed by bi-dimensional Empirical mode decomposition (BEMD) to obtain high frequency coefficients which is used to determine which parts of the input images that makes it into the fused image. The same technique is tested on images of different modality. In this thesis, a novel bi-dimensional Empirical mode decomposition (BEMD) based image fusion scheme is proposed. The BEMD decomposes the source images into intrinsic mode functions (IMFs) and residual components. IMF components of the first signal in the decomposition of the source images are used to generate the fused images using appropriate fusion rule. Performance evaluation of fused images is done by computing fusion quality metrics and the fusion results are compared with other existing fusion schemes. It is seen that the performance of the proposed scheme is better as compared with the existing fusion schemes.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132234940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378154
Pawan Dubey, T. Kanumuri, Ritesh Vyas
Proposed work aims to explore the discrimination capability of palmprint using Binary Wavelet Transform (BWT). As BWT transform is able to cluster the energy corresponding the edge location so, it can better represent the edges of the bit planes in its sub-bands. Firstly, a gray scale palmprint image is transformed into bit planes and then most significant of these bit planes are transformed through BWT. Further, micro and macro pattern histograms are extracted using Local Binary Pattern (LBP) from different transformed bit planes, and concatenated to form the feature vector. Experimental results validate that proposed approach is effective in terms of Genuine acceptance rate (GAR) of 98.71%.
{"title":"Palmprint recognition using binary wavelet transform and LBP representation","authors":"Pawan Dubey, T. Kanumuri, Ritesh Vyas","doi":"10.1109/RISE.2017.8378154","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378154","url":null,"abstract":"Proposed work aims to explore the discrimination capability of palmprint using Binary Wavelet Transform (BWT). As BWT transform is able to cluster the energy corresponding the edge location so, it can better represent the edges of the bit planes in its sub-bands. Firstly, a gray scale palmprint image is transformed into bit planes and then most significant of these bit planes are transformed through BWT. Further, micro and macro pattern histograms are extracted using Local Binary Pattern (LBP) from different transformed bit planes, and concatenated to form the feature vector. Experimental results validate that proposed approach is effective in terms of Genuine acceptance rate (GAR) of 98.71%.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378169
Sneha Agrawal, R. Chaurasiya
Automatic traffic sign detection and recognition (TSDR) is one of the most significant areas of object detection. In spite of numerous researches, it has always been a challenging problem. In this paper, an approach for detecting circular and triangular traffic signs is proposed. The performance of the entire system is measured on German traffic sign detection benchmark (GTSDB) and German traffic sign recognition benchmark (GTSRB) dataset. Traffic signs are detected using color segmentation and thresholding method in Hue Saturation Intensity (HSI) color space. Then, the shape of traffic signs is detected using geometric invariant Hu moments. Further, the features are extracted using a technique called HSI-HOG descriptor where features are extracted from each channel of HSI independently. To select the most discriminant features with minimal loss of information, dimensionality reduction technique Principal Component Analysis (PCA) is applied and classification is performed using Support Vector Machine (SVM) technique.
{"title":"Automatic traffic sign detection and recognition using moment invariants and support vector machine","authors":"Sneha Agrawal, R. Chaurasiya","doi":"10.1109/RISE.2017.8378169","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378169","url":null,"abstract":"Automatic traffic sign detection and recognition (TSDR) is one of the most significant areas of object detection. In spite of numerous researches, it has always been a challenging problem. In this paper, an approach for detecting circular and triangular traffic signs is proposed. The performance of the entire system is measured on German traffic sign detection benchmark (GTSDB) and German traffic sign recognition benchmark (GTSRB) dataset. Traffic signs are detected using color segmentation and thresholding method in Hue Saturation Intensity (HSI) color space. Then, the shape of traffic signs is detected using geometric invariant Hu moments. Further, the features are extracted using a technique called HSI-HOG descriptor where features are extracted from each channel of HSI independently. To select the most discriminant features with minimal loss of information, dimensionality reduction technique Principal Component Analysis (PCA) is applied and classification is performed using Support Vector Machine (SVM) technique.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115202773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378196
Deepak N. Agarwal, Y. K. Singh
This work presents a current reused low power 2.45 GHz LC oscillator. The paper provides a cross coupled LC oscillator used with NMOS resistor and the current reuse topology where two series transistors as staked switches and MOS resistor for symmetric output are used. This oscillator is designed with 0.5-μm CMOS process in ADS. Two topologies of LC oscillator are designed. The topology 2/1 draws only 117.9/68 μA current at 2/2.5 V DC supply, resulting in the oscillator consuming a very low power (0.2358 /0.17mW). The phase noise of proposed oscillator is −139 dBc/Hz at an offset 1 MHz. In order to eliminate mismatch in the output, an NMOS is used in triode region with 0.8235V gate voltage as a voltage drop provider.
{"title":"Low power, low phase noise current reuse 2.45 GHz LC oscillator with MOS resistor","authors":"Deepak N. Agarwal, Y. K. Singh","doi":"10.1109/RISE.2017.8378196","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378196","url":null,"abstract":"This work presents a current reused low power 2.45 GHz LC oscillator. The paper provides a cross coupled LC oscillator used with NMOS resistor and the current reuse topology where two series transistors as staked switches and MOS resistor for symmetric output are used. This oscillator is designed with 0.5-μm CMOS process in ADS. Two topologies of LC oscillator are designed. The topology 2/1 draws only 117.9/68 μA current at 2/2.5 V DC supply, resulting in the oscillator consuming a very low power (0.2358 /0.17mW). The phase noise of proposed oscillator is −139 dBc/Hz at an offset 1 MHz. In order to eliminate mismatch in the output, an NMOS is used in triode region with 0.8235V gate voltage as a voltage drop provider.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116228544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378202
Trapti Sharma, Laxmi Kumre
This work presents the contemplate review of diverse approaches employed to design XOR/XNOR circuits, as these circuits are the nucleus circuit for numerous computational intensive arithmetic circuits in VLSI. This paper describes the comparative analysis of performance evaluation of various reported XOR and XNOR circuits designs. The different designs are compared by performing the transistor level simulations on the benchmark circuit using HSPICE on 90nm PTM CMOS technology and analyzing the results in comprehensive manner. Based on the intensive simulations, the XOR/XNOR designs with feedback transistors outperforms well in comparison to other previously existing circuits in terms of high speed, low power and output voltage without any logic degradation with high noise tolerance capability.
{"title":"A comparative performance analysis of CMOS XOR XNOR circuits","authors":"Trapti Sharma, Laxmi Kumre","doi":"10.1109/RISE.2017.8378202","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378202","url":null,"abstract":"This work presents the contemplate review of diverse approaches employed to design XOR/XNOR circuits, as these circuits are the nucleus circuit for numerous computational intensive arithmetic circuits in VLSI. This paper describes the comparative analysis of performance evaluation of various reported XOR and XNOR circuits designs. The different designs are compared by performing the transistor level simulations on the benchmark circuit using HSPICE on 90nm PTM CMOS technology and analyzing the results in comprehensive manner. Based on the intensive simulations, the XOR/XNOR designs with feedback transistors outperforms well in comparison to other previously existing circuits in terms of high speed, low power and output voltage without any logic degradation with high noise tolerance capability.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125398788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/RISE.2017.8378208
Vandna Sikarwar, Vijayshri Chaurasia, J. S. Yadav, Yashwant Kurmi
Recent studies suggest that cells make stochastic choices with respect to differentiation or division. The effect of molecule concentration on cell division rate is analysed in this work. However, the molecular mechanism underlying such stochasticity is unknown. Here, we computationally model the effects of molecule concentration (acts as noise) on the Hes1/miR-9 oscillator. Consequences of low molecular numbers of interacting species are determined experimentally by the researchers. We report that increased stochasticity spreads the timing of differentiation in a population, such that initially equivalent cells differentiate over a period of time. Surprisingly, inherent stochasticity also increases the robustness of the progenitor state and lessens the impact of unequal, random distribution of molecules at cell division on the temporal spread of differentiation at the population level. This advantageous use of biological noise contrasts with the view that noise needs to be counteracted.
{"title":"Stochastic model analysis for Hes1/MiR-9 brain cell division system","authors":"Vandna Sikarwar, Vijayshri Chaurasia, J. S. Yadav, Yashwant Kurmi","doi":"10.1109/RISE.2017.8378208","DOIUrl":"https://doi.org/10.1109/RISE.2017.8378208","url":null,"abstract":"Recent studies suggest that cells make stochastic choices with respect to differentiation or division. The effect of molecule concentration on cell division rate is analysed in this work. However, the molecular mechanism underlying such stochasticity is unknown. Here, we computationally model the effects of molecule concentration (acts as noise) on the Hes1/miR-9 oscillator. Consequences of low molecular numbers of interacting species are determined experimentally by the researchers. We report that increased stochasticity spreads the timing of differentiation in a population, such that initially equivalent cells differentiate over a period of time. Surprisingly, inherent stochasticity also increases the robustness of the progenitor state and lessens the impact of unequal, random distribution of molecules at cell division on the temporal spread of differentiation at the population level. This advantageous use of biological noise contrasts with the view that noise needs to be counteracted.","PeriodicalId":166244,"journal":{"name":"2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128329772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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