Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324643
D.A. Gernhart, C. Chang, Kesse Ho
The interaction of signal line impedance, crosstalk, chip capacitive loading and driver circuit output impedance on the operation of a memory address bus is demonstrated. The ASTAP circuit simulation program is used for detailed studies. The results of three parallel address lines connected to memory chips for unterminated far ends are discussed. Signal-line impedance decreases when adjacent lines are introduced. Choosing the correct driver circuit output impedance and terminating resistance affects the signal-line voltage and switching. The memory chips add capacitive loading to the line, which also reduces the impedance and affects the delay of the line. Simultaneous switching of the address lines adds delay to the system as well. Some design parameters based upon these interactions are discussed.<>
{"title":"Memory card address bus design","authors":"D.A. Gernhart, C. Chang, Kesse Ho","doi":"10.1109/STIER.1990.324643","DOIUrl":"https://doi.org/10.1109/STIER.1990.324643","url":null,"abstract":"The interaction of signal line impedance, crosstalk, chip capacitive loading and driver circuit output impedance on the operation of a memory address bus is demonstrated. The ASTAP circuit simulation program is used for detailed studies. The results of three parallel address lines connected to memory chips for unterminated far ends are discussed. Signal-line impedance decreases when adjacent lines are introduced. Choosing the correct driver circuit output impedance and terminating resistance affects the signal-line voltage and switching. The memory chips add capacitive loading to the line, which also reduces the impedance and affects the delay of the line. Simultaneous switching of the address lines adds delay to the system as well. Some design parameters based upon these interactions are discussed.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114245976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324644
T. N. Rajashekhara, I. Chen
The advantage of carry free addition offered by signed-digit numbers is exploited in designing a fast adder circuit. Signed-digit numbers with radix 2 and digit set (-1,0,1), called redundant binary signed-digit (RBSD) numbers, are used in the design. Ternary logic circuits using an MOS/CMOS combination are employed. The ternary logic and RBSD number system complement each other well because one ternary bit can support one RBSD digit. This provides an advantage over using binary logic where more than one bit would be needed to support one RBSD digit. While the RBSD number system offers faster add times because of carry free addition, ternary logic offers reduced circuit complexity in terms of both transistor count and interconnections. All circuit implementations were simulated and verified for satisfactory performance using SPICE software on a SUN workstation.<>
{"title":"A fast adder design using signed-digit numbers and ternary logic","authors":"T. N. Rajashekhara, I. Chen","doi":"10.1109/STIER.1990.324644","DOIUrl":"https://doi.org/10.1109/STIER.1990.324644","url":null,"abstract":"The advantage of carry free addition offered by signed-digit numbers is exploited in designing a fast adder circuit. Signed-digit numbers with radix 2 and digit set (-1,0,1), called redundant binary signed-digit (RBSD) numbers, are used in the design. Ternary logic circuits using an MOS/CMOS combination are employed. The ternary logic and RBSD number system complement each other well because one ternary bit can support one RBSD digit. This provides an advantage over using binary logic where more than one bit would be needed to support one RBSD digit. While the RBSD number system offers faster add times because of carry free addition, ternary logic offers reduced circuit complexity in terms of both transistor count and interconnections. All circuit implementations were simulated and verified for satisfactory performance using SPICE software on a SUN workstation.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121585987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324654
T.N. Rajashekhara
The test response compression technique using signature analyzers or linear feedback shift registers (LFSRs) is discussed and some representative built-in self-test (BIST) designs which make use of LFSRs are presented. Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using LFSRs. The input to the LFSR is received from the output of a multiple input single output circuit under test (CUT). The structure and characteristics of LFSRs including a simplified mathematical analysis showing the confidence level in detecting faults are discussed. Some BIST design examples which include a programmable logic array, semiconductor memory, and a microcomputer are presented.<>
{"title":"Signature analyzers in built-in self-test circuits: a perspective","authors":"T.N. Rajashekhara","doi":"10.1109/STIER.1990.324654","DOIUrl":"https://doi.org/10.1109/STIER.1990.324654","url":null,"abstract":"The test response compression technique using signature analyzers or linear feedback shift registers (LFSRs) is discussed and some representative built-in self-test (BIST) designs which make use of LFSRs are presented. Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using LFSRs. The input to the LFSR is received from the output of a multiple input single output circuit under test (CUT). The structure and characteristics of LFSRs including a simplified mathematical analysis showing the confidence level in detecting faults are discussed. Some BIST design examples which include a programmable logic array, semiconductor memory, and a microcomputer are presented.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115775838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324642
E. M. Foster
A technique for optimizing bus performance early in the design cycle is described. The technique allows packaging-related aspects of bus delay to be analyzed in a spreadsheet format. The time required for receiver inputs to pass switching threshold is described as a series of simplex expression that can be entered into a spreadsheet for comparison of various design options. It assumes CMOS or TTL-like driver devices and unterminated receivers. Parameters that can be varied include driver output characteristics, receiver thresholds, number of receivers, bus partitioning, and card transmission line characteristics. An an example, analysis of design options for a large CMOS memory bus is demonstrated.<>
{"title":"A spreadsheet approach for early optimization of large bus switching performance","authors":"E. M. Foster","doi":"10.1109/STIER.1990.324642","DOIUrl":"https://doi.org/10.1109/STIER.1990.324642","url":null,"abstract":"A technique for optimizing bus performance early in the design cycle is described. The technique allows packaging-related aspects of bus delay to be analyzed in a spreadsheet format. The time required for receiver inputs to pass switching threshold is described as a series of simplex expression that can be entered into a spreadsheet for comparison of various design options. It assumes CMOS or TTL-like driver devices and unterminated receivers. Parameters that can be varied include driver output characteristics, receiver thresholds, number of receivers, bus partitioning, and card transmission line characteristics. An an example, analysis of design options for a large CMOS memory bus is demonstrated.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125718143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324640
J. Delgado-Frías
Since the conventional numerically oriented von Neumann computers are not appropriate for artificial intelligence (AI) software, new architectures for this application are discussed. AI computational requirements are considered. The requirements as well as the architectures for a set of AI applications are presented. LISP architectures including functional programming and the SPUR (symbolic processing using RISCs) system as an example are described. Logic oriented architectures are considered including OR-parallelism and AND-parallelism,. Knowledge oriented architectures and neural networks are discussed.<>
{"title":"Computer architectures for artificial intelligence processing","authors":"J. Delgado-Frías","doi":"10.1109/STIER.1990.324640","DOIUrl":"https://doi.org/10.1109/STIER.1990.324640","url":null,"abstract":"Since the conventional numerically oriented von Neumann computers are not appropriate for artificial intelligence (AI) software, new architectures for this application are discussed. AI computational requirements are considered. The requirements as well as the architectures for a set of AI applications are presented. LISP architectures including functional programming and the SPUR (symbolic processing using RISCs) system as an example are described. Logic oriented architectures are considered including OR-parallelism and AND-parallelism,. Knowledge oriented architectures and neural networks are discussed.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121901462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324637
L.A. Derrick, G. Randall
A conceptual framework that is adaptable must be created so CIM users can evolve in an open and decentralized way, suppliers receive sufficient requirements when developing new products, and enterprises can establish migration paths for existing applications toward more integrated systems. A plant production system may be thought of as a vertical structure formed several levels. The top layer is often called the hot system. Below it are computing systems and area controllers to manage specific business centers. The third layer is the manufacturing workstation. To successfully integrate a CIM enterprise, it is necessary to be able to both physically and logically connect the three levels of architecture. The three major areas of integration that must occur while evolving to a CIM environment are physical, application, and business integration. Each level depends on the previous for support. These areas of integration are discussed.<>
{"title":"Current trends in computer integrated manufacturing","authors":"L.A. Derrick, G. Randall","doi":"10.1109/STIER.1990.324637","DOIUrl":"https://doi.org/10.1109/STIER.1990.324637","url":null,"abstract":"A conceptual framework that is adaptable must be created so CIM users can evolve in an open and decentralized way, suppliers receive sufficient requirements when developing new products, and enterprises can establish migration paths for existing applications toward more integrated systems. A plant production system may be thought of as a vertical structure formed several levels. The top layer is often called the hot system. Below it are computing systems and area controllers to manage specific business centers. The third layer is the manufacturing workstation. To successfully integrate a CIM enterprise, it is necessary to be able to both physically and logically connect the three levels of architecture. The three major areas of integration that must occur while evolving to a CIM environment are physical, application, and business integration. Each level depends on the previous for support. These areas of integration are discussed.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130692837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324653
E. M. Foster
A method for simulating driver performance using the characteristic static output current curves for a low state (I/sub OL/) and high state (I/sub OH/) is presented. It offers a simplified alternative to complex theoretical models. This approach can be used to quickly evaluate the impact of a change in driver output on system performance, to determine the worst case performance, or to correlate experiments directly with a given test device. It requires that the I/sub OL/ and I/sub OH/, and the intrinsic transient time for the device be known. This information can be determined by measuring hardware, analyzing the output of a theoretical model, or summarizing data sheets.<>
{"title":"Creating simple driver models with device I-V curves","authors":"E. M. Foster","doi":"10.1109/STIER.1990.324653","DOIUrl":"https://doi.org/10.1109/STIER.1990.324653","url":null,"abstract":"A method for simulating driver performance using the characteristic static output current curves for a low state (I/sub OL/) and high state (I/sub OH/) is presented. It offers a simplified alternative to complex theoretical models. This approach can be used to quickly evaluate the impact of a change in driver output on system performance, to determine the worst case performance, or to correlate experiments directly with a given test device. It requires that the I/sub OL/ and I/sub OH/, and the intrinsic transient time for the device be known. This information can be determined by measuring hardware, analyzing the output of a theoretical model, or summarizing data sheets.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324630
W. H. Furnas
An image capture system using a 2" vidicon camera, interface, video board and control software to allow an AT class personal computer to directly digitize an image with 2048*2048*8 bit pixels is described. The nature of the camera allows the entire area of the picture to be taken at once, even with a photo flash. After the exposure is complete, one half a second is required to transfer the image from the camera to the image board in the personal computer. There it can be viewed and enhanced immediately. The design objective is assembling a low cost 2 K*2 K resolution direct image capture system. To meet the objective inexpensive components were chosen. The components are tied together with software and control logic. Operation is simplified for the user with a dynamic pan step size and using a typical operating mode for subsampling to allow viewing the overall image. Hardware and software for obtaining the performance required for working with the 4 megabyte images created when taking a single picture are described.<>
{"title":"A PC-based 2 K*2 K direct imaging system","authors":"W. H. Furnas","doi":"10.1109/STIER.1990.324630","DOIUrl":"https://doi.org/10.1109/STIER.1990.324630","url":null,"abstract":"An image capture system using a 2\" vidicon camera, interface, video board and control software to allow an AT class personal computer to directly digitize an image with 2048*2048*8 bit pixels is described. The nature of the camera allows the entire area of the picture to be taken at once, even with a photo flash. After the exposure is complete, one half a second is required to transfer the image from the camera to the image board in the personal computer. There it can be viewed and enhanced immediately. The design objective is assembling a low cost 2 K*2 K resolution direct image capture system. To meet the objective inexpensive components were chosen. The components are tied together with software and control logic. Operation is simplified for the user with a dynamic pan step size and using a typical operating mode for subsampling to allow viewing the overall image. Hardware and software for obtaining the performance required for working with the 4 megabyte images created when taking a single picture are described.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324633
J.E. Thorner
The processing of signals received from an array of sensors, termed beamforming, can result in the improved performance of systems designed for the detection and estimation of propagating signals. Several approaches to sonar beamforming are presented. The basic concepts behind the beamforming of signals obtained from an array of sensors are presented and demonstrated. Conventional and modern beamforming approaches are motivated and defined, and the advantages and drawbacks of each are discussed. The potential power of modern beamforming techniques is illustrated through a computer simulation evaluating the ability of several beamforming techniques to resolve between two closely spaced sources. The need of beamforming algorithm evaluation in conditions characteristic of the undersea environment is highlighted.<>
{"title":"Approaches to sonar beamforming","authors":"J.E. Thorner","doi":"10.1109/STIER.1990.324633","DOIUrl":"https://doi.org/10.1109/STIER.1990.324633","url":null,"abstract":"The processing of signals received from an array of sensors, termed beamforming, can result in the improved performance of systems designed for the detection and estimation of propagating signals. Several approaches to sonar beamforming are presented. The basic concepts behind the beamforming of signals obtained from an array of sensors are presented and demonstrated. Conventional and modern beamforming approaches are motivated and defined, and the advantages and drawbacks of each are discussed. The potential power of modern beamforming techniques is illustrated through a computer simulation evaluating the ability of several beamforming techniques to resolve between two closely spaced sources. The need of beamforming algorithm evaluation in conditions characteristic of the undersea environment is highlighted.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133722404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-04-25DOI: 10.1109/STIER.1990.324638
P. De Nardo, S.A. La Page, E.J. Staniulis
IBM's Distributed Automation Edition, (DAE) is a software platform that provides an application programmer with a set of services to be used in developing applications. The communication system (CS/2) provides the application programmer a base on which applications for a distributed manufacturing operation can be developed and integrated into a consistent enterprise. The LAN communication services provided in the CS/2 feature of DAE are described. CS/2 provides a comprehensive set of services that allows developers to configure a system specifically to their needs. It supplies the tools for managing data, devices, and resources in a distributed integrated environment. All services are configurable to meet the operational requirements. CS/2 provides an application program, interface for obtaining services, that relieve application developers of the need to concern themselves with details of many unique communication protocols and hardware interfaces. Through the use of control blocks, CS/2 binds logical resource names to the physical destinations. This provides network transparency to the application programmer.<>
{"title":"Network communications with DAE 1.0","authors":"P. De Nardo, S.A. La Page, E.J. Staniulis","doi":"10.1109/STIER.1990.324638","DOIUrl":"https://doi.org/10.1109/STIER.1990.324638","url":null,"abstract":"IBM's Distributed Automation Edition, (DAE) is a software platform that provides an application programmer with a set of services to be used in developing applications. The communication system (CS/2) provides the application programmer a base on which applications for a distributed manufacturing operation can be developed and integrated into a consistent enterprise. The LAN communication services provided in the CS/2 feature of DAE are described. CS/2 provides a comprehensive set of services that allows developers to configure a system specifically to their needs. It supplies the tools for managing data, devices, and resources in a distributed integrated environment. All services are configurable to meet the operational requirements. CS/2 provides an application program, interface for obtaining services, that relieve application developers of the need to concern themselves with details of many unique communication protocols and hardware interfaces. Through the use of control blocks, CS/2 binds logical resource names to the physical destinations. This provides network transparency to the application programmer.<<ETX>>","PeriodicalId":166693,"journal":{"name":"IEEE Technical Conference on Southern Tier","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132242138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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