Pub Date : 1999-08-09DOI: 10.1109/MTDT.1999.782681
Sue Brown, Jeff Campbell, Sherri Griffin, D. James, R. Haythornthwaite
Construction analysis is a useful tool to determine microcircuit structure and identify potential failure mechanisms. Cross sectioning procedures used in construction analysis have revealed two possible failure mechanisms. One mechanism involving the use of SOG results in poor adhesion and delamination. The other mechanism permits the corrosion of internal conductors through a combination of discontinuities in the passivation at growth boundaries and internal damage.
{"title":"Failure mechanisms detected in memory chips during routine construction analysis","authors":"Sue Brown, Jeff Campbell, Sherri Griffin, D. James, R. Haythornthwaite","doi":"10.1109/MTDT.1999.782681","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782681","url":null,"abstract":"Construction analysis is a useful tool to determine microcircuit structure and identify potential failure mechanisms. Cross sectioning procedures used in construction analysis have revealed two possible failure mechanisms. One mechanism involving the use of SOG results in poor adhesion and delamination. The other mechanism permits the corrosion of internal conductors through a combination of discontinuities in the passivation at growth boundaries and internal damage.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-09DOI: 10.1109/MTDT.1999.782682
Jun Zhao, F. Meyer, F. Lombardi
This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ).
{"title":"Interconnect diagnosis of bus-connected multi-RAM systems","authors":"Jun Zhao, F. Meyer, F. Lombardi","doi":"10.1109/MTDT.1999.782682","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782682","url":null,"abstract":"This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Different testing objectives (detection and maximal diagnosis) are considered. An extensive analysis of the faults is pursued to characterize their impact on the BCMRS as well as on the test operations (such as WRITE and READ).","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-09DOI: 10.1109/MTDT.1999.782684
D. Malone
This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7LM copper BEOL technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (i) SRAM operability in product-like clocking and ABIST environments. (ii) Demonstration of yield using 2-dimensional redundancy. (iii) Characterization of SRAM signals used in the macro timing rules. (iv) Obtain high volume pre-product manufacturing test experience. (v) Verify SRAM functionality at technology stress test conditions. Prototype test chips in IBM's .18 /spl mu/m technology have provided opportunities to investigate these areas, greatly mitigate risks associated with ever decreasing product design cycles and exercise the SRAM timing rules and logic models in a product-like application.
{"title":"Design validation of .18 /spl mu/m 1 GHz cache and register arrays","authors":"D. Malone","doi":"10.1109/MTDT.1999.782684","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782684","url":null,"abstract":"This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7LM copper BEOL technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (i) SRAM operability in product-like clocking and ABIST environments. (ii) Demonstration of yield using 2-dimensional redundancy. (iii) Characterization of SRAM signals used in the macro timing rules. (iv) Obtain high volume pre-product manufacturing test experience. (v) Verify SRAM functionality at technology stress test conditions. Prototype test chips in IBM's .18 /spl mu/m technology have provided opportunities to investigate these areas, greatly mitigate risks associated with ever decreasing product design cycles and exercise the SRAM timing rules and logic models in a product-like application.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-09DOI: 10.1109/MTDT.1999.782679
D. Rhodes, W. Wolf
The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at a particular level is fixed, it is easily shown that at least one divided cache structure exists for which the miss-rate is the same as a single unified cache. By using alternate implementations, however, the method may provide a significant decrease in miss-rates as is shown via simulations. Specifically, SPEC95 benchmarks are used to demonstrate that the technique is effective for general usage but it may be even more useful for embedded systems where memory access patterns can be more fully controlled (i.e. via the compiler). In addition to improved miss-rates, another advantage is that the hit-time for multiple smaller caches may be smaller than for a single larger cache. Disadvantageous, but readily surmountable, electrical aspects are also discussed.
{"title":"Unbalanced cache systems","authors":"D. Rhodes, W. Wolf","doi":"10.1109/MTDT.1999.782679","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782679","url":null,"abstract":"The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at a particular level is fixed, it is easily shown that at least one divided cache structure exists for which the miss-rate is the same as a single unified cache. By using alternate implementations, however, the method may provide a significant decrease in miss-rates as is shown via simulations. Specifically, SPEC95 benchmarks are used to demonstrate that the technique is effective for general usage but it may be even more useful for embedded systems where memory access patterns can be more fully controlled (i.e. via the compiler). In addition to improved miss-rates, another advantage is that the hit-time for multiple smaller caches may be smaller than for a single larger cache. Disadvantageous, but readily surmountable, electrical aspects are also discussed.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129387722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-09DOI: 10.1109/MTDT.1999.782690
G. Birk, D. Elliott, B. Cockburn
Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. (1989) and the noise cancellation techniques of a MLDRAM proposed by Gillingham (1996). Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons.
{"title":"A comparative simulation study of four multilevel DRAMs","authors":"G. Birk, D. Elliott, B. Cockburn","doi":"10.1109/MTDT.1999.782690","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782690","url":null,"abstract":"Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM schemes, along with a new MLDRAM scheme that combines the speed of a MLDRAM proposed by Furuyama et al. (1989) and the noise cancellation techniques of a MLDRAM proposed by Gillingham (1996). Our SPICE simulation models use the same array size and process models for each to allow us to make direct comparisons.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MTDT.1999.782689
D.P. van der Velde, A.J. v.d. Goor
In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000.
{"title":"Designing a memory module tester","authors":"D.P. van der Velde, A.J. v.d. Goor","doi":"10.1109/MTDT.1999.782689","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782689","url":null,"abstract":"In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114938694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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