Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573594
Michelle Lim, M. Islam, S. Jahariah, K. H. Yeo, S. Ali
This paper provides a comparison of low voltage design strategies in charge pumps that may be used with micro-power energy harvesters. The focus is on low input voltage (<; 500 mV) for possible cold start in monolithic integration. An overview of published low voltage techniques in charge pump designs are presented in four perspectives: body effect, gate voltages, MOS threshold voltage and power losses. Based on these four perspectives, latch-based charge pumps are constructed to compare the effects of several low voltage strategies on the charge pumps' performances. These charge pumps are simulated in two-stages using the common TSMC180nm CMOS technology. This results in the enhanced gate voltage (also lower conduction losses) and threshold lowering schemes having the fastest ramp-up of 10-20ms while zero-body effect scheme providing best voltage pumping efficiency > 90% for 100-500mV input voltage ranges. The results will help designers to achieve optimum low voltage operation in specific charge pump performance metrics.
{"title":"Comparison of latch-based charge pumps using low voltage strategies in energy harvesting applications","authors":"Michelle Lim, M. Islam, S. Jahariah, K. H. Yeo, S. Ali","doi":"10.1109/SMELEC.2016.7573594","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573594","url":null,"abstract":"This paper provides a comparison of low voltage design strategies in charge pumps that may be used with micro-power energy harvesters. The focus is on low input voltage (<; 500 mV) for possible cold start in monolithic integration. An overview of published low voltage techniques in charge pump designs are presented in four perspectives: body effect, gate voltages, MOS threshold voltage and power losses. Based on these four perspectives, latch-based charge pumps are constructed to compare the effects of several low voltage strategies on the charge pumps' performances. These charge pumps are simulated in two-stages using the common TSMC180nm CMOS technology. This results in the enhanced gate voltage (also lower conduction losses) and threshold lowering schemes having the fastest ramp-up of 10-20ms while zero-body effect scheme providing best voltage pumping efficiency > 90% for 100-500mV input voltage ranges. The results will help designers to achieve optimum low voltage operation in specific charge pump performance metrics.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573633
Chiew Ching Tan, P. Tan
In this paper, we studied the effect of mechanical stress due to Shallow Trench Isolation (STI) on the channel length direction (x-stress) and channel width direction (y-stress) by adopting two different channel orientations; <;110> and <;100>. When change from <;110> to <;100> channel orientation, PMOS sensitivity to both STI x-stress and y-stress reduces. For NMOS, both the channel orientations show the similar STI x-stress and y-stress effects. STI x-stress effects of NMOS and PMOS is contradicting. Hence, by adopting <;100> channel, the performance of PMOS can be improved without degrading the NMOS performance. The STI x-stress and y-stress effects on NMOS and PMOS transistors with <;110> and <;100> channel orientation are explained by using the electron and hole energy valleys diagrams.
{"title":"Shallow Trench Isolation stress effect on CMOS transistors with different channel orientations","authors":"Chiew Ching Tan, P. Tan","doi":"10.1109/SMELEC.2016.7573633","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573633","url":null,"abstract":"In this paper, we studied the effect of mechanical stress due to Shallow Trench Isolation (STI) on the channel length direction (x-stress) and channel width direction (y-stress) by adopting two different channel orientations; <;110> and <;100>. When change from <;110> to <;100> channel orientation, PMOS sensitivity to both STI x-stress and y-stress reduces. For NMOS, both the channel orientations show the similar STI x-stress and y-stress effects. STI x-stress effects of NMOS and PMOS is contradicting. Hence, by adopting <;100> channel, the performance of PMOS can be improved without degrading the NMOS performance. The STI x-stress and y-stress effects on NMOS and PMOS transistors with <;110> and <;100> channel orientation are explained by using the electron and hole energy valleys diagrams.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134026382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573589
N. Zamani, A. Zain, B. Majlis
This paper presents the simulation of a photonic crystal (PhC) cavity in low index contrast materials- Gallium Nitride on the sapphire substrate using two-dimensional (2D) Finite Difference Time Domain method (FDTD). We have performed the simulation based on H1 PhC configurations with the variation of lattice constant. We have obtained the quality factor of approximately 2200 and 1700 at the wavelength in the range of 486 and 483 nm respectively, which are suitable for operation of the blue laser. This configuration will be used as a basic building block for Lab-on-Chip (LoC) biosensors.
{"title":"Modelling of 2-D Gallium Nitride (GaN) photonic crystal","authors":"N. Zamani, A. Zain, B. Majlis","doi":"10.1109/SMELEC.2016.7573589","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573589","url":null,"abstract":"This paper presents the simulation of a photonic crystal (PhC) cavity in low index contrast materials- Gallium Nitride on the sapphire substrate using two-dimensional (2D) Finite Difference Time Domain method (FDTD). We have performed the simulation based on H1 PhC configurations with the variation of lattice constant. We have obtained the quality factor of approximately 2200 and 1700 at the wavelength in the range of 486 and 483 nm respectively, which are suitable for operation of the blue laser. This configuration will be used as a basic building block for Lab-on-Chip (LoC) biosensors.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127436184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573621
Noor Alia Binti Nor Hashim, Fazrena Azlee binti Hamid, J. Teo, M. Hamid
Maintaining the security of communication is very crucial nowadays. It is important in cryptographic security to have strong keys and is secretive. Random number generators are used to combat this problem by producing different and unique identification for each user in a network. Memristors has been studied as a potential tool in hardware security because of its energy efficiency and the nanotechnology fabrication process variations is more unique and random than the traditional complementary metal-oxide-semiconductor (CMOS) processes. This paper analyzes a memristor based ring oscillator random number generator design and how the relationship between the frequency and resistor or memristor affects the randomness of the generator and the implementations of this device in security application. It was concluded that as the resistor values increases, frequency of the signal decreases and Vout will also increased.
{"title":"Analysis of memristor based ring oscillators for hardware security","authors":"Noor Alia Binti Nor Hashim, Fazrena Azlee binti Hamid, J. Teo, M. Hamid","doi":"10.1109/SMELEC.2016.7573621","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573621","url":null,"abstract":"Maintaining the security of communication is very crucial nowadays. It is important in cryptographic security to have strong keys and is secretive. Random number generators are used to combat this problem by producing different and unique identification for each user in a network. Memristors has been studied as a potential tool in hardware security because of its energy efficiency and the nanotechnology fabrication process variations is more unique and random than the traditional complementary metal-oxide-semiconductor (CMOS) processes. This paper analyzes a memristor based ring oscillator random number generator design and how the relationship between the frequency and resistor or memristor affects the randomness of the generator and the implementations of this device in security application. It was concluded that as the resistor values increases, frequency of the signal decreases and Vout will also increased.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127526295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573661
A. Khalid, M. A. Mohamed, B. Majlis, M. Azam
We report graphene growth on polycrystalline Cobalt (Co) films by using induced coupled plasma RF-PECVD at 800°C temperature with 40 W plasma power. We also do the comparison by growing with and without plasma to observe the contribution of plasma in graphene growth on Cobalt films. Results show that the existence of plasma helps graphene formation meanwhile the existence of graphene is not observed with the absence of plasma. Plasma power is proven to generate high energy for decomposing methane forming radical carbon for the graphene growth mechanism. The as-grown graphene was characterized by using Raman Spectroscopy and Atomic force microscopy (AFM). The graphene was identified as multilayer from the Raman spectra. With the aid of plasma and proper optimization of the growth condition, the number of graphene layers can be tailored for low temperature substrate.
{"title":"Characterization of graphene growth using RF-PECVD on Cobalt films","authors":"A. Khalid, M. A. Mohamed, B. Majlis, M. Azam","doi":"10.1109/SMELEC.2016.7573661","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573661","url":null,"abstract":"We report graphene growth on polycrystalline Cobalt (Co) films by using induced coupled plasma RF-PECVD at 800°C temperature with 40 W plasma power. We also do the comparison by growing with and without plasma to observe the contribution of plasma in graphene growth on Cobalt films. Results show that the existence of plasma helps graphene formation meanwhile the existence of graphene is not observed with the absence of plasma. Plasma power is proven to generate high energy for decomposing methane forming radical carbon for the graphene growth mechanism. The as-grown graphene was characterized by using Raman Spectroscopy and Atomic force microscopy (AFM). The graphene was identified as multilayer from the Raman spectra. With the aid of plasma and proper optimization of the growth condition, the number of graphene layers can be tailored for low temperature substrate.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132901342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573640
D. Berhanuddin, M. Lourenço, R. Gwilliam, K. Homewood
We report a new approach of generating the dicarbon G-centre on silicon substrates by utilizing technique that is fully compatible with the standard silicon ultra-large-scale integration (ULSI) technology. Silicon wafers were implanted with carbon and irradiated with high energy protons to produce self-interstitials that are crucial in the formation of the G-centre. Prior to that, all the samples were pre-amorphised with germanium. Photoluminescence (PL) measurements at 80 K were carried out to investigate the point defect mediated luminescence of the G-centre with a wavelength of 1280 nm. The results show a prominent, sharp luminescence at the carbon related, G centre in majority of the samples.
{"title":"Photoluminescence study of the optically active, G-centre on pre-amorphised silicon by utilizing ion implantation technique","authors":"D. Berhanuddin, M. Lourenço, R. Gwilliam, K. Homewood","doi":"10.1109/SMELEC.2016.7573640","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573640","url":null,"abstract":"We report a new approach of generating the dicarbon G-centre on silicon substrates by utilizing technique that is fully compatible with the standard silicon ultra-large-scale integration (ULSI) technology. Silicon wafers were implanted with carbon and irradiated with high energy protons to produce self-interstitials that are crucial in the formation of the G-centre. Prior to that, all the samples were pre-amorphised with germanium. Photoluminescence (PL) measurements at 80 K were carried out to investigate the point defect mediated luminescence of the G-centre with a wavelength of 1280 nm. The results show a prominent, sharp luminescence at the carbon related, G centre in majority of the samples.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128787363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573575
K. Ibrahim
Manufacturing contributes more than 80% of Malaysia's exports in 2016, with Integrated Circuits (IC) making-up a major portion of this. According to recent SEMI projections, semiconductors continue to grow by 17% in 2017, across various technology nodes. SilTerra, a home-grown semiconductor foundry, is a relatively small player, by global standards. However, it is a significant contributor to value-added semiconductor exports for Malaysia. So, moving forward, can smaller foundries like SilTerra sustain and be competitive to remain significant? This topic will be discussed and some proposals will be shared on how various parties can work together to ensure the industry is sustainable. Sustainability is a key factor to succeed in this highly competitive industry. This effort involves every stakeholder within the ecosystem. If this collaboration is not done in a timely fashion, the semiconductor industry in Malaysia will likely fall behind other countries that are proactively positioning themselves as more productive and efficient.
{"title":"Made in Malaysia Integrated Circuits, how far can we go?","authors":"K. Ibrahim","doi":"10.1109/SMELEC.2016.7573575","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573575","url":null,"abstract":"Manufacturing contributes more than 80% of Malaysia's exports in 2016, with Integrated Circuits (IC) making-up a major portion of this. According to recent SEMI projections, semiconductors continue to grow by 17% in 2017, across various technology nodes. SilTerra, a home-grown semiconductor foundry, is a relatively small player, by global standards. However, it is a significant contributor to value-added semiconductor exports for Malaysia. So, moving forward, can smaller foundries like SilTerra sustain and be competitive to remain significant? This topic will be discussed and some proposals will be shared on how various parties can work together to ensure the industry is sustainable. Sustainability is a key factor to succeed in this highly competitive industry. This effort involves every stakeholder within the ecosystem. If this collaboration is not done in a timely fashion, the semiconductor industry in Malaysia will likely fall behind other countries that are proactively positioning themselves as more productive and efficient.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124228800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573600
M. Aziz, F. Salehuddin, A. Zain, K. Kaharudin, H. Hazura, S. Idris, A. R. Hanim, Z. Manap
The short-channel effect (SCE) is the main problem of many metal-oxide-semiconductor field-effect transistor (MOSFET) industries. A lot of studies addressing the SCE effect have been conducted. One of the methods used for this is called SOI (silicon-on-insulator) technology. This method has been proven to effectively reduce the SCE effect. In this research paper, the electrical characteristic of an 18 nm gate length SOI PMOSFET was analyzed based on the prediction of the International Technology Roadmap for Semiconductors (ITRS). The threshold voltage would be the key characteristic in this research. Four process parameters were used with two noise factors in order to conduct nine sets of experiments using the L9 orthogonal array Taguchi method. At the end of the experiment, the best setting that was predicted by the Taguchi method would be utilized for the purpose of verification. The result shows that VTH after the optimization approach is closer to the nominal value (-0.533V), that is, within the appropriate range of ITRS 2013.
{"title":"Analyze of threshold voltage in SOI PMOSFET device using Taguchi method","authors":"M. Aziz, F. Salehuddin, A. Zain, K. Kaharudin, H. Hazura, S. Idris, A. R. Hanim, Z. Manap","doi":"10.1109/SMELEC.2016.7573600","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573600","url":null,"abstract":"The short-channel effect (SCE) is the main problem of many metal-oxide-semiconductor field-effect transistor (MOSFET) industries. A lot of studies addressing the SCE effect have been conducted. One of the methods used for this is called SOI (silicon-on-insulator) technology. This method has been proven to effectively reduce the SCE effect. In this research paper, the electrical characteristic of an 18 nm gate length SOI PMOSFET was analyzed based on the prediction of the International Technology Roadmap for Semiconductors (ITRS). The threshold voltage would be the key characteristic in this research. Four process parameters were used with two noise factors in order to conduct nine sets of experiments using the L9 orthogonal array Taguchi method. At the end of the experiment, the best setting that was predicted by the Taguchi method would be utilized for the purpose of verification. The result shows that VTH after the optimization approach is closer to the nominal value (-0.533V), that is, within the appropriate range of ITRS 2013.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131968460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573645
K. Joseph
An unique type of residues with ring shape was detected at high topography metal surface after the via etch process, which is plasma dry etching with the combination of isotropic etch and anisotropic etch. This process needs to etch through the Inter Metal Dielectric (IMD) stack consists of High Density Plasma (HDP) Undoped Silicate Glass (USG), SIlicon Oxy-Nitride (SION) and TetraEthylOrthoSilicate (TEOS). This ring shape residues formed during the isotropic etch and could not be etched away in the subsequent anisotropic etch, and it was found to be induced by the significant etch rate differences between TEOS and SION, coupled with the fluctuations in the TEOS thickness and the isotropic etch rate. The detailed mechanism on the formation of this ring shape residue and the solution to this issue are discussed in this paper. The solution has been proven to be effective with no trace of via ring shape residues since the implementation.
{"title":"Mechanism of via residues with unique ring shape","authors":"K. Joseph","doi":"10.1109/SMELEC.2016.7573645","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573645","url":null,"abstract":"An unique type of residues with ring shape was detected at high topography metal surface after the via etch process, which is plasma dry etching with the combination of isotropic etch and anisotropic etch. This process needs to etch through the Inter Metal Dielectric (IMD) stack consists of High Density Plasma (HDP) Undoped Silicate Glass (USG), SIlicon Oxy-Nitride (SION) and TetraEthylOrthoSilicate (TEOS). This ring shape residues formed during the isotropic etch and could not be etched away in the subsequent anisotropic etch, and it was found to be induced by the significant etch rate differences between TEOS and SION, coupled with the fluctuations in the TEOS thickness and the isotropic etch rate. The detailed mechanism on the formation of this ring shape residue and the solution to this issue are discussed in this paper. The solution has been proven to be effective with no trace of via ring shape residues since the implementation.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116061037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-01DOI: 10.1109/SMELEC.2016.7573637
N. F. Murat, W. M. Mukhtar, A. Rashid, K. A. Dasuki, A. A. R. A. Yussuf
Nowadays, surface plasmon resonance (SPR) sensor has been widely used in biosensing applications to detect the wide diversity of biomolecular interactions. There are few parameters need to be concerned in order to optimize the performance of SPR sensors such as film thicknesses, type of thin films and their configurations. In this study, we seek to determine the optimum thicknesses of hybrid thin films which consist of gold-graphene oxide layers for the enhancement of SPR sensor sensitivity. By using a theoretical approach, a WINSPALL 3.02 simulator had been used to investigate the effects of various thicknesses of hybrid configuration's thin films towards the excitation of surface plasmon polaritons (SPP). A layer of 3 nm protein was added to compare the maximum adsorption of the SPR sensor based on their configuration. It was found that the optimum thicknesses of gold and graphene oxide are 50 nm and 0.68 nm respectively for achieving best sensitivity. Thus, the sensitivity value for gold-GO thin films is higher than silver-GO which are 19.42 °/RIU and 5.45 °/RIU with FWHM = 2.28° and 0.64° respectively.
{"title":"Optimization of gold thin films thicknesses in enhancing SPR response","authors":"N. F. Murat, W. M. Mukhtar, A. Rashid, K. A. Dasuki, A. A. R. A. Yussuf","doi":"10.1109/SMELEC.2016.7573637","DOIUrl":"https://doi.org/10.1109/SMELEC.2016.7573637","url":null,"abstract":"Nowadays, surface plasmon resonance (SPR) sensor has been widely used in biosensing applications to detect the wide diversity of biomolecular interactions. There are few parameters need to be concerned in order to optimize the performance of SPR sensors such as film thicknesses, type of thin films and their configurations. In this study, we seek to determine the optimum thicknesses of hybrid thin films which consist of gold-graphene oxide layers for the enhancement of SPR sensor sensitivity. By using a theoretical approach, a WINSPALL 3.02 simulator had been used to investigate the effects of various thicknesses of hybrid configuration's thin films towards the excitation of surface plasmon polaritons (SPP). A layer of 3 nm protein was added to compare the maximum adsorption of the SPR sensor based on their configuration. It was found that the optimum thicknesses of gold and graphene oxide are 50 nm and 0.68 nm respectively for achieving best sensitivity. Thus, the sensitivity value for gold-GO thin films is higher than silver-GO which are 19.42 °/RIU and 5.45 °/RIU with FWHM = 2.28° and 0.64° respectively.","PeriodicalId":169983,"journal":{"name":"2016 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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