Pub Date : 1962-12-01DOI: 10.1109/TEC.1962.5219462
W. Carr, A. Milnes
A three-terminal network consisting of two matched tunnel diodes and a fixed resistor is introduced as a basic element for performing peak threshold summation logic. The characteristic between two terminals resembles a tunnel diode curve where application of a signal or bias current to the third terminal causes reduction of the observed peak current. Decrease of this peak current below a fixed load line allows switching from the low- to the high-voltage state for logic-function circuit operation. Such bias-controlled tunnel pairs are shown to be unilateral to a considerable extent (30 db). This is advantageous in logic networks since it allows directional flow of information without the provision of multiphase power supplies or backward diodes, as needed in conventional tunnel diode logic circuits to eliminate back-switching. Circuits are described based on this principle, consisting entirely of tunnel junctions and resistors, for performing OR, MAJORITY, AND and NOR logic. Generalized design equations for circuits with a fan-in of M and a fan-out of N are derived. Test circuits based upon the generalized equations with a fan-in of 9 and a fan-out of 5 were found to operate over a temperature range from ?70° to +60°C. A sample switching speed measurement for an OR gate using 1-ma tunnel diodes and a normal degree of drive showed a 7.5-nsec rise time which was triple that observed with a single tunnel diode under similar conditions.
{"title":"Bias-Controlled Tunnel-Pair Logic Circuits","authors":"W. Carr, A. Milnes","doi":"10.1109/TEC.1962.5219462","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219462","url":null,"abstract":"A three-terminal network consisting of two matched tunnel diodes and a fixed resistor is introduced as a basic element for performing peak threshold summation logic. The characteristic between two terminals resembles a tunnel diode curve where application of a signal or bias current to the third terminal causes reduction of the observed peak current. Decrease of this peak current below a fixed load line allows switching from the low- to the high-voltage state for logic-function circuit operation. Such bias-controlled tunnel pairs are shown to be unilateral to a considerable extent (30 db). This is advantageous in logic networks since it allows directional flow of information without the provision of multiphase power supplies or backward diodes, as needed in conventional tunnel diode logic circuits to eliminate back-switching. Circuits are described based on this principle, consisting entirely of tunnel junctions and resistors, for performing OR, MAJORITY, AND and NOR logic. Generalized design equations for circuits with a fan-in of M and a fan-out of N are derived. Test circuits based upon the generalized equations with a fan-in of 9 and a fan-out of 5 were found to operate over a temperature range from ?70° to +60°C. A sample switching speed measurement for an OR gate using 1-ma tunnel diodes and a normal degree of drive showed a 7.5-nsec rise time which was triple that observed with a single tunnel diode under similar conditions.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219440
L. Calabi, J. A. Riley
{"title":"Inessentiality in Minimal Networks and Formulas","authors":"L. Calabi, J. A. Riley","doi":"10.1109/TEC.1962.5219440","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219440","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"36 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121005473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219423
H. Yamada
Three notions are introduced: 1) a class of logic nets with ``disjunctively linear structure,'' 2) ``disjunctively linear behavior'' or logic nets, and 3) ``position diagrams'' to represent logic nets. Through the study of their properties, it is shown that there is a close relationship between disjunctively linear structures and the behavior of logic nets. It is then shown that the state diagrams of Moore and Mealy and the regular expression of Kleene can be considered as particular manifestations of the notion of disjunctive linearity. By means of the notion of disjunctive linearity, a unified treatment is given to state diagrams by Mealy and the logic nets constructed by Copi, Elgot, and Wright from regular expressions. Finally, a discussion is given to the normal form and the position diagram providing a technique for describing disjunctively linear logic nets. Some problems, such as the practical application of disjunctively linear logic nets for hazard-free operation and the minimization of regular expressions through the use of position diagrams, are suggested.
{"title":"Disjunctively Linear Logic Nets","authors":"H. Yamada","doi":"10.1109/TEC.1962.5219423","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219423","url":null,"abstract":"Three notions are introduced: 1) a class of logic nets with ``disjunctively linear structure,'' 2) ``disjunctively linear behavior'' or logic nets, and 3) ``position diagrams'' to represent logic nets. Through the study of their properties, it is shown that there is a close relationship between disjunctively linear structures and the behavior of logic nets. It is then shown that the state diagrams of Moore and Mealy and the regular expression of Kleene can be considered as particular manifestations of the notion of disjunctive linearity. By means of the notion of disjunctive linearity, a unified treatment is given to state diagrams by Mealy and the logic nets constructed by Copi, Elgot, and Wright from regular expressions. Finally, a discussion is given to the normal form and the position diagram providing a technique for describing disjunctively linear logic nets. Some problems, such as the practical application of disjunctively linear logic nets for hazard-free operation and the minimization of regular expressions through the use of position diagrams, are suggested.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114064031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219424
I. J. Gabelman
The synthesis of a threshold element which realizes a desired Boolean function as its output may be accomplished by solving a basic set of linear inequalities. The determination of this basic set is discussed with the aid of a geometric interpretation of such realizable functions on the vertices of a unit N cube. A solution may be obtained to these inequalities by linear programming. In this paper, a method of synthesis which lends itself to rapid and simple hand computation is given.
{"title":"The Synthesis of Boolean Functions Using a Single rrhreshold Element","authors":"I. J. Gabelman","doi":"10.1109/TEC.1962.5219424","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219424","url":null,"abstract":"The synthesis of a threshold element which realizes a desired Boolean function as its output may be accomplished by solving a basic set of linear inequalities. The determination of this basic set is discussed with the aid of a geometric interpretation of such realizable functions on the vertices of a unit N cube. A solution may be obtained to these inequalities by linear programming. In this paper, a method of synthesis which lends itself to rapid and simple hand computation is given.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132884955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219427
Charles H. Wolff
An efficient error correction code for correcting errors of one kind in an arbitrary N-character message is discussed. The coded check character is obtained by summing the weighted coded characters (columns of binary digits where each binary digit assumes a unique weight) within an entire record modulo a prime integer. This check character is then added to the record before transmission over a channel (e.g., magnetic tape). A single parity check is appended to each character of the record to make possible single error detection per character. The received message, perturbed by noise in a constant position or single track, is decoded by again adding up the received information plus check characters in a modulo p counter. Error location is achieved by solving for x in the expression ax mod p, when a, the number of parity checks that failed, and ax mod p, the contents of a mod p counter, are known. This type of residue check may be employed to indicate which track is in error. Thus, error correction can be performed on the characters containig parity check failures.
讨论了一种有效的纠错码，用于纠错任意n字符报文中的一类错误。编码校验字符是通过将整个记录中的加权编码字符(每个二进制数字都有一个唯一的权重的二进制列)对素数取模而得到的。在通过通道(如磁带)传输之前，将这个校验字符添加到记录中。单个奇偶校验被附加到记录的每个字符上，以便对每个字符进行单个错误检测。接收到的信息在恒定位置或单轨道上受到噪声的干扰，通过在模p计数器中再次将接收到的信息加上校验字符相加来解码。错误定位是通过在表达式ax mod p中求解x来实现的，当a(失败的奇偶校验次数)和ax mod p (mod p计数器的内容)已知时。这种类型的残留检查可以用来指示哪条轨道是错误的。因此，可以对包含奇偶校验失败的字符执行纠错。
{"title":"Coding for Multiple Asymmetric Errors in One Channel of a Multichannel System","authors":"Charles H. Wolff","doi":"10.1109/TEC.1962.5219427","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219427","url":null,"abstract":"An efficient error correction code for correcting errors of one kind in an arbitrary N-character message is discussed. The coded check character is obtained by summing the weighted coded characters (columns of binary digits where each binary digit assumes a unique weight) within an entire record modulo a prime integer. This check character is then added to the record before transmission over a channel (e.g., magnetic tape). A single parity check is appended to each character of the record to make possible single error detection per character. The received message, perturbed by noise in a constant position or single track, is decoded by again adding up the received information plus check characters in a modulo p counter. Error location is achieved by solving for x in the expression ax mod p, when a, the number of parity checks that failed, and ax mod p, the contents of a mod p counter, are known. This type of residue check may be employed to indicate which track is in error. Thus, error correction can be performed on the characters containig parity check failures.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130926173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219432
A. Rubin
It is shown in this paper how a straightforward solution to the regression problem can be obtained for continuous variables on a general-purpose analog computer. The linear case (least squares straight line) is thoroughly described. A specific nonlinear problem, that of estimating the parameters of a missile trajectory, is also described. The regression equations are derived and analog computer circuits for the solution are drawn. It is also shown that the steepest descent technique for parameter optimization is essentially the same technique as the classical statistical methods of multivariate regression analysis, but that significant analog computer circuit simplification occurs in using the steepest descent technique applied directly to the objective function.
{"title":"Continuous Regression Techniques Using Analog Computers","authors":"A. Rubin","doi":"10.1109/TEC.1962.5219432","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219432","url":null,"abstract":"It is shown in this paper how a straightforward solution to the regression problem can be obtained for continuous variables on a general-purpose analog computer. The linear case (least squares straight line) is thoroughly described. A specific nonlinear problem, that of estimating the parameters of a missile trajectory, is also described. The regression equations are derived and analog computer circuits for the solution are drawn. It is also shown that the steepest descent technique for parameter optimization is essentially the same technique as the classical statistical methods of multivariate regression analysis, but that significant analog computer circuit simplification occurs in using the steepest descent technique applied directly to the objective function.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219434
A. L. Vivatson, W. Slemmer
{"title":"Comments on \"Real-Time Analog-Digital Computation\"","authors":"A. L. Vivatson, W. Slemmer","doi":"10.1109/TEC.1962.5219434","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219434","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115024510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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