Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219438
S. Geller
A technique is described for making the internal base-to-emitter junction characteristics of an alloy junction transistor available to an analog computer simulation process. This is accomplished with an active feedback network that continuously compensates for the internal voltage drop across the extrinsic base-spreading resistance at all base current levels.
{"title":"Obtaining the Internal Junction Characteristics of a Transistor for Use in Analog Simulation","authors":"S. Geller","doi":"10.1109/TEC.1962.5219438","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219438","url":null,"abstract":"A technique is described for making the internal base-to-emitter junction characteristics of an alloy junction transistor available to an analog computer simulation process. This is accomplished with an active feedback network that continuously compensates for the internal voltage drop across the extrinsic base-spreading resistance at all base current levels.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130889680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219422
D. Armstrong
A set of procedures for assigning codes to internal states of a synchronous sequential machine so as to minimize the internal logic in two-level form is proposed. The procedures are based on interpreting the state table of a sequential machine as a set of mappings from present states into next states, under control of the inputs. Attention is focused on a particular subset of these mappings, called pr mappings. A numerical score is assigned to each pr mapping, which is a measure of the desirability of ``selecting'' the mapping for inclusion in a ``basic set'' of mappings. A basic set has the property of determining a unique code assignment (within a symmetry of the cube of internal states). The procedures are applied to a 3-stage shift register and result in the optimum encoding for that device. Finally, it is briefly indicated how three previous assignment methods, including one developed by the author, are related to those described here. Algorithms are presented for some but not all of the proposed procedures. These algorithms must be completed before the proposals can be implemented by a computer program.
{"title":"On the Efficient Assignment of Internal Codes to Sequential Machines","authors":"D. Armstrong","doi":"10.1109/TEC.1962.5219422","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219422","url":null,"abstract":"A set of procedures for assigning codes to internal states of a synchronous sequential machine so as to minimize the internal logic in two-level form is proposed. The procedures are based on interpreting the state table of a sequential machine as a set of mappings from present states into next states, under control of the inputs. Attention is focused on a particular subset of these mappings, called pr mappings. A numerical score is assigned to each pr mapping, which is a measure of the desirability of ``selecting'' the mapping for inclusion in a ``basic set'' of mappings. A basic set has the property of determining a unique code assignment (within a symmetry of the cube of internal states). The procedures are applied to a 3-stage shift register and result in the optimum encoding for that device. Finally, it is briefly indicated how three previous assignment methods, including one developed by the author, are related to those described here. Algorithms are presented for some but not all of the proposed procedures. These algorithms must be completed before the proposals can be implemented by a computer program.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133991867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219433
Clement Green, H. D'Hoop, André Debroux
This paper describes the working of the APACHE (Analog Programing And CHEcking) system for the production of analog computer programs using a digital computer, which has been developed jointly by digital and analog programers at the computation center of EURATOM in Ispra, Italy. The language which has been formulated for the writing of analog problems is discussed and its rules are set out in the Appendix, while the processes involved in the utilization of the program are described and illustrated by an example of the listing of the digital computer input and output for a range of equation types. Finally, the significance of this new programing system in terms of economic exploitation of the analog machine, the use of trained personnel, and the design of new computers, are considered briefly.
本文介绍了由意大利Ispra欧洲原子能机构(EURATOM)计算中心的数字编程人员和模拟编程人员共同开发的用数字计算机制作模拟计算机程序的APACHE (Analog programming And CHEcking)系统的工作原理。讨论了用于编写模拟问题的语言，并在附录中列出了其规则，同时通过一系列方程类型的数字计算机输入和输出列表的示例描述和说明了使用该程序所涉及的过程。最后，从模拟机的经济开发、训练有素的人员的使用和新型计算机的设计等方面简要地考虑了这种新的编程系统的意义。
{"title":"APACHE-A Breakthrough in Analog Computing","authors":"Clement Green, H. D'Hoop, André Debroux","doi":"10.1109/TEC.1962.5219433","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219433","url":null,"abstract":"This paper describes the working of the APACHE (Analog Programing And CHEcking) system for the production of analog computer programs using a digital computer, which has been developed jointly by digital and analog programers at the computation center of EURATOM in Ispra, Italy. The language which has been formulated for the writing of analog problems is discussed and its rules are set out in the Appendix, while the processes involved in the utilization of the program are described and illustrated by an example of the listing of the digital computer input and output for a range of equation types. Finally, the significance of this new programing system in terms of economic exploitation of the analog machine, the use of trained personnel, and the design of new computers, are considered briefly.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122296554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219429
J. Baldwin
When the flux in the driven branch of a multipath core is reversed most of it will return via the shortest return path in the core. A small fraction will return by the next shortest. The ratio of the flux change in the shortest path to that in the next shortest is called the branching ratio r. Experimental branching ratios are much larger than they reasonably should be. In this paper a magnetic circuit analysis which neglects leakage and reversible flux but includes the dependence of branch reluctance on flux is applied to the three-rung laddic. The calculations predict a branching ratio at infinite drive which is about a factor of two greater than might be naively expected. Except in special cases they predict that it should decrease monotonically with drive. Experimentally it may either increase, decrease, or saturate shortly after threshold. The experimental values are uniformly greater than the theoretical. It appears likely that the disparity between theory and experiment can be attributed to flux leakage during switching. This leakage may be minimized by silver plating the core. A remeasurement of the branching ratio as a function of drive and geometry seems to be indicated at the present time.
{"title":"Flux Reversal in Three-Rung Laddics","authors":"J. Baldwin","doi":"10.1109/TEC.1962.5219429","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219429","url":null,"abstract":"When the flux in the driven branch of a multipath core is reversed most of it will return via the shortest return path in the core. A small fraction will return by the next shortest. The ratio of the flux change in the shortest path to that in the next shortest is called the branching ratio r. Experimental branching ratios are much larger than they reasonably should be. In this paper a magnetic circuit analysis which neglects leakage and reversible flux but includes the dependence of branch reluctance on flux is applied to the three-rung laddic. The calculations predict a branching ratio at infinite drive which is about a factor of two greater than might be naively expected. Except in special cases they predict that it should decrease monotonically with drive. Experimentally it may either increase, decrease, or saturate shortly after threshold. The experimental values are uniformly greater than the theoretical. It appears likely that the disparity between theory and experiment can be attributed to flux leakage during switching. This leakage may be minimized by silver plating the core. A remeasurement of the branching ratio as a function of drive and geometry seems to be indicated at the present time.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"200 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219425
R. Teoste
The design of a repairable redundant computer is discussed using the Von Neumann multiplexing scheme. The general considerations, as well as the reasons for selecting this type of redundancy, are given. A reliability model of the redundant equipment is presented with resulting curves for estimating the reliability improvement and the additional cost of the redundant equipment. The mean time between failures of a typical redundant computer is shown to be several orders of magnitude greater than that of the nonredundant version of the same computer.
{"title":"Design of a Repairable Redundant Computer","authors":"R. Teoste","doi":"10.1109/TEC.1962.5219425","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219425","url":null,"abstract":"The design of a repairable redundant computer is discussed using the Von Neumann multiplexing scheme. The general considerations, as well as the reasons for selecting this type of redundancy, are given. A reliability model of the redundant equipment is presented with resulting curves for estimating the reliability improvement and the additional cost of the redundant equipment. The mean time between failures of a typical redundant computer is shown to be several orders of magnitude greater than that of the nonredundant version of the same computer.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219431
C. Chow
Within the framework of an early paper1 which considers character recognition as a statistical decision problem, the detailed structure of a recognition system can be systematically derived from the functional form of probability distributions. A binary matrix representation of signal is used in this paper. A nearest-neighbor dependence method is obtained by going beyond the usual assumption of statistical independence. The recognition network consists of three levels?a layer of AND gates, a set of linear summing networks in parallel, and a maximum selection circuit. Formulas for weights or recognition parameters are also derived, as logarithms of ratios of conditional probabilities. These formulas lead to a straightforward procedure of estimating weights from sample characters, which are then used in subsequent recognition. Simulation of the recognition method is performed on a digital computer. The program consists of two main operations-estimation of parameters from sample characters, and recognition using these estimated values. The experimental results indicate that the effect of neighbor dependence upon recognition performance is significant. On the basis of a rather small sample of 50 sets of hand-printed alphanumeric characters, the recognition performance of the nearest-neighbor method compares favorably with other recognition schemes.
{"title":"A Recognition Method Using Neighbor Dependence","authors":"C. Chow","doi":"10.1109/TEC.1962.5219431","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219431","url":null,"abstract":"Within the framework of an early paper1 which considers character recognition as a statistical decision problem, the detailed structure of a recognition system can be systematically derived from the functional form of probability distributions. A binary matrix representation of signal is used in this paper. A nearest-neighbor dependence method is obtained by going beyond the usual assumption of statistical independence. The recognition network consists of three levels?a layer of AND gates, a set of linear summing networks in parallel, and a maximum selection circuit. Formulas for weights or recognition parameters are also derived, as logarithms of ratios of conditional probabilities. These formulas lead to a straightforward procedure of estimating weights from sample characters, which are then used in subsequent recognition. Simulation of the recognition method is performed on a digital computer. The program consists of two main operations-estimation of parameters from sample characters, and recognition using these estimated values. The experimental results indicate that the effect of neighbor dependence upon recognition performance is significant. On the basis of a rather small sample of 50 sets of hand-printed alphanumeric characters, the recognition performance of the nearest-neighbor method compares favorably with other recognition schemes.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219426
F. Lee
A method is described for designing systems which automatically check themselves and give indications by which internal faults can be located quickly and accurately. Relatively little circuitry is required, and the performance of the test and fault location are easy. The proposed method entails the arrangement of a sequence of events which can be completed properly only if no malfunction exists. Applied to a 555-transistor digital system, the method yielded the following results: An indicator-light test and a 2.27-second self-check provide 100 per cent confidence that the device is in perfect order. 90 per cent of the trouble indications isolate faults to one or two plug-in cards, each holding one to six transistor circuits. This checking capability is provided by only 182. per cent of the transistors in the system.
{"title":"An Automatic Self-Checking and Fault-Locating Method","authors":"F. Lee","doi":"10.1109/TEC.1962.5219426","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219426","url":null,"abstract":"A method is described for designing systems which automatically check themselves and give indications by which internal faults can be located quickly and accurately. Relatively little circuitry is required, and the performance of the test and fault location are easy. The proposed method entails the arrangement of a sequence of events which can be completed properly only if no malfunction exists. Applied to a 555-transistor digital system, the method yielded the following results: An indicator-light test and a 2.27-second self-check provide 100 per cent confidence that the device is in perfect order. 90 per cent of the trouble indications isolate faults to one or two plug-in cards, each holding one to six transistor circuits. This checking capability is provided by only 182. per cent of the transistors in the system.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117167245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219430
F. Tsui
For the improvement of the performance of the sense-amplifier circuit for conventional ferrite-core memories, the principles of pre-amplification strobing and noise-matched clipping are proposed and discussed. A circuit incorporating these principles and achieving notable reliability and economy is described. The circuit is suitable for working with short cycle times and low signal-to-noise ratio values and can be used to process matrices of sizes considerably larger than 4096 cores.
{"title":"Improving the Performance of the Sense-Amplifier Circuit Through Pre-Amplification Strobing and Noise-Matched Clipping","authors":"F. Tsui","doi":"10.1109/TEC.1962.5219430","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219430","url":null,"abstract":"For the improvement of the performance of the sense-amplifier circuit for conventional ferrite-core memories, the principles of pre-amplification strobing and noise-matched clipping are proposed and discussed. A circuit incorporating these principles and achieving notable reliability and economy is described. The circuit is suitable for working with short cycle times and low signal-to-noise ratio values and can be used to process matrices of sizes considerably larger than 4096 cores.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126235409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219442
P. R. Bryant, R. Killick
{"title":"Correction to \"Nonlinear Feedback Shift Registers\"","authors":"P. R. Bryant, R. Killick","doi":"10.1109/TEC.1962.5219442","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219442","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115704149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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