Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407924
W. J. Wray
Now that standard Transistor Resistor Logic is well understood and widely used, the possibilities for reducing component count by changing the height of the switching threshold, as measured in units of input, are being explored. This paper presents the worst case design formulation, both steady-state and transient, for such variable-threshold circuitry. In addition there is a brief discussion of the logic represented. Numerical results illustrate the logical possibilities and the effect of increasing the threshold on transient behavior.
{"title":"Worst Case Design of Variable-Threshold TRL Circuits","authors":"W. J. Wray","doi":"10.1109/IRETELC.1962.5407924","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407924","url":null,"abstract":"Now that standard Transistor Resistor Logic is well understood and widely used, the possibilities for reducing component count by changing the height of the switching threshold, as measured in units of input, are being explored. This paper presents the worst case design formulation, both steady-state and transient, for such variable-threshold circuitry. In addition there is a brief discussion of the logic represented. Numerical results illustrate the logical possibilities and the effect of increasing the threshold on transient behavior.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133697094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407922
Peter G. Neumann
A noiseless matrix switch is a selection switch in which, for a given set of inputs, one corresponding output (the selected output) is nonzero while all other outputs are zero; the switch is load-sharing with efficiency one if all nonzero inputs contribute to the selected output with the same sign. This paper develops a general theory of noiseless load-sharing matrix switches, from which many new switches can be derived. Considerable design flexibility is thereby provided, with respect to the number of inputs, the types of input drivers, and the winding ratios. As an example, previous results (Chien) indicate that 20 inputs are required for a certain type of 16-output switch. The present re-results show that only 17 inputs are required.
{"title":"On the Logical Design of Noiseless Load-Sharing Matrix Switches","authors":"Peter G. Neumann","doi":"10.1109/IRETELC.1962.5407922","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407922","url":null,"abstract":"A noiseless matrix switch is a selection switch in which, for a given set of inputs, one corresponding output (the selected output) is nonzero while all other outputs are zero; the switch is load-sharing with efficiency one if all nonzero inputs contribute to the selected output with the same sign. This paper develops a general theory of noiseless load-sharing matrix switches, from which many new switches can be derived. Considerable design flexibility is thereby provided, with respect to the number of inputs, the types of input drivers, and the winding ratios. As an example, previous results (Chien) indicate that 20 inputs are required for a certain type of 16-output switch. The present re-results show that only 17 inputs are required.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128813729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407917
J. Brzozowski
This paper is an exposition of the theory of regular expressions and its applications to sequential circuits. The results of several authors are presented in a unified manner, pointing out the similarities and differences in the various treatments of the subject. Whenever possible, the terminology and notation of sequential circuit theory are used. The topics presented include: the relation of regular expressions to sequential circuits; algorithms for constructing sequential circuits and state diagrams corresponding to a given regular expression; methods for obtaining a regular expression from a state diagram of a sequential circuit, improper state diagrams, algebraic properties of regular expressions, and applications to codes.
{"title":"A Survey of Regular Expressions and Their Applications","authors":"J. Brzozowski","doi":"10.1109/IRETELC.1962.5407917","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407917","url":null,"abstract":"This paper is an exposition of the theory of regular expressions and its applications to sequential circuits. The results of several authors are presented in a unified manner, pointing out the similarities and differences in the various treatments of the subject. Whenever possible, the terminology and notation of sequential circuit theory are used. The topics presented include: the relation of regular expressions to sequential circuits; algorithms for constructing sequential circuits and state diagrams corresponding to a given regular expression; methods for obtaining a regular expression from a state diagram of a sequential circuit, improper state diagrams, algebraic properties of regular expressions, and applications to codes.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407920
R. Singleton
Designs for load-sharing zero-noise core switches have been proposed by Constantine, Marcus, and Chien. Blachman class has proposed a core memory wiring plan which with modification can be converted to a load-sharing zero-noise switch. An examination of these switch plans shows that they have a common relationship to a class of mathematical structures known to mathematicians and statisticians as balanced incomplete block designs. This relationship is formulated, and it is then shown that all balanced incomplete block designs lead to load-sharing zero-noise switches. Three methods of forming the winding matrix for a switch are given, and expressions for the load-sharing factor, set bias, and reset bias in terms of the balanced incomplete block design parameters are derived for each switch type. Similarly, partially balanced incomplete block designs are shown to lead to low-noise load-sharing switches. Switch operation under fault conditions is briefly discussed. Most of the known load-sharing core switch types can be viewed as based on either balanced or partially balanced incomplete block designs. A review of the available block designs indicates that a number of new switches can be based on these designs. A modification of a distributed memory model proposed by C. Rosen is discussed. With wiring plans based on block designs, it appears possible to construct very-large-capacity memory units which are relatively insensitive to wiring errors.
{"title":"Load-Sharing Core Switches Based on Block Designs","authors":"R. Singleton","doi":"10.1109/IRETELC.1962.5407920","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407920","url":null,"abstract":"Designs for load-sharing zero-noise core switches have been proposed by Constantine, Marcus, and Chien. Blachman class has proposed a core memory wiring plan which with modification can be converted to a load-sharing zero-noise switch. An examination of these switch plans shows that they have a common relationship to a class of mathematical structures known to mathematicians and statisticians as balanced incomplete block designs. This relationship is formulated, and it is then shown that all balanced incomplete block designs lead to load-sharing zero-noise switches. Three methods of forming the winding matrix for a switch are given, and expressions for the load-sharing factor, set bias, and reset bias in terms of the balanced incomplete block design parameters are derived for each switch type. Similarly, partially balanced incomplete block designs are shown to lead to low-noise load-sharing switches. Switch operation under fault conditions is briefly discussed. Most of the known load-sharing core switch types can be viewed as based on either balanced or partially balanced incomplete block designs. A review of the available block designs indicates that a number of new switches can be based on these designs. A modification of a distributed memory model proposed by C. Rosen is discussed. With wiring plans based on block designs, it appears possible to construct very-large-capacity memory units which are relatively insensitive to wiring errors.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132345242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407925
J. D. R. McQuillan
An examination of the properties of a pulse transmission matrix for a storage system is given in detail. An attempt is made to arrive at design criteria for a practical system. It appears that microstrip techniques afford an economic approach to the problem and that technically, impedances of the order of 50 ohms will present optimum over-all performance. Use of conductors of about 1 mm in width and electroformed earth shields separated by about 2 mm, will result in an access time less than 6 m? sec and a total physical size of less than a meter cube.
{"title":"The Design Problems of a Megabit Storage Matrix for Use in a High-Speed Computer","authors":"J. D. R. McQuillan","doi":"10.1109/IRETELC.1962.5407925","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407925","url":null,"abstract":"An examination of the properties of a pulse transmission matrix for a storage system is given in detail. An attempt is made to arrive at design criteria for a practical system. It appears that microstrip techniques afford an economic approach to the problem and that technically, impedances of the order of 50 ohms will present optimum over-all performance. Use of conductors of about 1 mm in width and electroformed earth shields separated by about 2 mm, will result in an access time less than 6 m? sec and a total physical size of less than a meter cube.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407931
D. S. Williams, J. Beckett
{"title":"Teaching Aid for \"Games That Teach the Fundamentals of Computer Operation\"","authors":"D. S. Williams, J. Beckett","doi":"10.1109/IRETELC.1962.5407931","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407931","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125617825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407926
Edgar C. Leaycraft, E. Melan
Design factors and operational features of a multiaperture ferrite memory core are discussed showing how a low coercive force, low switching coefficient material may be used for a high-speed coincident current storage device. The formulation, geometry, and important processing variables are given and a method of handling large numbers of asymmetrical cores for electrical test is described. Electromagnetic characteristics, pulse drive and bias test conditions are given. Data is presented showing the effect on core responses of varying net drive, pulse duration, half select drive and temperature. This device represents about a four-fold speed increase in comparison with present coincident current toroids.
{"title":"Characteristics of a High-Speed Multipath Core for a Coincident-Current Memory","authors":"Edgar C. Leaycraft, E. Melan","doi":"10.1109/IRETELC.1962.5407926","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407926","url":null,"abstract":"Design factors and operational features of a multiaperture ferrite memory core are discussed showing how a low coercive force, low switching coefficient material may be used for a high-speed coincident current storage device. The formulation, geometry, and important processing variables are given and a method of handling large numbers of asymmetrical cores for electrical test is described. Electromagnetic characteristics, pulse drive and bias test conditions are given. Data is presented showing the effect on core responses of varying net drive, pulse duration, half select drive and temperature. This device represents about a four-fold speed increase in comparison with present coincident current toroids.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"85 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127985431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407921
R. C. Minnick, J. Haynes
A number of the more commonly known magnetic core access switches are combined in a single analytical model. In addition to yielding as special cases the known access switches on which it is based, this model produces many apparently new switches. Relationships among the various parameters in this model are developed in such a way that the designer may choose the number of drivers, the load-sharing factor, the number of turns of wire per switch core and the magnitude of the maximum disturbing magnetomotive force within certain limits. Several methods are developed for economizing on the number of drivers used in switches, and certain special access switches are treated. The current knowledge is reviewed on a fairly recent and important class of access switches, known as load-sharing zero-noise switches. These switches are compared with one another, and a fundamental theorem is proved that such switches can have no more outputs than inputs. Several new classes of load-sharing zero-noise switches are developed and analyzed; in particular, switches are developed which allow more flexibility in the choice of the load-sharing factor than formerly was the case.
{"title":"Magnetic Core Access Switches","authors":"R. C. Minnick, J. Haynes","doi":"10.1109/IRETELC.1962.5407921","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407921","url":null,"abstract":"A number of the more commonly known magnetic core access switches are combined in a single analytical model. In addition to yielding as special cases the known access switches on which it is based, this model produces many apparently new switches. Relationships among the various parameters in this model are developed in such a way that the designer may choose the number of drivers, the load-sharing factor, the number of turns of wire per switch core and the magnitude of the maximum disturbing magnetomotive force within certain limits. Several methods are developed for economizing on the number of drivers used in switches, and certain special access switches are treated. The current knowledge is reviewed on a fairly recent and important class of access switches, known as load-sharing zero-noise switches. These switches are compared with one another, and a fundamental theorem is proved that such switches can have no more outputs than inputs. Several new classes of load-sharing zero-noise switches are developed and analyzed; in particular, switches are developed which allow more flexibility in the choice of the load-sharing factor than formerly was the case.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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