Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219428
W. Smith, A. Pohm
A transistor amplifier with nonlinear tunnel-diode or backward-diode feedback is described for use as a resistor-coupled threshold logic circuit or general purpose switch. The tunnel-diode feedback serves to virtually eliminate saturation and prevent cutoff thus allowing the high gain-bandwidth products of epitaxial switching transistors to be utilized at all times during switching. Switching plus delay times as low as 2 nsec have been observed with a fan in and fan out of three. Ring oscillator experiments show that delays per stage from 2 to 5 nsec are easily obtained with logical gains of two or three. The input impedance of the network is 3 to 12 ohms leading to a very practical threshold network. The particular logic decision is determined only by the bias current. Tolerance calculations are presented that indicate component requirements will not be severe. The peak current is not a critical parameter and can easily vary 100 per cent. Due to the quantizing effect of the tunnel-diode feedback, circuits with fan ins and fan outs of three would operate satisfactorily under worst case conditions with 2 per cent resistors and mild restrictions on the transistor and diode parameters. By adding backward diodes in series with the input resistors the tolerance requirements can be relaxed to 10 per cent resistors and slight restrictions on the diodes or transistor parameters. By using backward diodes the fan in and fan out can be substantially increased with little loss in speed.
{"title":"A New Approach to Resistor-Transistor-Tunnel-Diode Nanosecond Logic","authors":"W. Smith, A. Pohm","doi":"10.1109/TEC.1962.5219428","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219428","url":null,"abstract":"A transistor amplifier with nonlinear tunnel-diode or backward-diode feedback is described for use as a resistor-coupled threshold logic circuit or general purpose switch. The tunnel-diode feedback serves to virtually eliminate saturation and prevent cutoff thus allowing the high gain-bandwidth products of epitaxial switching transistors to be utilized at all times during switching. Switching plus delay times as low as 2 nsec have been observed with a fan in and fan out of three. Ring oscillator experiments show that delays per stage from 2 to 5 nsec are easily obtained with logical gains of two or three. The input impedance of the network is 3 to 12 ohms leading to a very practical threshold network. The particular logic decision is determined only by the bias current. Tolerance calculations are presented that indicate component requirements will not be severe. The peak current is not a critical parameter and can easily vary 100 per cent. Due to the quantizing effect of the tunnel-diode feedback, circuits with fan ins and fan outs of three would operate satisfactorily under worst case conditions with 2 per cent resistors and mild restrictions on the transistor and diode parameters. By adding backward diodes in series with the input resistors the tolerance requirements can be relaxed to 10 per cent resistors and slight restrictions on the diodes or transistor parameters. By using backward diodes the fan in and fan out can be substantially increased with little loss in speed.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129181683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-10-01DOI: 10.1109/TEC.1962.5219441
A. K. Choudhury, M. Basu
{"title":"A Mechanized Chart for Simplification of Switching Functions","authors":"A. K. Choudhury, M. Basu","doi":"10.1109/TEC.1962.5219441","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219441","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129858937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-08-01DOI: 10.1109/TEC.1962.5219391
John N. Mitchell
A method of computer multiplication and division is proposed which uses binary logarithms. The logarithm of a binary number may be determined approximately from the number itself by simple shifting and counting. A simple add or subtract and shift operation is all that is required to multiply or divide. Since the logarithms used are approximate there can be errors in the result. An error analysis is given and a means of reducing the error for the multiply operation is shown.
{"title":"Computer Multiplication and Division Using Binary Logarithms","authors":"John N. Mitchell","doi":"10.1109/TEC.1962.5219391","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219391","url":null,"abstract":"A method of computer multiplication and division is proposed which uses binary logarithms. The logarithm of a binary number may be determined approximately from the number itself by simple shifting and counting. A simple add or subtract and shift operation is all that is required to multiply or divide. Since the logarithms used are approximate there can be errors in the result. An error analysis is given and a means of reducing the error for the multiply operation is shown.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-08-01DOI: 10.1109/TEC.1962.5219402
R. C. Minnick
{"title":"Comments on \"The Use of the Simplex Algorithm in the Mechanization of Boolean Switching Functions by Means of Magnetic Cores","authors":"R. C. Minnick","doi":"10.1109/TEC.1962.5219402","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219402","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124689718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-08-01DOI: 10.1109/TEC.1962.5219386
I. B. Pyne, E. McCluskey
This paper is primarily concerned with finding, in the most efficient possible way, the set of all solutions to a cyclic prime implicant table. (A solution is a set of rows such that every column contains at least one marked entry in a row belonging to the set and such that no row can be deleted from the set without destroying this property.) Extensive use is made of the relationship between this and the problem of efficiently reducing a Boolean frontal function from the form of a product of sums of single literals to a sum of products. The transformation methods commonly in use today have the disadvantage that they tend to introduce duplicate and redundant products. (A redundant product includes at least one row which can be removed, and the remaining rows will still constitute a solution.) Several methods which appreciably reduce the number of such redundancies are presented. One of these methods (called row branching), applies repeatedly the algebraic transformation f = af(? = 1) + f(?= 0) where ? is the Boolean variable corresponding to a row of the table, and f is the function corresponding to the given table. The mechanism by which a redundant solution is generated is described. The paper includes other useful transformation procedures such as, for example, a tabular method in which redundancies are avoided systematically at each step.
{"title":"The Reduction of Redundancy in Solving Prime Implicant Tables","authors":"I. B. Pyne, E. McCluskey","doi":"10.1109/TEC.1962.5219386","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219386","url":null,"abstract":"This paper is primarily concerned with finding, in the most efficient possible way, the set of all solutions to a cyclic prime implicant table. (A solution is a set of rows such that every column contains at least one marked entry in a row belonging to the set and such that no row can be deleted from the set without destroying this property.) Extensive use is made of the relationship between this and the problem of efficiently reducing a Boolean frontal function from the form of a product of sums of single literals to a sum of products. The transformation methods commonly in use today have the disadvantage that they tend to introduce duplicate and redundant products. (A redundant product includes at least one row which can be removed, and the remaining rows will still constitute a solution.) Several methods which appreciably reduce the number of such redundancies are presented. One of these methods (called row branching), applies repeatedly the algebraic transformation f = af(? = 1) + f(?= 0) where ? is the Boolean variable corresponding to a row of the table, and f is the function corresponding to the given table. The mechanism by which a redundant solution is generated is described. The paper includes other useful transformation procedures such as, for example, a tabular method in which redundancies are avoided systematically at each step.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127974996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-08-01DOI: 10.1109/TEC.1962.5219395
T. Anderson
A technique for performing Stieltjes integration on an analog computer is developed. The particular class of integrator functions considered consists of those functions of bounded variation with a finite number of jump discontinuities. The desired results are achieved through the use of analog logic and memory circuits and an example given showing an application of the method.
{"title":"A Method for Evaluating Stieltjes Integrals on the Analog Computer","authors":"T. Anderson","doi":"10.1109/TEC.1962.5219395","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219395","url":null,"abstract":"A technique for performing Stieltjes integration on an analog computer is developed. The particular class of integrator functions considered consists of those functions of bounded variation with a finite number of jump discontinuities. The desired results are achieved through the use of analog logic and memory circuits and an example given showing an application of the method.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-08-01DOI: 10.1109/TEC.1962.5219390
Peter G. Neumann
Maximum-likelihood encoding and decoding procedures are presented for cyclic permutation error-correcting codes. These procedures take advantage of the cyclic permutation structure, and are applicable to all such codes. On the other hand, familiar parity-checking procedures are applicable only to those few cyclic permutation codes which are group codes. A comparison of the two different procedures for the group code case shows that they are roughly comparable in complexity.
{"title":"Encoding and Decoding for Cyclic Permutation Codes","authors":"Peter G. Neumann","doi":"10.1109/TEC.1962.5219390","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219390","url":null,"abstract":"Maximum-likelihood encoding and decoding procedures are presented for cyclic permutation error-correcting codes. These procedures take advantage of the cyclic permutation structure, and are applicable to all such codes. On the other hand, familiar parity-checking procedures are applicable only to those few cyclic permutation codes which are group codes. A comparison of the two different procedures for the group code case shows that they are roughly comparable in complexity.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114975295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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