Pub Date : 1962-06-01DOI: 10.1109/IRETELC.1962.5407923
J. A. Ekiss
The consideration of the transistor as a charge-controlled device as proposed by Beaufoy and Sparkes has proved to be a useful way, both conceptually and analytically, to view the transistor. In this paper the charge-control theory is applied to a number of problems of interest to switching circuit designers. The charge-control theory is briefly reviewed to provide a foundation for the problems considered. The theory is then applied to describe in detail the ``on-demand current gain'' s s and its effect on circuit design. The basic equations developed for switching times are applied to an RCTL circuit and equations for rise, storage and fall times are developed. The effect of stray capacitance on switching times is developed in a particularly simple and unique way.
{"title":"Applications of the Charge-Control Theory","authors":"J. A. Ekiss","doi":"10.1109/IRETELC.1962.5407923","DOIUrl":"https://doi.org/10.1109/IRETELC.1962.5407923","url":null,"abstract":"The consideration of the transistor as a charge-controlled device as proposed by Beaufoy and Sparkes has proved to be a useful way, both conceptually and analytically, to view the transistor. In this paper the charge-control theory is applied to a number of problems of interest to switching circuit designers. The charge-control theory is briefly reviewed to provide a foundation for the problems considered. The theory is then applied to describe in detail the ``on-demand current gain'' s s and its effect on circuit design. The basic equations developed for switching times are applied to an RCTL circuit and equations for rise, storage and fall times are developed. The effect of stray capacitance on switching times is developed in a particularly simple and unique way.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123762608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219347
Theodore M. Booth
The vertex frame is similar to an n-dimensional cube or Tychonoff frame that has been cut and unfolded into the shape of a Karnaugh map. The methods of use are similar to those for Karnaugh maps. Minimal disjunctive and conjunctive normal formulas are found for problems with or without don't-care cases. The selection graph, a linear graph, is used to enhance the prime antecedent (= prime implicant) selection procedure. The vertex frame readily handles most problems of up to six variables. Problems with seven and eight variables have been worked successfully, but this is an area where more experience is needed in working out actual problems that arise in engineering practice. As with any map method, pattern recognition plays an important role, and thus it takes longer to become proficient in this method than in some of the formula-manipulation methods (e.g., Quine's, McCluskey's, Mott's). The problem of recognizing plots, on a vertex frame, of symmetric and unate truth functions is discussed.
{"title":"The Vertex-Frame Method for Obtaining Minimal Proposition-Letter Formulas","authors":"Theodore M. Booth","doi":"10.1109/TEC.1962.5219347","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219347","url":null,"abstract":"The vertex frame is similar to an n-dimensional cube or Tychonoff frame that has been cut and unfolded into the shape of a Karnaugh map. The methods of use are similar to those for Karnaugh maps. Minimal disjunctive and conjunctive normal formulas are found for problems with or without don't-care cases. The selection graph, a linear graph, is used to enhance the prime antecedent (= prime implicant) selection procedure. The vertex frame readily handles most problems of up to six variables. Problems with seven and eight variables have been worked successfully, but this is an area where more experience is needed in working out actual problems that arise in engineering practice. As with any map method, pattern recognition plays an important role, and thus it takes longer to become proficient in this method than in some of the formula-manipulation methods (e.g., Quine's, McCluskey's, Mott's). The problem of recognizing plots, on a vertex frame, of symmetric and unate truth functions is discussed.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125582460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219361
I. Toda
{"title":"On the Number of Types of Self-Dual Logical Functions","authors":"I. Toda","doi":"10.1109/TEC.1962.5219361","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219361","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124498730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219353
H. Sobol
It is necessary to understand the static thermal properties of cryotron gates before one can predict the limitations associated with dissipative heating of a complex cryotronic computer. An experimental program has been conducted to determine the thermal properties of isolated and of thermally coupled gates. All experiments reported in this paper were performed on tin gates evaporated onto glass substrates. The total thermal conductance K of a gate is defined, and experimental values of K are presented as a function of power and gate geometry. An analysis of the heat flow is given, based on a temperature-dependent coefficient of heat transfer. Theoretical values of K and temperature distribution are derived. The theory qualitatively predicts the temperature variation. Finally, the results are extrapolated to estimate the number of cryotrons that can be used safely in a thermally coupled system.
{"title":"Time Average Thermal Properties of a Computer Utilizing Thin-Film Superconducting Elements","authors":"H. Sobol","doi":"10.1109/TEC.1962.5219353","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219353","url":null,"abstract":"It is necessary to understand the static thermal properties of cryotron gates before one can predict the limitations associated with dissipative heating of a complex cryotronic computer. An experimental program has been conducted to determine the thermal properties of isolated and of thermally coupled gates. All experiments reported in this paper were performed on tin gates evaporated onto glass substrates. The total thermal conductance K of a gate is defined, and experimental values of K are presented as a function of power and gate geometry. An analysis of the heat flow is given, based on a temperature-dependent coefficient of heat transfer. Theoretical values of K and temperature distribution are derived. The theory qualitatively predicts the temperature variation. Finally, the results are extrapolated to estimate the number of cryotrons that can be used safely in a thermally coupled system.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123504762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219349
Ronald M. Guffin
The design of a special-purpose digital computer for solving simultaneous equations which operates with numbers coded in the residue number system is described. Since addition, subtraction or multiplication can be done in one-bit time using this coding, Gauss-Seidel iteration can be done in a very fast and efficient manner. The computer has been arbitrarily designed to solve dense systems of equations with as many as 128 unknowns and sparse systems with as many as 512 unknowns. Operating at a 500-kc clock rate, the computer would be able to perform one complete iteration on a system with 128 unknowns 30 times faster than an IBM 704. Using a 7 digit residue code requiring a 42-bit word, the computer would provide solutions of up to 4 significant figures. By using the best presently obtainable components, computing speed can be increased by a factor of 5. The size of the system which can be handled and the number of significant digits which can be obtained in the solutions can also be extended if desired. The speed of computation obtained with this computer is made possible by the combination of the one-bit-time arithmetic operations obtainable with residue numbers, the high data rate possible with a magnetic drum, and the sequential nature of the Gauss-Seidel iteration procedure. The digital techniques which have been developed to realize a computer of this type include methods of encoding decimal numbers into residue representation, rescaling residue numbers, and decoding residue numbers into binary coded decimal form.
{"title":"A Computer for Solving Linear Simultaneous Equations Using the Residue Number System","authors":"Ronald M. Guffin","doi":"10.1109/TEC.1962.5219349","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219349","url":null,"abstract":"The design of a special-purpose digital computer for solving simultaneous equations which operates with numbers coded in the residue number system is described. Since addition, subtraction or multiplication can be done in one-bit time using this coding, Gauss-Seidel iteration can be done in a very fast and efficient manner. The computer has been arbitrarily designed to solve dense systems of equations with as many as 128 unknowns and sparse systems with as many as 512 unknowns. Operating at a 500-kc clock rate, the computer would be able to perform one complete iteration on a system with 128 unknowns 30 times faster than an IBM 704. Using a 7 digit residue code requiring a 42-bit word, the computer would provide solutions of up to 4 significant figures. By using the best presently obtainable components, computing speed can be increased by a factor of 5. The size of the system which can be handled and the number of significant digits which can be obtained in the solutions can also be extended if desired. The speed of computation obtained with this computer is made possible by the combination of the one-bit-time arithmetic operations obtainable with residue numbers, the high data rate possible with a magnetic drum, and the sequential nature of the Gauss-Seidel iteration procedure. The digital techniques which have been developed to realize a computer of this type include methods of encoding decimal numbers into residue representation, rescaling residue numbers, and decoding residue numbers into binary coded decimal form.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117010305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219354
C. Renton, B. Rabinovici
A full binary adder utilizing a single tunnel diode and three resistors as its basic components is described, the circuit design criteria is outlined and values for a typical case are computed. The operating rate of the adder was determined analytically to be approximately 3 nsec. Experimental results obtained with a practical circuit that employed a 1N2939 tunnel diode were in good agreement with the analytical findings. The Sum and Carry outputs were 130 mv and 300 mv, respectively. These outputs need to be amplified if used to drive identical stages since there is no gain in this circuit. Since a full binary adder is a multipurpose logic element, a simple, compact, full binary adder that contains few components presents attractive possibilities for new computer logical schemes. This adder offers circuit simplicity and stability and is particularly suitable for application where low-power dissipation and compactness are desired.
{"title":"Tunnel-Diode Full Binary Adder","authors":"C. Renton, B. Rabinovici","doi":"10.1109/TEC.1962.5219354","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219354","url":null,"abstract":"A full binary adder utilizing a single tunnel diode and three resistors as its basic components is described, the circuit design criteria is outlined and values for a typical case are computed. The operating rate of the adder was determined analytically to be approximately 3 nsec. Experimental results obtained with a practical circuit that employed a 1N2939 tunnel diode were in good agreement with the analytical findings. The Sum and Carry outputs were 130 mv and 300 mv, respectively. These outputs need to be amplified if used to drive identical stages since there is no gain in this circuit. Since a full binary adder is a multipurpose logic element, a simple, compact, full binary adder that contains few components presents attractive possibilities for new computer logical schemes. This adder offers circuit simplicity and stability and is particularly suitable for application where low-power dissipation and compactness are desired.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117252968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219356
T. Kilburn, D. Edwards, M. Lanigan, F. Sumner
After a brief survey of the basic Atlas machine, the paper describes an automatic system which in principle can be applied to any combination of two storage systems so that the combination can be regarded by the machine user as a single level. The actual system described relates to a fast core store-drum combination. The effect of the system on instruction times is illustrated, and the tape transfer system is also introduced since it fits basically in through the same hardware. The scheme incorporates a ``learning'' program, a technique which can be of greater importance in future computers.
{"title":"One-Level Storage System","authors":"T. Kilburn, D. Edwards, M. Lanigan, F. Sumner","doi":"10.1109/TEC.1962.5219356","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219356","url":null,"abstract":"After a brief survey of the basic Atlas machine, the paper describes an automatic system which in principle can be applied to any combination of two storage systems so that the combination can be regarded by the machine user as a single level. The actual system described relates to a fast core store-drum combination. The effect of the system on instruction times is illustrated, and the tape transfer system is also introduced since it fits basically in through the same hardware. The scheme incorporates a ``learning'' program, a technique which can be of greater importance in future computers.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134120687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219366
M. Fischler, E. Poe
uout t What is the effect if R is not made and maintained exactly equal to Ri? If R is larger a in L-COMPARATOR U out ItCES TO than Ri then the circuit exhibits customary LL| UH UI H e+9x>C_~ 4°/ > transition occurs for uip>uo, and alternately au s iY~08 w . the UH->UL transition for ui,,uo [Fig. 6(c)]. Since the ideal Fig. 1-Ideal comparator characteristic. condition [Fig. 6(b)] is embraced by these Fig. 5-Composite characteristic (simplified) of a tunneltwo cases, it can be attained exactly in princidiode pair whose diodes have electrical characteristics ple. In practice, a minute amount of hysteresis similar to those shown in Fig. 3. is, of course, inevitable. ;R For high-speed operation, freedom from hysteresis will depend on diode junction ca-
如果R不完全等于Ri，会有什么影响?如果L-COMPARATOR U out ItCES TO中的R比Ri大，则电路表现出惯常的LL / uu / uu +9x>C_~ 4°/ >跃迁，在upp > 0时发生跃迁，在y ~ 8w时交替发生跃迁。ui，，uo的UH->UL转换[图6(c)]。自理想图1-理想比较器特性。条件[图6(b)]包含在这些图5中。隧道的复合特性(简化)在两种情况下，可以精确地获得二极管具有电特性ple的原理二极管对。在实际应用中，与图3所示类似的微小迟滞量。当然，这是不可避免的。R对于高速运行，不受迟滞影响取决于二极管结ca
{"title":"Threshold Realization of Arithmetic Circuits","authors":"M. Fischler, E. Poe","doi":"10.1109/TEC.1962.5219366","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219366","url":null,"abstract":"uout t What is the effect if R is not made and maintained exactly equal to Ri? If R is larger a in L-COMPARATOR U out ItCES TO than Ri then the circuit exhibits customary LL| UH <E HIGH STATE H f.& 4 hysteresis [Fig. 6(a) ]. In this case, the UL-*>UI H e+9x>C_~ 4°/ > transition occurs for uip>uo, and alternately au s iY~08 w . the UH->UL transition for ui,,<uo. Conversely, '0v SWITCHES TO uf R is smaller than Ri, the situation is reversed LOW STATEu U L (S~'+ u) -u'~+ u2) so that UL--5U1 takes place for uiX<uo and --UL (uc' +ut) <.//(u'^+u2) -*UL for uii>uo [Fig. 6(c)]. Since the ideal Fig. 1-Ideal comparator characteristic. condition [Fig. 6(b)] is embraced by these Fig. 5-Composite characteristic (simplified) of a tunneltwo cases, it can be attained exactly in princidiode pair whose diodes have electrical characteristics ple. In practice, a minute amount of hysteresis similar to those shown in Fig. 3. is, of course, inevitable. ;R For high-speed operation, freedom from hysteresis will depend on diode junction ca-","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115210712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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