Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219352
E. J. Galli
The system design and evaluation of an experimental system are presented. The ``Stenowriter'' utilizes a special-purpose translation computer, equipped with a large random-access memory, to provide real-time processing of spoken material into typewritten English. The input is provided by an operator using a special keyboard with which information may be stenographically encoded as rapidly as it is spoken. The stenographic code is automatically processed by the translation system into corresponding English with proper spelling and format. The output appears on an electric typewriter. Through multiplexing techniques, information for a large number of input-output units can be processed, each on a real-time basis, by one computer.
{"title":"The StenowriterߞA System for the Lexical Processing of Stenotypy","authors":"E. J. Galli","doi":"10.1109/TEC.1962.5219352","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219352","url":null,"abstract":"The system design and evaluation of an experimental system are presented. The ``Stenowriter'' utilizes a special-purpose translation computer, equipped with a large random-access memory, to provide real-time processing of spoken material into typewritten English. The input is provided by an operator using a special keyboard with which information may be stenographically encoded as rapidly as it is spoken. The stenographic code is automatically processed by the translation system into corresponding English with proper spelling and format. The output appears on an electric typewriter. Through multiplexing techniques, information for a large number of input-output units can be processed, each on a real-time basis, by one computer.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219351
J. Atkin, N. B. Marple
A data-processing technique is described in which a function is evaluated by rapid interrogation of the given data for the presence of combinations of data variables giving rise to values of the function which are of interest. Testing unlabeled measurements from several observers to find data sets which satisfy a test function is discussed as an example. For many problems the required time is much shorter than that needed when processing is carried out by a high speed general purpose machine. Logical design and equipment requirements for solution of such a problem by data interrogation are discussed.
{"title":"Information Processing by Data Interrogation","authors":"J. Atkin, N. B. Marple","doi":"10.1109/TEC.1962.5219351","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219351","url":null,"abstract":"A data-processing technique is described in which a function is evaluated by rapid interrogation of the given data for the presence of combinations of data variables giving rise to values of the function which are of interest. Testing unlabeled measurements from several observers to find data sets which satisfy a test function is discussed as an example. For many problems the required time is much shorter than that needed when processing is carried out by a high speed general purpose machine. Logical design and equipment requirements for solution of such a problem by data interrogation are discussed.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124108167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219348
D. Cantor, G. Estrin, R. Turn
Sequential table look-up algorithms are proposed for the evaluation of ln x and exp x. Tables of pre-computed constants are utilized in transforming the argument into a range where the function may be approximated by a simpler polynomial. In the case of ln x, x is transformed so that it falls into a close neighborhood of 1; in the case of exp x, x is transformed to a close neighborhood of 0. These algorithms are particularly effective when mechanized so as to carry out the predetermined sequence of operations without waste manipulation. Such special purpose organization is reasonable within the variable structure part of UCLA's proposed Fixed-Plus-Variable structure computer, as the same equipment may be reorganized for use in other special purpose configurations at other times. In this paper the sequential table look-up algorithms and their speed advantages over existing subroutine approximation procedures are described. The design of special purpose configurations which leads to another factor of speed increase as compared to a stored program implementation of the algorithms is presented. The properties of the supervisory control which integrate the operation of the ``fixed structure'' general purpose computer and the ``variable structure'' special purpose configurations are specified and the over-all computational gains evaluated. An order-of-magnitude increase in speed compared to existing subroutines is predicted in both cases.
{"title":"Logarithmic and Exponential Function Evaluation in a Variable Structure Digital Computer","authors":"D. Cantor, G. Estrin, R. Turn","doi":"10.1109/TEC.1962.5219348","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219348","url":null,"abstract":"Sequential table look-up algorithms are proposed for the evaluation of ln x and exp x. Tables of pre-computed constants are utilized in transforming the argument into a range where the function may be approximated by a simpler polynomial. In the case of ln x, x is transformed so that it falls into a close neighborhood of 1; in the case of exp x, x is transformed to a close neighborhood of 0. These algorithms are particularly effective when mechanized so as to carry out the predetermined sequence of operations without waste manipulation. Such special purpose organization is reasonable within the variable structure part of UCLA's proposed Fixed-Plus-Variable structure computer, as the same equipment may be reorganized for use in other special purpose configurations at other times. In this paper the sequential table look-up algorithms and their speed advantages over existing subroutine approximation procedures are described. The design of special purpose configurations which leads to another factor of speed increase as compared to a stored program implementation of the algorithms is presented. The properties of the supervisory control which integrate the operation of the ``fixed structure'' general purpose computer and the ``variable structure'' special purpose configurations are specified and the over-all computational gains evaluated. An order-of-magnitude increase in speed compared to existing subroutines is predicted in both cases.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129125636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219364
P. R. Bryant, F. G. Heath, R. Killick
{"title":"Counting with Feedback Shift Registers by Means of a Jump Technique","authors":"P. R. Bryant, F. G. Heath, R. Killick","doi":"10.1109/TEC.1962.5219364","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219364","url":null,"abstract":"","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126383262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219345
S. Ginsburg
Numerous physical situations related to data processing are shown to be modeled by a mathematical entity called a quasi-machine. The situations described include 1) single inputs producing multiple outputs, 2) machines yielding no outputs upon insertion of certain inputs, 3) the retention of the last n outputs only, 4) ``erase left'' on tape, 5) different input routines doing the same work, and 6) certain types of asynchronous switching circuits. The first five may be modeled by quasi-machines with a special property, such quasi-machines being called abstract machines.
{"title":"Examples of Abstract Machines","authors":"S. Ginsburg","doi":"10.1109/TEC.1962.5219345","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219345","url":null,"abstract":"Numerous physical situations related to data processing are shown to be modeled by a mathematical entity called a quasi-machine. The situations described include 1) single inputs producing multiple outputs, 2) machines yielding no outputs upon insertion of certain inputs, 3) the retention of the last n outputs only, 4) ``erase left'' on tape, 5) different input routines doing the same work, and 6) certain types of asynchronous switching circuits. The first five may be modeled by quasi-machines with a special property, such quasi-machines being called abstract machines.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"57 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219344
W. Kilmer
The networks considered in this paper consist of n identical combinational logic cells connected in cascade through bi-directional discrete information channels. All switching is done synchronously with unit time delay through each cell. Three classes of networks are formed according to whether or not information flow in one direction along the cascade is dependent upon that in the other. Steady-state behavioral relationships between the three classes are discussed, and the class having mutually dependent information flow is shown to be the only one which can exhibit steady-state memory properties. The main object of the paper is to derive several theorems concerning these memory properties. The last section interprets some previous results of Hennie as a start on the transients and cycling problems.
{"title":"Iterative Switching Networks Composed of Combinational Cells","authors":"W. Kilmer","doi":"10.1109/TEC.1962.5219344","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219344","url":null,"abstract":"The networks considered in this paper consist of n identical combinational logic cells connected in cascade through bi-directional discrete information channels. All switching is done synchronously with unit time delay through each cell. Three classes of networks are formed according to whether or not information flow in one direction along the cascade is dependent upon that in the other. Steady-state behavioral relationships between the three classes are discussed, and the class having mutually dependent information flow is shown to be the only one which can exhibit steady-state memory properties. The main object of the paper is to derive several theorems concerning these memory properties. The last section interprets some previous results of Hennie as a start on the transients and cycling problems.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219346
K. Maitra
This paper studies a class of switching networks which are constructed by cascading two-input, single-output completely flexible binary logical cells. It is assumed that each cell can be adjusted at will in order that any one of the sixteen possible switching functions of its two binary inputs may be obtained at its single output lead. An n-input cascaded network is composed of n-l, two-input, single output logical cells. The inputs to a typical cell Ai consist of a signal variable Xi and the output ai from the preceding cell Ai-1. For the end cell A1 the inputs are the signal variables X0 and X1. The output is derived from the terminal cell An-1. In view of the growing interest in the area of ``self-organizing'' or ``adaptive'' switching networks, the study of the type of network just discussed seems to be pertinent. The results presented here are pertinent to typical n-input cascaded structures, and consist of characterization and enumeration of the class of all n-place realizable switching functions, test procedure for the determination of the realizability of arbitrary n-place switching functions, and finally determination of all possible cascaded structures for synthesis of realizable n-place switching functions. The paper develops some new techniques especially suited to the present study. These techniques may also hopefully find applications in other types of logic synthesis.
{"title":"Cascaded Switching Networks of Two-Input Flexible Cells","authors":"K. Maitra","doi":"10.1109/TEC.1962.5219346","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219346","url":null,"abstract":"This paper studies a class of switching networks which are constructed by cascading two-input, single-output completely flexible binary logical cells. It is assumed that each cell can be adjusted at will in order that any one of the sixteen possible switching functions of its two binary inputs may be obtained at its single output lead. An n-input cascaded network is composed of n-l, two-input, single output logical cells. The inputs to a typical cell Ai consist of a signal variable Xi and the output ai from the preceding cell Ai-1. For the end cell A1 the inputs are the signal variables X0 and X1. The output is derived from the terminal cell An-1. In view of the growing interest in the area of ``self-organizing'' or ``adaptive'' switching networks, the study of the type of network just discussed seems to be pertinent. The results presented here are pertinent to typical n-input cascaded structures, and consist of characterization and enumeration of the class of all n-place realizable switching functions, test procedure for the determination of the realizability of arbitrary n-place switching functions, and finally determination of all possible cascaded structures for synthesis of realizable n-place switching functions. The paper develops some new techniques especially suited to the present study. These techniques may also hopefully find applications in other types of logic synthesis.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134326640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219350
T. Marill
In the synthesis of switching circuits, a formal representation of the function to be realized by the circuit is first established and simplified as much as possible. Only then is construction of the circuit undertaken. It is argued that an analogous strategy should be followed in the synthesis of digital computer programs: the function to be realized by a program should first be established in a suitable formalism; the resulting formal expression should then be simplified as much as possible; only at this point should translation into the final ``machine'' program be undertaken. In the light of this discussion, the simplification of a certain type of elementary program, containing no branching or internal modification, is considered in detail. It is argued that the analysis of this type of program, whose formalization is called a ``computational chain,'' is a prerequisite to the analysis of more general programs. A system of notation is developed, and rules are given for minimizing the temporary storage requirements associated with a computational chain, for eliminating vacuous and redundant parts, and for forming combinations of chains.
{"title":"Computational Chains and the Simplification of Computer Programs","authors":"T. Marill","doi":"10.1109/TEC.1962.5219350","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219350","url":null,"abstract":"In the synthesis of switching circuits, a formal representation of the function to be realized by the circuit is first established and simplified as much as possible. Only then is construction of the circuit undertaken. It is argued that an analogous strategy should be followed in the synthesis of digital computer programs: the function to be realized by a program should first be established in a suitable formalism; the resulting formal expression should then be simplified as much as possible; only at this point should translation into the final ``machine'' program be undertaken. In the light of this discussion, the simplification of a certain type of elementary program, containing no branching or internal modification, is considered in detail. It is argued that the analysis of this type of program, whose formalization is called a ``computational chain,'' is a prerequisite to the analysis of more general programs. A system of notation is developed, and rules are given for minimizing the temporary storage requirements associated with a computational chain, for eliminating vacuous and redundant parts, and for forming combinations of chains.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133737064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219360
G. P. Steck
A stochastic model is presented which gives the probabilities of successful recognition of the Browning-Bledsoe recognition scheme as a function of scheme parameters and pattern variability parameters. Also, procedures are given for estimating the variability parameters from data so that the model can be used to predict readability. The adequacy of the model is checked by comparing estimated readability with observed readability for two sets of data, one with high variability and one with low variability. The Browning-Bledsoe recognition scheme is also treated as a coding and decoding problem in which case the concepts of information theory are useful. Finally, brief mention is made of the connection between pattern recognition problems and classification problems in general, and the Browning-Bledsoe recognition scheme is compared and contrasted with other recognition schemes which make use of measurements on patterns.
{"title":"Stochastic Model for the Browning-Bledsoe Pattern Recognition Scheme","authors":"G. P. Steck","doi":"10.1109/TEC.1962.5219360","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219360","url":null,"abstract":"A stochastic model is presented which gives the probabilities of successful recognition of the Browning-Bledsoe recognition scheme as a function of scheme parameters and pattern variability parameters. Also, procedures are given for estimating the variability parameters from data so that the model can be used to predict readability. The adequacy of the model is checked by comparing estimated readability with observed readability for two sets of data, one with high variability and one with low variability. The Browning-Bledsoe recognition scheme is also treated as a coding and decoding problem in which case the concepts of information theory are useful. Finally, brief mention is made of the connection between pattern recognition problems and classification problems in general, and the Browning-Bledsoe recognition scheme is compared and contrasted with other recognition schemes which make use of measurements on patterns.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1962-04-01DOI: 10.1109/TEC.1962.5219355
J. Baldwin
Circuits which are analogous to multipath magnetic cores are described. Toroidal cores are employed to simulate the branches of the multipath core. The conservation of flux at a node is simulated by means of shorted windings connecting groups of cores. These insure that the sum of the flux changes in the cores on a given winding will vanish. Ampere's law is simulated by proper choice of both number of turns and core dimensions. Equations are derived which determine the parameters of the analog in terms of those of the multipath core. These state that the volume of a core must be proportional to the volume of the corresponding branch, that the number of turns a shorted winding makes on a core should be proportional to the ratio of core diameter to branch length, and that the number of ampere-turns of externally supplied drive should also be proportional to this ratio. Analog circuits employing single-turn coupling loops and cores of different diameters are discussed as a special case. Another special case employs multiturn windings but identical cores. It is shown that the current flowing in a shorted winding is proportional to the magnetic potential of the corresponding node of the multipath core. The use of the core analog for the direct observation of internodal magnetic potential differences is illustrated by means of oscilloscope photographs of the magnetic potential difference between the nodes of a three-rung laddic.
{"title":"Circuits Employing Toroidal Magnetic Cores as Analogs of Multipath Cores","authors":"J. Baldwin","doi":"10.1109/TEC.1962.5219355","DOIUrl":"https://doi.org/10.1109/TEC.1962.5219355","url":null,"abstract":"Circuits which are analogous to multipath magnetic cores are described. Toroidal cores are employed to simulate the branches of the multipath core. The conservation of flux at a node is simulated by means of shorted windings connecting groups of cores. These insure that the sum of the flux changes in the cores on a given winding will vanish. Ampere's law is simulated by proper choice of both number of turns and core dimensions. Equations are derived which determine the parameters of the analog in terms of those of the multipath core. These state that the volume of a core must be proportional to the volume of the corresponding branch, that the number of turns a shorted winding makes on a core should be proportional to the ratio of core diameter to branch length, and that the number of ampere-turns of externally supplied drive should also be proportional to this ratio. Analog circuits employing single-turn coupling loops and cores of different diameters are discussed as a special case. Another special case employs multiturn windings but identical cores. It is shown that the current flowing in a shorted winding is proportional to the magnetic potential of the corresponding node of the multipath core. The use of the core analog for the direct observation of internodal magnetic potential differences is illustrated by means of oscilloscope photographs of the magnetic potential difference between the nodes of a three-rung laddic.","PeriodicalId":177496,"journal":{"name":"IRE Trans. Electron. Comput.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1962-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126621607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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