Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655934
Yi-Min Jiang, K. Cheng
We present an integer-linear-programming-based approach for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. It produces the exact solutions for the maximum instantaneous current for small circuits, and tight upper bounds for large circuits. We formulate the maximum instantaneous current estimation problem as an integer linear programming (ILP) problem, and solve the corresponding ILP formulae to obtain the exact solution. For large circuits we propose to partition the circuits, and apply our ILP-based approach for each sub-circuit. The sum of the exact solutions of all sub-circuits provides an upper bound of the exact solution for the entire circuit. Our experimental results show that the upper bounds produced by our approach combined with the lower bounds produced by a genetic-algorithm-based approach confine the exact solution to a small range.
{"title":"Exact and approximate estimation for maximum instantaneous current of CMOS circuits","authors":"Yi-Min Jiang, K. Cheng","doi":"10.1109/DATE.1998.655934","DOIUrl":"https://doi.org/10.1109/DATE.1998.655934","url":null,"abstract":"We present an integer-linear-programming-based approach for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. It produces the exact solutions for the maximum instantaneous current for small circuits, and tight upper bounds for large circuits. We formulate the maximum instantaneous current estimation problem as an integer linear programming (ILP) problem, and solve the corresponding ILP formulae to obtain the exact solution. For large circuits we propose to partition the circuits, and apply our ILP-based approach for each sub-circuit. The sum of the exact solutions of all sub-circuits provides an upper bound of the exact solution for the entire circuit. Our experimental results show that the upper bounds produced by our approach combined with the lower bounds produced by a genetic-algorithm-based approach confine the exact solution to a small range.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121683579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655853
V. Yarmolik, S. Hellebrand, H. Wunderlich
After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the module-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.
{"title":"Self-adjusting output data compression: An efficient BIST technique for RAMs","authors":"V. Yarmolik, S. Hellebrand, H. Wunderlich","doi":"10.1109/DATE.1998.655853","DOIUrl":"https://doi.org/10.1109/DATE.1998.655853","url":null,"abstract":"After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the module-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"209 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122431656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655985
P. Nordholz, H. Grabinski, D. Treytnar, J. Otterstedt, D. Niggemeyer, U. Arz, T. Williams
Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 /spl mu/m technology will be given. The geometric data for the interconnects in 0.10 /spl mu/m technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.
{"title":"Core interconnect testing hazards","authors":"P. Nordholz, H. Grabinski, D. Treytnar, J. Otterstedt, D. Niggemeyer, U. Arz, T. Williams","doi":"10.1109/DATE.1998.655985","DOIUrl":"https://doi.org/10.1109/DATE.1998.655985","url":null,"abstract":"Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 /spl mu/m technology will be given. The geometric data for the interconnects in 0.10 /spl mu/m technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655850
M. Mutz
Several hardware compilers on the market convert from so-called RT level VHDL subsets to logic level descriptions. Such models still need clock signals and the notion of physical time in order to be executable. In a stage of a top-down design starting from the algorithmic level, register transfers are considered where the timing is not controlled by clock signals and where physical time is not yet relevant. We propose an executable VHDL subset for such register transfer models.
{"title":"Register transfer level VHDL models without clocks","authors":"M. Mutz","doi":"10.1109/DATE.1998.655850","DOIUrl":"https://doi.org/10.1109/DATE.1998.655850","url":null,"abstract":"Several hardware compilers on the market convert from so-called RT level VHDL subsets to logic level descriptions. Such models still need clock signals and the notion of physical time in order to be executable. In a stage of a top-down design starting from the algorithmic level, register transfers are considered where the timing is not controlled by clock signals and where physical time is not yet relevant. We propose an executable VHDL subset for such register transfer models.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123057330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655881
V. Chandramouli, J. Whittemore, K. Sakallah
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project that aims to provide such a foundation for functional timing analysis. As part of this work we have developed an abstract automaton based delay model that accounts for the various analog factors affecting delay, such as signal slopes, near simultaneous switching, etc., while at the same rime accounting for circuit functionality. This paper presents this delay model.
{"title":"AFTA: A formal delay model for functional timing analysis","authors":"V. Chandramouli, J. Whittemore, K. Sakallah","doi":"10.1109/DATE.1998.655881","DOIUrl":"https://doi.org/10.1109/DATE.1998.655881","url":null,"abstract":"Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project that aims to provide such a foundation for functional timing analysis. As part of this work we have developed an abstract automaton based delay model that accounts for the various analog factors affecting delay, such as signal slopes, near simultaneous switching, etc., while at the same rime accounting for circuit functionality. This paper presents this delay model.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124797312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655909
R. Freund, P. Feldmann
This paper introduces SyMPVL, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit. The algorithm employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices. These matrices determine a matrix-Pade approximation of the multi-port transfer function, and can serve as a reduced-order model of the original circuit. They can be "stamped" directly into the Jacobian matrix of a SPICE-type circuit simulator, or can be used to synthesize an equivalent smaller circuit. We also prove stability and passivity of the reduced-order models in the RL, RC, and LC special cases, and report numerical results for SyMPVL applied to example circuits.
{"title":"Reduced-order modeling of large linear passive multi-terminal circuits using matrix-Pade approximation","authors":"R. Freund, P. Feldmann","doi":"10.1109/DATE.1998.655909","DOIUrl":"https://doi.org/10.1109/DATE.1998.655909","url":null,"abstract":"This paper introduces SyMPVL, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit. The algorithm employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices. These matrices determine a matrix-Pade approximation of the multi-port transfer function, and can serve as a reduced-order model of the original circuit. They can be \"stamped\" directly into the Jacobian matrix of a SPICE-type circuit simulator, or can be used to synthesize an equivalent smaller circuit. We also prove stability and passivity of the reduced-order models in the RL, RC, and LC special cases, and report numerical results for SyMPVL applied to example circuits.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655939
L. Bisdounis, O. Koufopavlou, C. Goutis, S. Nikolaidis
In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.
{"title":"Switching response modeling of the CMOS inverter for sub-micron devices","authors":"L. Bisdounis, O. Koufopavlou, C. Goutis, S. Nikolaidis","doi":"10.1109/DATE.1998.655939","DOIUrl":"https://doi.org/10.1109/DATE.1998.655939","url":null,"abstract":"In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub-micron regime, is presented. A detailed analysis of the inverter operation is provided which results in accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129476405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655893
Holger Keding, Markus Willems, Martin Coors, H. Meyr
Digital systems, especially those for mobile applications are sensitive to power consumption, chip size and costs. Therefore they are realized using fixed-point architectures, either dedicated HW or programmable DSPs. On the other hand, system design starts from a floating-point description. These requirements have been the motivation for FRIDGE, a design environment for the specification, evaluation and implementation of fixed-point systems. FRIDGE offers a seamless design flow from a floating-point description to a fixed point implementation. Within this paper we focus on two core capabilities of FRIDGE: (1) the concept of an interactive, automated transformation of floating-point programs written in ANSI-C into fixed-point specifications, based on an interpolative approach. The design time reductions that can be achieved make FRIDGE a key component for an efficient HW/SW-codesign; (2) a fast fixed-point simulation that performs comprehensive compile-time analyses, reducing simulation time by one order of magnitude compared to existing approaches.
{"title":"FRIDGE: a fixed-point design and simulation environment","authors":"Holger Keding, Markus Willems, Martin Coors, H. Meyr","doi":"10.1109/DATE.1998.655893","DOIUrl":"https://doi.org/10.1109/DATE.1998.655893","url":null,"abstract":"Digital systems, especially those for mobile applications are sensitive to power consumption, chip size and costs. Therefore they are realized using fixed-point architectures, either dedicated HW or programmable DSPs. On the other hand, system design starts from a floating-point description. These requirements have been the motivation for FRIDGE, a design environment for the specification, evaluation and implementation of fixed-point systems. FRIDGE offers a seamless design flow from a floating-point description to a fixed point implementation. Within this paper we focus on two core capabilities of FRIDGE: (1) the concept of an interactive, automated transformation of floating-point programs written in ANSI-C into fixed-point specifications, based on an interpolative approach. The design time reductions that can be achieved make FRIDGE a key component for an efficient HW/SW-codesign; (2) a fast fixed-point simulation that performs comprehensive compile-time analyses, reducing simulation time by one order of magnitude compared to existing approaches.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655879
J. Rabaey, M. Wan
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a variety of the macromodules (micro-processors, DSPs, programmable logic and embedded memories) are being reported by a number of companies. Most of these systems target the embedded market where speed, area, and power requirements are paramount, and a balance between hardware and software implementation is needed. Reconfigurable computing devices have recently emerged as one of the major alternative implementation approaches, addressing most of the requirements outlined above.
{"title":"An energy-conscious exploration methodology for reconfigurable DSPs","authors":"J. Rabaey, M. Wan","doi":"10.1109/DATE.1998.655879","DOIUrl":"https://doi.org/10.1109/DATE.1998.655879","url":null,"abstract":"As the \"system-on-a-chip\" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a variety of the macromodules (micro-processors, DSPs, programmable logic and embedded memories) are being reported by a number of companies. Most of these systems target the embedded market where speed, area, and power requirements are paramount, and a balance between hardware and software implementation is needed. Reconfigurable computing devices have recently emerged as one of the major alternative implementation approaches, addressing most of the requirements outlined above.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127803612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-23DOI: 10.1109/DATE.1998.655991
M. Ringe, T. Lindenkreuz, E. Barke
The importance of identifying false paths in a combinational circuit cannot be overstated since they may mask the true delay. We present a fast algorithm based on Boolean satisfiability for solving this problem. We also present extensions to this per-path approach to find the critical path of a circuit in a reasonable time.
{"title":"Path verification using Boolean satisfiability","authors":"M. Ringe, T. Lindenkreuz, E. Barke","doi":"10.1109/DATE.1998.655991","DOIUrl":"https://doi.org/10.1109/DATE.1998.655991","url":null,"abstract":"The importance of identifying false paths in a combinational circuit cannot be overstated since they may mask the true delay. We present a fast algorithm based on Boolean satisfiability for solving this problem. We also present extensions to this per-path approach to find the critical path of a circuit in a reasonable time.","PeriodicalId":179207,"journal":{"name":"Proceedings Design, Automation and Test in Europe","volume":"5 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120895782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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