Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649073
Christos Vezyrtzis, Weiwei Jiang, S. Nowick, Y. Tsividis
This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning. The chip was used as part of a ADC/DSP/DAC chain which, unlike the case with conventional, clocked systems, maintains its frequency response intact when the sample rate changes. For certain inputs, the system has signal-to-error ratio which exceeds that of clocked systems.
{"title":"A flexible, clockless digital filter","authors":"Christos Vezyrtzis, Weiwei Jiang, S. Nowick, Y. Tsividis","doi":"10.1109/ESSCIRC.2013.6649073","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649073","url":null,"abstract":"This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning. The chip was used as part of a ADC/DSP/DAC chain which, unlike the case with conventional, clocked systems, maintains its frequency response intact when the sample rate changes. For certain inputs, the system has signal-to-error ratio which exceeds that of clocked systems.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116931248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649099
D. Cartasegna, P. Malcovati, L. Crespi, A. Baschirotto
This paper presents a third-order audio class-D amplifier, implemented in a 0.18-μm CMOS technology, achieving -92 dB of total harmonic distortion (THD) and 105 dBA of dynamic range (DR) with a quiescent current of 2 mA. The circuit delivers up to 2.4 W on a 4-Ω load with a peak efficiency of 88%. The THD performance, achieved thanks to the third-order loop filter, makes the proposed device suitable for high-end audio applications, where linear amplifiers are still the dominant solution.
{"title":"A 0.18-µm CMOS, −92-dB THD, 105-dBA DR, third-order audio class-D amplifier","authors":"D. Cartasegna, P. Malcovati, L. Crespi, A. Baschirotto","doi":"10.1109/ESSCIRC.2013.6649099","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649099","url":null,"abstract":"This paper presents a third-order audio class-D amplifier, implemented in a 0.18-μm CMOS technology, achieving -92 dB of total harmonic distortion (THD) and 105 dBA of dynamic range (DR) with a quiescent current of 2 mA. The circuit delivers up to 2.4 W on a 4-Ω load with a peak efficiency of 88%. The THD performance, achieved thanks to the third-order loop filter, makes the proposed device suitable for high-end audio applications, where linear amplifiers are still the dominant solution.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649144
V. Anghel, C. Bartholomeusz, G. Pristavu, G. Brezeanu
Switch-mode power supplies have become the premier choice for LED backlighting applications. This paper introduces a new current-mode floating buck controller architecture, used for driving constant current through a string of LEDs. Unlike state-of-the-art controllers, this architecture is based on fixed peak current and variable OFF time as the current control method. An innovative time modulator is added to provide a constant feedback loop response regardless of external components. The proposed controller architecture is designed, implemented in a 0.5μm CMOS process and its performances are validated by simulations and measurements.
{"title":"Variable off time current-mode floating buck controller - A different approach","authors":"V. Anghel, C. Bartholomeusz, G. Pristavu, G. Brezeanu","doi":"10.1109/ESSCIRC.2013.6649144","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649144","url":null,"abstract":"Switch-mode power supplies have become the premier choice for LED backlighting applications. This paper introduces a new current-mode floating buck controller architecture, used for driving constant current through a string of LEDs. Unlike state-of-the-art controllers, this architecture is based on fixed peak current and variable OFF time as the current control method. An innovative time modulator is added to provide a constant feedback loop response regardless of external components. The proposed controller architecture is designed, implemented in a 0.5μm CMOS process and its performances are validated by simulations and measurements.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649064
P. Kinget, J. Kuppambatti, B. Vigraham, Chun-Wei Hsu
Summary form only given. Analog circuits perform critical operations in any modern integrated circuit. Digital integrated circuits require analog circuits for logic or I/O clock generation, as well as for temperature monitoring or supply regulation. In mixed signal products, analog circuits perform the critical translation of information from the physical (analog) world to the digital world of ones and zeros. Analog-to-digital converters are typically preceded by signal conditioning circuits, including filtering and amplification, while digital-to-analog conversion needs to be followed by some form of analog signal conditioning.
{"title":"Scaling analog circuits","authors":"P. Kinget, J. Kuppambatti, B. Vigraham, Chun-Wei Hsu","doi":"10.1109/ESSCIRC.2013.6649064","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649064","url":null,"abstract":"Summary form only given. Analog circuits perform critical operations in any modern integrated circuit. Digital integrated circuits require analog circuits for logic or I/O clock generation, as well as for temperature monitoring or supply regulation. In mixed signal products, analog circuits perform the critical translation of information from the physical (analog) world to the digital world of ones and zeros. Analog-to-digital converters are typically preceded by signal conditioning circuits, including filtering and amplification, while digital-to-analog conversion needs to be followed by some form of analog signal conditioning.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131288761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSDERC.2013.6818811
J. Alamo
Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling has nearly reached the end of the road and further progress to propel this technology to the THz regime will require significant device innovations. Separately, as Si CMOS faces mounting difficulties to maintain its historical density scaling path, InGaAs-channel MOSFETs have recently emerged as a credible alternative for mainstream logic technology capable of scaling to the 10 nm node and below. To get to this point, fundamental technical problems had to be solved though there are still many challenges to be addressed before the first non-Si CMOS technology becomes a reality. The intense research that this exciting prospect is generating is also reinvigorating the prospects of InGaAs FETs to become the first true THz electronics technology. This paper reviews progress and challenges of InGaAs-based FET technology for THz and CMOS.
{"title":"Nanometer-scale InGaAs Field-Effect Transistors for THz and CMOS technologies","authors":"J. Alamo","doi":"10.1109/ESSDERC.2013.6818811","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818811","url":null,"abstract":"Integrated circuits based on InGaAs Field Effect Transistors are currently in wide use in the RF front-ends of smart phones and other mobile platforms, wireless LANs, high data rate fiber-optic links and many defense and space communication systems. InGaAs ICs are also under intense research for new millimeter-wave applications such as collision avoidance radar and gigabit WLANs. InGaAs FET scaling has nearly reached the end of the road and further progress to propel this technology to the THz regime will require significant device innovations. Separately, as Si CMOS faces mounting difficulties to maintain its historical density scaling path, InGaAs-channel MOSFETs have recently emerged as a credible alternative for mainstream logic technology capable of scaling to the 10 nm node and below. To get to this point, fundamental technical problems had to be solved though there are still many challenges to be addressed before the first non-Si CMOS technology becomes a reality. The intense research that this exciting prospect is generating is also reinvigorating the prospects of InGaAs FETs to become the first true THz electronics technology. This paper reviews progress and challenges of InGaAs-based FET technology for THz and CMOS.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133962647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649098
P. Callemeyn, M. Steyaert
A fully-integrated Class-D DC-AC converter is realized in a 130 nm 1.2V CMOS technology with an on-chip inductor and capacitor. Several dies are combined to achieve higher output power. A multilevel topology allows the combined Class-D DC-AC system to achieve higher output voltages at a multiple of the nominal supply voltage of 1.2V. Problems such as hot carrier degradation and oxide breakdown are absent, since each subblock operates within the standard voltage limits. An off-chip low frequency signal can be used as a reference clock for the Class-D DC-AC converter using an on-chip PWM generation circuit. For this monolithic multilevel system, no discrete components are needed anymore, reducing the bill of materials. A maximum efficiency of 66.5% for a stand-alone die is reached. An output peak voltage of 2.4V peak-to-peak is achieved at an efficiency of 33% by using a combination of several dies. A total output power of 95mW is obtained.
{"title":"A monolithic stacked Class-D approach for high voltage DC-AC conversion in standard CMOS","authors":"P. Callemeyn, M. Steyaert","doi":"10.1109/ESSCIRC.2013.6649098","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649098","url":null,"abstract":"A fully-integrated Class-D DC-AC converter is realized in a 130 nm 1.2V CMOS technology with an on-chip inductor and capacitor. Several dies are combined to achieve higher output power. A multilevel topology allows the combined Class-D DC-AC system to achieve higher output voltages at a multiple of the nominal supply voltage of 1.2V. Problems such as hot carrier degradation and oxide breakdown are absent, since each subblock operates within the standard voltage limits. An off-chip low frequency signal can be used as a reference clock for the Class-D DC-AC converter using an on-chip PWM generation circuit. For this monolithic multilevel system, no discrete components are needed anymore, reducing the bill of materials. A maximum efficiency of 66.5% for a stand-alone die is reached. An output peak voltage of 2.4V peak-to-peak is achieved at an efficiency of 33% by using a combination of several dies. A total output power of 95mW is obtained.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649143
G. Capodivacca, P. Milanesi, Andrea Scenini
This paper describes the design and the implementation of a digital controller for LED driver. By utilizing a simple comparator for sampling the output current a relay base controller has been dimensioned. Using a 5bit DPWM and the relay controller the low frequency limit cycle oscillations can be avoided.
{"title":"Integrated buck LED driver with application specific digital architecture","authors":"G. Capodivacca, P. Milanesi, Andrea Scenini","doi":"10.1109/ESSCIRC.2013.6649143","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649143","url":null,"abstract":"This paper describes the design and the implementation of a digital controller for LED driver. By utilizing a simple comparator for sampling the output current a relay base controller has been dimensioned. Using a 5bit DPWM and the relay controller the low frequency limit cycle oscillations can be avoided.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1035 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134435433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649147
A. Schmidt, H. Kappert, R. Kokozinski
The analog performance, e.g. intrinsic gain and bandwidth, of SOI (Silicon-on-Insulator) MOSFETs is strongly affected by increasing operating temperature. Increased leakage currents and decreased device performance significantly reduce the high temperature capability of analog circuits at high temperatures. In this paper, we demonstrate that the reverse body biasing (RBB) approach improves the transistor's analog performance up to 400°C. With RBB, operation in the lower moderate inversion region of the SOI transistor is feasible at increased temperatures. The method also allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD (partially depleted) SOI CMOS process. NHGATE and PHGATE devices with an H-shaped gate have been investigated. Results report an improvement of the gm/Id factor and the intrinsic gain Ai in the moderate inversion region by applying RBB. In addition, essential analog building blocks, e.g. current mirrors, an analog switch and a two-stage operational amplifier have been investigated. It is shown that the high temperature operation of these circuits is significantly enhanced when RBB is applied.
{"title":"High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing","authors":"A. Schmidt, H. Kappert, R. Kokozinski","doi":"10.1109/ESSCIRC.2013.6649147","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649147","url":null,"abstract":"The analog performance, e.g. intrinsic gain and bandwidth, of SOI (Silicon-on-Insulator) MOSFETs is strongly affected by increasing operating temperature. Increased leakage currents and decreased device performance significantly reduce the high temperature capability of analog circuits at high temperatures. In this paper, we demonstrate that the reverse body biasing (RBB) approach improves the transistor's analog performance up to 400°C. With RBB, operation in the lower moderate inversion region of the SOI transistor is feasible at increased temperatures. The method also allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD (partially depleted) SOI CMOS process. NHGATE and PHGATE devices with an H-shaped gate have been investigated. Results report an improvement of the gm/Id factor and the intrinsic gain Ai in the moderate inversion region by applying RBB. In addition, essential analog building blocks, e.g. current mirrors, an analog switch and a two-stage operational amplifier have been investigated. It is shown that the high temperature operation of these circuits is significantly enhanced when RBB is applied.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"591 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133073971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649119
Bichoy Bahr, R. Marathe, Wentao Wang, D. Weinstein
This paper presents a review of our work in CMOS-MEMS resonators fabricated in Front-End-of-Line (FEOL) processing of standard CMOS technology with no need for post-processing or special packaging. Acoustic resonators composed of Si and SiO2 found in the CMOS stack are demonstrated, confined by Acoustic Bragg Reflectors and sensed using a standard transistor embedded inside the acoustic resonant cavity. The merits of active transistor sensing of MEMS resonators at high frequencies are discussed, leading to the principle of the Resonant Body Transistors (RBTs) described in this work. RBTs realized in IBM's 32nm SOI process are demonstrated with resonance frequency above 11 GHz and Q~30, spanning a footprint of less than 15 μm2. Finally, thermal stability of <;3 ppm/K is shown for these CMOS-integrated devices. The CMOS-MEMS resonators presented here offer building blocks for RF circuit design which can be integrated seamlessly with supporting circuits for on-chip clocking and signal processing.
{"title":"Solid state RF MEMS resonators in standard CMOS","authors":"Bichoy Bahr, R. Marathe, Wentao Wang, D. Weinstein","doi":"10.1109/ESSCIRC.2013.6649119","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649119","url":null,"abstract":"This paper presents a review of our work in CMOS-MEMS resonators fabricated in Front-End-of-Line (FEOL) processing of standard CMOS technology with no need for post-processing or special packaging. Acoustic resonators composed of Si and SiO2 found in the CMOS stack are demonstrated, confined by Acoustic Bragg Reflectors and sensed using a standard transistor embedded inside the acoustic resonant cavity. The merits of active transistor sensing of MEMS resonators at high frequencies are discussed, leading to the principle of the Resonant Body Transistors (RBTs) described in this work. RBTs realized in IBM's 32nm SOI process are demonstrated with resonance frequency above 11 GHz and Q~30, spanning a footprint of less than 15 μm2. Finally, thermal stability of <;3 ppm/K is shown for these CMOS-integrated devices. The CMOS-MEMS resonators presented here offer building blocks for RF circuit design which can be integrated seamlessly with supporting circuits for on-chip clocking and signal processing.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115024294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649095
S. Manohar, P. Balsara
This paper presents a dynamic logic based adaptive dead-time control circuit (DADTC) for fast and adaptive control to minimize body diode conduction losses and dead-time of the buck regulator operating in discontinuous conduction mode (DCM). Dead-time is an important metric for improving efficiency of low voltage converters. DADTC provides instant sensing and feedback based on the load to minimize dead-time significantly compared to prior art and enables higher overall power efficiency of the converter. Further, the presented buck converter has inherent pulse skipping mode to lower the switching frequency at light loads further enhancing light load efficiency. The buck regulator was fabricated in 0.35 μm CMOS process with an input voltage range of 1.8V-3V and load current range of 1mA-200mA. Measurement results show that the proposed design achieves peak power efficiency of 94.6% and a high overall power efficiency ( > ~89%) for load currents greater than 5mA with a sensing delay of only ~5ns for VIN = 1.8V.
{"title":"94.6% peak efficiency DCM buck converter with fast adaptive dead-time control","authors":"S. Manohar, P. Balsara","doi":"10.1109/ESSCIRC.2013.6649095","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649095","url":null,"abstract":"This paper presents a dynamic logic based adaptive dead-time control circuit (DADTC) for fast and adaptive control to minimize body diode conduction losses and dead-time of the buck regulator operating in discontinuous conduction mode (DCM). Dead-time is an important metric for improving efficiency of low voltage converters. DADTC provides instant sensing and feedback based on the load to minimize dead-time significantly compared to prior art and enables higher overall power efficiency of the converter. Further, the presented buck converter has inherent pulse skipping mode to lower the switching frequency at light loads further enhancing light load efficiency. The buck regulator was fabricated in 0.35 μm CMOS process with an input voltage range of 1.8V-3V and load current range of 1mA-200mA. Measurement results show that the proposed design achieves peak power efficiency of 94.6% and a high overall power efficiency ( > ~89%) for load currents greater than 5mA with a sensing delay of only ~5ns for VIN = 1.8V.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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