Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649093
S. Izumi, K. Yamashita, M. Nakano, T. Konishi, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, M. Yoshimoto
This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.
{"title":"A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system","authors":"S. Izumi, K. Yamashita, M. Nakano, T. Konishi, H. Kawaguchi, H. Kimura, K. Marumoto, T. Fuchikami, Y. Fujimori, H. Nakajima, T. Shiga, M. Yoshimoto","doi":"10.1109/ESSCIRC.2013.6649093","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649093","url":null,"abstract":"This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649160
W. Steyaert, P. Reynaert
This work presents a 540 GHz signal generator consisting of a LC-VCO with buffer, implemented in a 40 nm bulk CMOS technology. The buffer is optimized for non-linear operation, to maximize the third harmonic generation at 540 GHz. The third harmonic is coupled to the load by a transformer. To accurately measure the output power, a WR-1.5 probe has been used. The output power is -31 dBm at 543 GHz, for 16.8 mW of DC power consumption. The output frequency can be tuned from 561.5 GHz to 539.6 GHz, resulting in a 21.9 GHz tuning range,the highest reported so far for CMOS THz oscillators. The 3-dB output bandwidth is 5.5 GHz.
{"title":"A 0.54 THz signal generator in 40 nm bulk CMOS with 22 GHz tuning range","authors":"W. Steyaert, P. Reynaert","doi":"10.1109/ESSCIRC.2013.6649160","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649160","url":null,"abstract":"This work presents a 540 GHz signal generator consisting of a LC-VCO with buffer, implemented in a 40 nm bulk CMOS technology. The buffer is optimized for non-linear operation, to maximize the third harmonic generation at 540 GHz. The third harmonic is coupled to the load by a transformer. To accurately measure the output power, a WR-1.5 probe has been used. The output power is -31 dBm at 543 GHz, for 16.8 mW of DC power consumption. The output frequency can be tuned from 561.5 GHz to 539.6 GHz, resulting in a 21.9 GHz tuning range,the highest reported so far for CMOS THz oscillators. The 3-dB output bandwidth is 5.5 GHz.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124169280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649159
Luca Fanori, P. Andreani
This paper presents a high-swing VCO combining the efficiency of the class-C oscillator with that of the complementary PMOS-NMOS topology. Moreover, removing the traditional tail current source, the VCO exhibits an even larger swing, maximizing the phase noise performance. Designed in a 90nm CMOS process, the VCO operates between 3.3GHz and 4.4 GHz, for a 28% tuning range. Drawing 1.8mA from 1.2V, the phase noise is -142 dBc/Hz at a 10MHz offset from a 4.4GHz carrier. The resulting phase-noise FoM is 191.5 dBc/Hz and varies 1.5 dB across the tuning range.
{"title":"A high-swing complementary class-C VCO","authors":"Luca Fanori, P. Andreani","doi":"10.1109/ESSCIRC.2013.6649159","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649159","url":null,"abstract":"This paper presents a high-swing VCO combining the efficiency of the class-C oscillator with that of the complementary PMOS-NMOS topology. Moreover, removing the traditional tail current source, the VCO exhibits an even larger swing, maximizing the phase noise performance. Designed in a 90nm CMOS process, the VCO operates between 3.3GHz and 4.4 GHz, for a 28% tuning range. Drawing 1.8mA from 1.2V, the phase noise is -142 dBc/Hz at a 10MHz offset from a 4.4GHz carrier. The resulting phase-noise FoM is 191.5 dBc/Hz and varies 1.5 dB across the tuning range.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649109
A. Do, Chun Yin, K. Yeo, T. T. Kim
This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged by a pulsed current source to minimize power. The proposed ABC scheme monitors the ML sensing using two dummy rows. It digitally adjusts the pulse width and the delay of the search control signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum operating point, making the CAM tolerant to fabrication variations. Additionally, multi-Vt transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharge speed by 2× when compared with the standard-Vt devices at 1.2V, 80 °C. The test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 500 MHz /1.2 V.
{"title":"Design of a power-efficient CAM using automated background checking scheme for small match line swing","authors":"A. Do, Chun Yin, K. Yeo, T. T. Kim","doi":"10.1109/ESSCIRC.2013.6649109","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649109","url":null,"abstract":"This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged by a pulsed current source to minimize power. The proposed ABC scheme monitors the ML sensing using two dummy rows. It digitally adjusts the pulse width and the delay of the search control signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum operating point, making the CAM tolerant to fabrication variations. Additionally, multi-Vt transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharge speed by 2× when compared with the standard-Vt devices at 1.2V, 80 °C. The test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 500 MHz /1.2 V.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133180967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649129
E. Muijs, P. Silva, A. V. Staveren, W. Serdijn
This paper presents a temperature compensated logarithmic amplifier (log-amp) RF power detector implemented in CMOS 0.18μm technology. The input power can range from -50 to +10 dBm for RF signals ranging from 100MHz to 1.5 GHz. This design attains a typical DR of 39 dB for a ±1 dB log-conformance error (LCE). Up to 900MHz the temperature drift is never larger than ±1.1 dB for all 24 measured samples over a temperature range from -40 to +85°C. The current consumption is 6.3mA from a 1.8V power supply and the chip area is 0.76mm2.
{"title":"A 39 dB DR CMOS log-amp RF power detector with ±1.1 dB temperature drift from −40 to 85°C","authors":"E. Muijs, P. Silva, A. V. Staveren, W. Serdijn","doi":"10.1109/ESSCIRC.2013.6649129","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649129","url":null,"abstract":"This paper presents a temperature compensated logarithmic amplifier (log-amp) RF power detector implemented in CMOS 0.18μm technology. The input power can range from -50 to +10 dBm for RF signals ranging from 100MHz to 1.5 GHz. This design attains a typical DR of 39 dB for a ±1 dB log-conformance error (LCE). Up to 900MHz the temperature drift is never larger than ±1.1 dB for all 24 measured samples over a temperature range from -40 to +85°C. The current consumption is 6.3mA from a 1.8V power supply and the chip area is 0.76mm2.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130818814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649148
P. Schröter, Magnus-Maria Hell, Martin Frey
This paper introduces an integrated Local Interconnect Network (LIN) transceiver which sets a new performance benchmark in terms of electromagnetic compatibility (EMC). The proposed topology succeeds in an extraordinary high robustness against RF disturbances which are injected into the BUS and in very low electromagnetic emissions (EMEs) radiated by the LIN network without adding any external components for filtering. In order to evaluate the circuits superior EMC performance, it was designed using a HV-BiCMOS technology for automotive applications, the EMC behavior was measured and the results were compared with a state of the art topology.
{"title":"EMC compliant LIN transceiver","authors":"P. Schröter, Magnus-Maria Hell, Martin Frey","doi":"10.1109/ESSCIRC.2013.6649148","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649148","url":null,"abstract":"This paper introduces an integrated Local Interconnect Network (LIN) transceiver which sets a new performance benchmark in terms of electromagnetic compatibility (EMC). The proposed topology succeeds in an extraordinary high robustness against RF disturbances which are injected into the BUS and in very low electromagnetic emissions (EMEs) radiated by the LIN network without adding any external components for filtering. In order to evaluate the circuits superior EMC performance, it was designed using a HV-BiCMOS technology for automotive applications, the EMC behavior was measured and the results were compared with a state of the art topology.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649101
Nan Qi, B. Chi, Yang Xu, Zhou Chen, Yang Xu, Jun Xie, Zheng Song, Zhihua Wang
A fully-integrated dual-channel reconfigurable GNSS (GPS/GLONASS/Galileo/Compass) receiver in 180nm CMOS is presented, supporting simultaneous dual-system signal reception. Two channels of the receiver share RF front-end circuits and the frequency synthesizer, and employ separate IF-strips to support the different navigation systems. Reconfigurable signal bandwidths are supported, covering from 2.2MHz to 10MHz to implement both civil and high precision positioning. The on-chip I/Q mismatch calibration circuit is integrated to improve the image rejection ratio (IRR), which can be realized automatically with the aid of a FPGA. Besides, the receiver integrates internal AFC, DCOC, LDO and DCXO, which make it a complete GNSS radio. Thanks to the power scalable analog baseband circuits, the power consumption in the typical dual-channel mode is reduced to 23mA. The receiver achieves 2.5dB noise figure, 55dB dynamic range with 1dB steps, 50dB IRR and -57dBm input 1dB-compression point. The receiver can cooperate with a digital baseband to track real-time satellites in the open sky, achieving higher than 40dB CNR for both GPS and Compass systems.
{"title":"A 180nm fully-integrated dual-channel reconfigurable receiver for GNSS interoperations","authors":"Nan Qi, B. Chi, Yang Xu, Zhou Chen, Yang Xu, Jun Xie, Zheng Song, Zhihua Wang","doi":"10.1109/ESSCIRC.2013.6649101","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649101","url":null,"abstract":"A fully-integrated dual-channel reconfigurable GNSS (GPS/GLONASS/Galileo/Compass) receiver in 180nm CMOS is presented, supporting simultaneous dual-system signal reception. Two channels of the receiver share RF front-end circuits and the frequency synthesizer, and employ separate IF-strips to support the different navigation systems. Reconfigurable signal bandwidths are supported, covering from 2.2MHz to 10MHz to implement both civil and high precision positioning. The on-chip I/Q mismatch calibration circuit is integrated to improve the image rejection ratio (IRR), which can be realized automatically with the aid of a FPGA. Besides, the receiver integrates internal AFC, DCOC, LDO and DCXO, which make it a complete GNSS radio. Thanks to the power scalable analog baseband circuits, the power consumption in the typical dual-channel mode is reduced to 23mA. The receiver achieves 2.5dB noise figure, 55dB dynamic range with 1dB steps, 50dB IRR and -57dBm input 1dB-compression point. The receiver can cooperate with a digital baseband to track real-time satellites in the open sky, achieving higher than 40dB CNR for both GPS and Compass systems.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"153 1‐3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113956384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649091
M. Zargham, P. Gulak
This paper presents a fully integrated 2.2×2.2mm2, wireless power transfer (WPT) receiver in 0.13μm CMOS without any external components or post-processing steps. The on-chip receiver coil (Rx) demonstrates a peak measured WPT efficiency of -18.47dB, -20.96dB and -20.13dB at 10mm of separation through air, bovine muscle and 0.2molar NaCl, respectively. Fully integrating the large receiver coil along with supporting circuits introduces new challenges that are addressed in this paper. The receiver employs a synchronous adaptive matching network that guarantees the maximum achievable efficiency for a given resistive load. The proposed WPT rectifier uses feedback to avoid plasma-induced gate-oxide damage and a new dual-supply regulator architecture to achieve high power supply rejection ratio (PSRR) without utilizing any large off-chip capacitors.
{"title":"A 0.13µm CMOS integrated wireless power receiver for biomedical applications","authors":"M. Zargham, P. Gulak","doi":"10.1109/ESSCIRC.2013.6649091","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649091","url":null,"abstract":"This paper presents a fully integrated 2.2×2.2mm2, wireless power transfer (WPT) receiver in 0.13μm CMOS without any external components or post-processing steps. The on-chip receiver coil (Rx) demonstrates a peak measured WPT efficiency of -18.47dB, -20.96dB and -20.13dB at 10mm of separation through air, bovine muscle and 0.2molar NaCl, respectively. Fully integrating the large receiver coil along with supporting circuits introduces new challenges that are addressed in this paper. The receiver employs a synchronous adaptive matching network that guarantees the maximum achievable efficiency for a given resistive load. The proposed WPT rectifier uses feedback to avoid plasma-induced gate-oxide damage and a new dual-supply regulator architecture to achieve high power supply rejection ratio (PSRR) without utilizing any large off-chip capacitors.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124366355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649127
Anders Nejdel, Markus Törmänen, H. Sjöland
This paper presents a highly linear receiver front-end operating from 700 MHz to 3.7 GHz with 3rd order harmonic rejection. It consists of a complementary low noise transconductance amplifier with capacitive cross coupling and negative gm current sources, a six phase current-mode passive mixer, and baseband transimpedance amplifiers providing programmable gain. The circuit has been fabricated in 65 nm CMOS technology with an active area of just 0.09 mm2. It consumes 7.2 mA, excluding the six phase local oscillator generation, from a 1.2 V supply, achieving a third order harmonic rejection of 40 dB, and a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2 and IIP3 at full gain is +55 dBm and +5 dBm, respectively.
{"title":"A 0.7 – 3.7 GHz six phase receiver front-end with third order harmonic rejection","authors":"Anders Nejdel, Markus Törmänen, H. Sjöland","doi":"10.1109/ESSCIRC.2013.6649127","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649127","url":null,"abstract":"This paper presents a highly linear receiver front-end operating from 700 MHz to 3.7 GHz with 3rd order harmonic rejection. It consists of a complementary low noise transconductance amplifier with capacitive cross coupling and negative gm current sources, a six phase current-mode passive mixer, and baseband transimpedance amplifiers providing programmable gain. The circuit has been fabricated in 65 nm CMOS technology with an active area of just 0.09 mm2. It consumes 7.2 mA, excluding the six phase local oscillator generation, from a 1.2 V supply, achieving a third order harmonic rejection of 40 dB, and a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2 and IIP3 at full gain is +55 dBm and +5 dBm, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121115967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649075
Chuang Lu, M. Matters-Kammerer, R. Mahmoudi, P. Baltus, E. Habekotté, K. V. Hartingsveldt, F. V. D. Wilt
This paper presents a 48 GHz high resolution LO-path phase shifter implemented in 40-nm low-power CMOS technology. The full 360° phase shift tuning is implemented by a switched capacitor loaded tunable transmission line for fine tuning, in combination with a selection of one out of the N×45° phase steps available from the frequency divider-by-4 for coarse tuning. The measured phase shift resolution is 5.4° between 44 GHz and 54 GHz, which offers about 6-bit resolution. The chip area of the core circuitry is 550μm×260μm, and the total current consumption is 14.1 mA from a 1.2 V supply voltage.
{"title":"A 48 GHz 6-bit LO-path phase shifter in 40-nm CMOS for 60 GHz applications","authors":"Chuang Lu, M. Matters-Kammerer, R. Mahmoudi, P. Baltus, E. Habekotté, K. V. Hartingsveldt, F. V. D. Wilt","doi":"10.1109/ESSCIRC.2013.6649075","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649075","url":null,"abstract":"This paper presents a 48 GHz high resolution LO-path phase shifter implemented in 40-nm low-power CMOS technology. The full 360° phase shift tuning is implemented by a switched capacitor loaded tunable transmission line for fine tuning, in combination with a selection of one out of the N×45° phase steps available from the frequency divider-by-4 for coarse tuning. The measured phase shift resolution is 5.4° between 44 GHz and 54 GHz, which offers about 6-bit resolution. The chip area of the core circuitry is 550μm×260μm, and the total current consumption is 14.1 mA from a 1.2 V supply voltage.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122619070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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