Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649149
S. Porrazzo, V. N. Manyam, A. Morgado, D. San Segundo Bello, C. van Hoof, A. V. van Roermund, R. Yazicioglu, E. Cantatore
The paper presents a reconfigurable Delta-Sigma Modulator (ΔΣM) suitable for three operation modes, whose application ranges from bio-potential signal monitoring to hearing aids. A feed-forward 2nd-order SC ΔΣM architecture with 4-bit quantizer is selected according to an analytic power optimization procedure. The ΔΣM features programmable sampling capacitors in the first integrator and novel reconfigurable power-gated OTAs to adjust power consumption in each operation mode. An asynchronous embedded SAR converter implements low-power quantization and passive addition in the feed-forward topology. The prototype is implemented in a 0.18μm CMOS technology and operates from a supply voltage of 1V. Measurements show peak SNDRs from 99 to 75dB for signal bandwidths spanning from 256Hz to 16kHz, achieving figures of merit which are almost constant in the different modes, and range from 0.20 to 0.27pJ/c.s.
{"title":"A 1-V 99-to-75dB SNDR, 256Hz–16kHz bandwidth, 8.6-to-39µW reconfigurable SC ΔΣ Modulator for autonomous biomedical applications","authors":"S. Porrazzo, V. N. Manyam, A. Morgado, D. San Segundo Bello, C. van Hoof, A. V. van Roermund, R. Yazicioglu, E. Cantatore","doi":"10.1109/ESSCIRC.2013.6649149","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649149","url":null,"abstract":"The paper presents a reconfigurable Delta-Sigma Modulator (ΔΣM) suitable for three operation modes, whose application ranges from bio-potential signal monitoring to hearing aids. A feed-forward 2nd-order SC ΔΣM architecture with 4-bit quantizer is selected according to an analytic power optimization procedure. The ΔΣM features programmable sampling capacitors in the first integrator and novel reconfigurable power-gated OTAs to adjust power consumption in each operation mode. An asynchronous embedded SAR converter implements low-power quantization and passive addition in the feed-forward topology. The prototype is implemented in a 0.18μm CMOS technology and operates from a supply voltage of 1V. Measurements show peak SNDRs from 99 to 75dB for signal bandwidths spanning from 256Hz to 16kHz, achieving figures of merit which are almost constant in the different modes, and range from 0.20 to 0.27pJ/c.s.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125794983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649103
Ashkan Borna, C. Hull, Yanjie Wang, Hua Wang, A. Niknejad
This paper presents a 2.4GHz current-mode RF direct-conversion receiver implemented in a 90nm CMOS process with a novel adaptive notch filter. The notch filter uses the blocker frequency to up-convert a DC null to the pass-band, attenuating the blocker before entering the receiver. A synthesized inductor on the order of μH realizes the DC null. Blocker attenuation as large as 20dB is observed at a 40MHz offset frequency while the in-band attenuation increases by only 2dB. This proves that this technique is effective in attenuating blockers in broadband multi-standard radios without using any high-Q mechanical filters at their front-ends.
{"title":"An RF receiver with an integrated adaptive notch filter for multi-standard applications","authors":"Ashkan Borna, C. Hull, Yanjie Wang, Hua Wang, A. Niknejad","doi":"10.1109/ESSCIRC.2013.6649103","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649103","url":null,"abstract":"This paper presents a 2.4GHz current-mode RF direct-conversion receiver implemented in a 90nm CMOS process with a novel adaptive notch filter. The notch filter uses the blocker frequency to up-convert a DC null to the pass-band, attenuating the blocker before entering the receiver. A synthesized inductor on the order of μH realizes the DC null. Blocker attenuation as large as 20dB is observed at a 40MHz offset frequency while the in-band attenuation increases by only 2dB. This proves that this technique is effective in attenuating blockers in broadband multi-standard radios without using any high-Q mechanical filters at their front-ends.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649104
G. Tant, A. Giry, P. Vincent, J. Arnould, J. Fournier
This paper presents the implementation and measurement results of a power amplifier with passive load modulation targeting Femtocell base station applications and integrated in SOI CMOS 130nm process. The proposed structure combines a SOI LDMOS power stage with a SOI CMOS Tunable Matching Network (TMN) based on high voltage switched capacitors in order to improve PA efficiency at back-off power. At 2.14GHz, the PA achieves 31.5dBm of measured peak power under 4V supply and compared to a conventional PA with fixed output matching network, the measured efficiency improvement is 60 % at 8.5 dB back-off.
{"title":"A 2.14GHz watt-level power amplifier with passive load modulation in a SOI CMOS technology","authors":"G. Tant, A. Giry, P. Vincent, J. Arnould, J. Fournier","doi":"10.1109/ESSCIRC.2013.6649104","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649104","url":null,"abstract":"This paper presents the implementation and measurement results of a power amplifier with passive load modulation targeting Femtocell base station applications and integrated in SOI CMOS 130nm process. The proposed structure combines a SOI LDMOS power stage with a SOI CMOS Tunable Matching Network (TMN) based on high voltage switched capacitors in order to improve PA efficiency at back-off power. At 2.14GHz, the PA achieves 31.5dBm of measured peak power under 4V supply and compared to a conventional PA with fixed output matching network, the measured efficiency improvement is 60 % at 8.5 dB back-off.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121115011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649125
T. Gemmeke, M. Konijnenburg, Christian Bachmann
In-situ performance monitoring offers significantly better voltage scaling potential than classic ring-oscillator based approaches as it eliminates the uncertainty due to local random variations. The major challenge of such an approach is the timely generation of signaling events to control the voltage level at the most energy efficient point still offering reliable operation. In this paper we present a novel threshold based notification scheme together with a detailed analysis of corner cases. The presented measurement results are based on an implementation in a digital signal processor in a 40nm low-power technology achieving an effective voltage margin as low as 5mV.
{"title":"In-situ performance monitor employing threshold based notifications (TheBaN)","authors":"T. Gemmeke, M. Konijnenburg, Christian Bachmann","doi":"10.1109/ESSCIRC.2013.6649125","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649125","url":null,"abstract":"In-situ performance monitoring offers significantly better voltage scaling potential than classic ring-oscillator based approaches as it eliminates the uncertainty due to local random variations. The major challenge of such an approach is the timely generation of signaling events to control the voltage level at the most energy efficient point still offering reliable operation. In this paper we present a novel threshold based notification scheme together with a detailed analysis of corner cases. The presented measurement results are based on an implementation in a digital signal processor in a 40nm low-power technology achieving an effective voltage margin as low as 5mV.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121231649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649114
C. Condemine, J. Willemin, S. Bouquet, S. Robinet, A. Robinet, L. Jouanet, G. Regis, O. Compagnon, S. Vitry
This paper presents a high density pressure measurement ribbon used to characterize air-flow on a shape. The system is made of 128 15-bits pressure sensors thermally compensated by 10 bits temperature sensors. The MEMS pressure sensor capacitance variations are converted into digital thanks to a second order switched capacitors sigma-delta converter. An innovative serial-bit sliding window FIR filter allows asynchronous data transfer on the 8MHz SPI like bus with limited time response (<;1ms) and low frequency modulator (333kHz). The temperature to digital conversion is carried out by a passive sigma-delta modulator, reaching low area and low power consumption. The global system noise is limited to 24 Pa in a range of [20kPa/95kPa] and [-30°C/+60°C].
{"title":"128 nodes 4.5 mm pitch 15-bit pressure sensor ribbon","authors":"C. Condemine, J. Willemin, S. Bouquet, S. Robinet, A. Robinet, L. Jouanet, G. Regis, O. Compagnon, S. Vitry","doi":"10.1109/ESSCIRC.2013.6649114","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649114","url":null,"abstract":"This paper presents a high density pressure measurement ribbon used to characterize air-flow on a shape. The system is made of 128 15-bits pressure sensors thermally compensated by 10 bits temperature sensors. The MEMS pressure sensor capacitance variations are converted into digital thanks to a second order switched capacitors sigma-delta converter. An innovative serial-bit sliding window FIR filter allows asynchronous data transfer on the 8MHz SPI like bus with limited time response (<;1ms) and low frequency modulator (333kHz). The temperature to digital conversion is carried out by a passive sigma-delta modulator, reaching low area and low power consumption. The global system noise is limited to 24 Pa in a range of [20kPa/95kPa] and [-30°C/+60°C].","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649152
J. Mao, Z. Zou, Lirong Zheng
This paper presents an energy-efficient injection-locking based UWB transmitter for RFID tags in a 0.18 μm CMOS technology. The transmitter is powered by 900 MHz UHF signals radiated by a reader wirelessly, and responds UWB pulses by locking-gating-amplifying the sub-harmonic of the UHF signal. A simple harmonic injection-locking ring oscillator (ILRO) is utilized to generate a 450 MHz carrier for sub-GHz UWB, eliminating power-hungry and complex timing components such as PLL and crystal on tags. The measurement results show that the sensitivity of the ILRO is -15 dBm under 21% locking range without any extra amplifier. Thanks to fast setup time of the ILRO, the proposed transmitter is power-scalable with 35 pJ/pulse energy consumption by duty-cycling. The amplitude of the transmitted UWB pulse is 0.75 Vpp, allowing a pulse rate up to 5 MHz under the FCC regulations. The entire power consumption of the transmitter is 175 μW, which is favorable to wirelessly-powered RFID applications.
{"title":"A 35 pJ/pulse injection-locking based UWB transmitter for wirelessly-powered RFID tags","authors":"J. Mao, Z. Zou, Lirong Zheng","doi":"10.1109/ESSCIRC.2013.6649152","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649152","url":null,"abstract":"This paper presents an energy-efficient injection-locking based UWB transmitter for RFID tags in a 0.18 μm CMOS technology. The transmitter is powered by 900 MHz UHF signals radiated by a reader wirelessly, and responds UWB pulses by locking-gating-amplifying the sub-harmonic of the UHF signal. A simple harmonic injection-locking ring oscillator (ILRO) is utilized to generate a 450 MHz carrier for sub-GHz UWB, eliminating power-hungry and complex timing components such as PLL and crystal on tags. The measurement results show that the sensitivity of the ILRO is -15 dBm under 21% locking range without any extra amplifier. Thanks to fast setup time of the ILRO, the proposed transmitter is power-scalable with 35 pJ/pulse energy consumption by duty-cycling. The amplitude of the transmitted UWB pulse is 0.75 Vpp, allowing a pulse rate up to 5 MHz under the FCC regulations. The entire power consumption of the transmitter is 175 μW, which is favorable to wirelessly-powered RFID applications.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"610 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649082
V. Milovanovic, H. Zimmermann
A fully differential continuous-time comparator, that consists of a preamplifier-latch cascade, achieves propagation delays of 99 ps for a 50mVpp and 74 ps for a 100mVpp input signal amplitude under 1.1V supply and 1.2mW power consumption. The comparator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. Dynamic delay-power management is supported through digital programmability of the self-biasing and supply voltage scaling. The design occupies 0.0007mm2 in 40 nm LP CMOS process.
{"title":"A 40 nm LP CMOS self-biased continuous-time comparator with sub-100ps delay at 1.1V & 1.2mW","authors":"V. Milovanovic, H. Zimmermann","doi":"10.1109/ESSCIRC.2013.6649082","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649082","url":null,"abstract":"A fully differential continuous-time comparator, that consists of a preamplifier-latch cascade, achieves propagation delays of 99 ps for a 50mVpp and 74 ps for a 100mVpp input signal amplitude under 1.1V supply and 1.2mW power consumption. The comparator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. Dynamic delay-power management is supported through digital programmability of the self-biasing and supply voltage scaling. The design occupies 0.0007mm2 in 40 nm LP CMOS process.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"246 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649108
F. Abouzeid, A. Bienfait, K. Akyel, S. Clerc, L. Ciampolini, P. Roche
We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.
{"title":"Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI","authors":"F. Abouzeid, A. Bienfait, K. Akyel, S. Clerc, L. Ciampolini, P. Roche","doi":"10.1109/ESSCIRC.2013.6649108","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649108","url":null,"abstract":"We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124175497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649121
K. Palem, L. Avinash, C. Enz, C. Piguet
Moore's law, the driving force behind the computing technology revolution is widely expected to face limiting, if not disruptive, hurdles within the next 5 years or so, owing in part to its inability to cope with the errors arising from device variations and perturbations as well as the accompanying increased power density in deep nanoscale CMOS regime. To overcome these twin hurdles and in a sharp contrast to that of conventional research based on von Neumann's legacy of designing reliable hardware from unreliable components, we adopt a radically different philosophy of designing unreliable hardware from reliable or unreliable components, wherein we take advantage of the inherent- or induced- errors in the circuits to achieve significant cost (in terms of size, energy, design, performance, manufacturing and verification) savings. Our approach not only is sensitive to the value of information, thereby producing good enough designs of lesser cost but also opens an entirely new design space where perceptual- and statistical-limitations (and hence, the desired quality) is a dimension that can be traded off.
{"title":"Why design reliable chips when faulty ones are even better","authors":"K. Palem, L. Avinash, C. Enz, C. Piguet","doi":"10.1109/ESSCIRC.2013.6649121","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649121","url":null,"abstract":"Moore's law, the driving force behind the computing technology revolution is widely expected to face limiting, if not disruptive, hurdles within the next 5 years or so, owing in part to its inability to cope with the errors arising from device variations and perturbations as well as the accompanying increased power density in deep nanoscale CMOS regime. To overcome these twin hurdles and in a sharp contrast to that of conventional research based on von Neumann's legacy of designing reliable hardware from unreliable components, we adopt a radically different philosophy of designing unreliable hardware from reliable or unreliable components, wherein we take advantage of the inherent- or induced- errors in the circuits to achieve significant cost (in terms of size, energy, design, performance, manufacturing and verification) savings. Our approach not only is sensitive to the value of information, thereby producing good enough designs of lesser cost but also opens an entirely new design space where perceptual- and statistical-limitations (and hence, the desired quality) is a dimension that can be traded off.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649158
T. Siriburanon, W. Deng, Ahmed Musa, K. Okada, A. Matsuzawa
This paper presents a wide-locking-range, low-power, Injection-Locked Frequency Divider (ILFD) using even-harmonic-enhanced direct injection technique which can operate with a high division ratio of 4 and 6. The proposed ILFD has been fabricated in a 65nm CMOS process with a core area of 0.002mm2. The proposed ILFD achieves the widest measured locking range reported of 4.3 GHz (13.2%) for a divide-by-6 operation with a power consumption of only 3.1mW without any tuning mechanism. Moreover, it also achieves 5.7GHz (28.5%) for divide-by-4 operation while consuming only 3.1mW. Combining its multi-division and tuning capability, the dividing capability ranges from 14.0-38.0GHz while consuming 2.8 to 5.4mW.
{"title":"A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs","authors":"T. Siriburanon, W. Deng, Ahmed Musa, K. Okada, A. Matsuzawa","doi":"10.1109/ESSCIRC.2013.6649158","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649158","url":null,"abstract":"This paper presents a wide-locking-range, low-power, Injection-Locked Frequency Divider (ILFD) using even-harmonic-enhanced direct injection technique which can operate with a high division ratio of 4 and 6. The proposed ILFD has been fabricated in a 65nm CMOS process with a core area of 0.002mm2. The proposed ILFD achieves the widest measured locking range reported of 4.3 GHz (13.2%) for a divide-by-6 operation with a power consumption of only 3.1mW without any tuning mechanism. Moreover, it also achieves 5.7GHz (28.5%) for divide-by-4 operation while consuming only 3.1mW. Combining its multi-division and tuning capability, the dividing capability ranges from 14.0-38.0GHz while consuming 2.8 to 5.4mW.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114680583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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