Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649069
M. Caruso, M. Bassi, A. Bevilacqua, A. Neviani
A 65 nm CMOS LO generation system capable of providing quadrature signals over the wide 2 to 16GHz frequency range for short-range radar applications is presented. Made of a 6.5 to 18.4GHz PLL, and an injection-locked programmable divider by 1, 2, or 4, it features a phase noise at 10MHz offset <; -129 dBc/Hz, a RMS jitter <; 0.68 ps, a reference spur level <; -48 dBc, and a settling time of 2 μs.
{"title":"Wideband 2–16GHz local oscillator generation for short-range radar applications","authors":"M. Caruso, M. Bassi, A. Bevilacqua, A. Neviani","doi":"10.1109/ESSCIRC.2013.6649069","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649069","url":null,"abstract":"A 65 nm CMOS LO generation system capable of providing quadrature signals over the wide 2 to 16GHz frequency range for short-range radar applications is presented. Made of a 6.5 to 18.4GHz PLL, and an injection-locked programmable divider by 1, 2, or 4, it features a phase noise at 10MHz offset <; -129 dBc/Hz, a RMS jitter <; 0.68 ps, a reference spur level <; -48 dBc, and a settling time of 2 μs.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124764583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649128
Nicola Codega, A. Liscidini, R. Castello
A 55nm CMOS current-mode transmitter for multistandard wireless communications (including LTE) that requires only 1.5mm2 (with 4 output ports) is presented. The circuit is made up of two portions: a class A/B up-converter and a baseband that includes DAC, VGA, low-pass filter (two Biquad plus a passive first order) and class A/B signal conditioner. Combining a third order filter with the class A/B conditioner results in a reduction of both current consumption and RX-band noise injection. For LTE10, the consumption is 96mW and 34mW at 4dBm and at -10dBm output power, respectively. The complete transmitter gives -158dBc/Hz RX-band noise injection at 30MHz offset.
{"title":"A low out-of-band noise LTE transmitter with current-mode approach","authors":"Nicola Codega, A. Liscidini, R. Castello","doi":"10.1109/ESSCIRC.2013.6649128","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649128","url":null,"abstract":"A 55nm CMOS current-mode transmitter for multistandard wireless communications (including LTE) that requires only 1.5mm2 (with 4 output ports) is presented. The circuit is made up of two portions: a class A/B up-converter and a baseband that includes DAC, VGA, low-pass filter (two Biquad plus a passive first order) and class A/B signal conditioner. Combining a third order filter with the class A/B conditioner results in a reduction of both current consumption and RX-band noise injection. For LTE10, the consumption is 96mW and 34mW at 4dBm and at -10dBm output power, respectively. The complete transmitter gives -158dBc/Hz RX-band noise injection at 30MHz offset.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127971362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649124
T. Akazawa, S. Sasaki, H. Mattausch
The reported digital, word-parallel and scalable coprocessor architecture for nearest Euclidean distance (ED) search is based on mapping the distance into time domain onto an equivalent clock number. Area-efficient sequential square calculation and a minimization algorithm of the clock number necessary for the search are applied for practical efficiency. Experimental concept verification was done with an 180nm CMOS design implementing 32 reference vectors with 16 components and 8 bit per component. The fabricated test chips achieved 1.19μs average search time, 5.77 μs worst-case search time and low power dissipation of 8.75mW at 47MHz and Vdd=1.8V for code-book-based picture compression. To our best knowledge this is the first report of practical, word-parallel, digital nearest ED-search architecture. In comparison to previous digital-analog ASIC and GPU implementations, factors 1.8 and 4.5·105 smaller power delay products per 1NN search are realized, respectively.
{"title":"Word-parallel coprocessor architecture for digital nearest Euclidean distance search","authors":"T. Akazawa, S. Sasaki, H. Mattausch","doi":"10.1109/ESSCIRC.2013.6649124","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649124","url":null,"abstract":"The reported digital, word-parallel and scalable coprocessor architecture for nearest Euclidean distance (ED) search is based on mapping the distance into time domain onto an equivalent clock number. Area-efficient sequential square calculation and a minimization algorithm of the clock number necessary for the search are applied for practical efficiency. Experimental concept verification was done with an 180nm CMOS design implementing 32 reference vectors with 16 components and 8 bit per component. The fabricated test chips achieved 1.19μs average search time, 5.77 μs worst-case search time and low power dissipation of 8.75mW at 47MHz and Vdd=1.8V for code-book-based picture compression. To our best knowledge this is the first report of practical, word-parallel, digital nearest ED-search architecture. In comparison to previous digital-analog ASIC and GPU implementations, factors 1.8 and 4.5·105 smaller power delay products per 1NN search are realized, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649117
Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, R. Staszewski
We present a two-channel RF generation system for a 2 GHz basestation transmitter that avoids pulling due to various parasitic coupling paths, especially between a strong RF output and a sensitive LC-tank of an RF oscillator. This is achieved through a fractional frequency translation by means of a programmable fractional divider realized as a dynamic edge selector of eight oscillator phases. This way, the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels is avoided, thus rendered harmless in the creation of injection pulling spurs. The proposed method can push the injection pulling spurs far away from the carrier and at an infinitesimal power level below -80 dBc. The pulling mitigation for two RF channels has been verified in a 65-nm CMOS testchip that occupies 0.56×1.46 mm2 area and emits -156 dBc/Hz noise floor. An RF oscillator is realized as a class-C topology without tail current source.
{"title":"Frequency translation through fractional division for a two-channel pulling mitigation","authors":"Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, R. Staszewski","doi":"10.1109/ESSCIRC.2013.6649117","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649117","url":null,"abstract":"We present a two-channel RF generation system for a 2 GHz basestation transmitter that avoids pulling due to various parasitic coupling paths, especially between a strong RF output and a sensitive LC-tank of an RF oscillator. This is achieved through a fractional frequency translation by means of a programmable fractional divider realized as a dynamic edge selector of eight oscillator phases. This way, the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels is avoided, thus rendered harmless in the creation of injection pulling spurs. The proposed method can push the injection pulling spurs far away from the carrier and at an infinitesimal power level below -80 dBc. The pulling mitigation for two RF channels has been verified in a 65-nm CMOS testchip that occupies 0.56×1.46 mm2 area and emits -156 dBc/Hz noise floor. An RF oscillator is realized as a class-C topology without tail current source.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117321566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649102
A. Ng, S. Zheng, H. Leung, Y. Chao, H. Luong
A 0.9GHz-to-5.8GHz SDR RFE is presented employing a dual-band LNA with a switchable 3-coil transformer as loading for current-gain boosting and an automatic LO phase-error detection and calibration circuitry for harmonic rejection. Fabricated in 65nm CMOS and integrated with a fully-integrated all-digital synthesizer (ADFS), the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6dBm and -12.8dBm, 3rd-order HRR of 81dB, and 5th-order HRR of 70dB, while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2.
{"title":"A 0.9GHz–5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio","authors":"A. Ng, S. Zheng, H. Leung, Y. Chao, H. Luong","doi":"10.1109/ESSCIRC.2013.6649102","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649102","url":null,"abstract":"A 0.9GHz-to-5.8GHz SDR RFE is presented employing a dual-band LNA with a switchable 3-coil transformer as loading for current-gain boosting and an automatic LO phase-error detection and calibration circuitry for harmonic rejection. Fabricated in 65nm CMOS and integrated with a fully-integrated all-digital synthesizer (ADFS), the RFE measures NF between 2.9dB and 3.8dB, IIP3 between -1.6dBm and -12.8dBm, 3rd-order HRR of 81dB, and 5th-order HRR of 70dB, while consuming between 66mA and 82mA from a 1.2V and occupying a total chip area of 4.2 mm2.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131568546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649151
F. Sebastiano, R. V. Veldhoven
Front-ends for automotive sensors must digitize multiple channels with high resolution while minimizing their silicon area to save costs. Both channel latency and inter-channel gain mismatch must be minimized to be able to serve multiple sensor applications, ranging from ABS to power steering, with the same front-end. The proposed ΣΔ ADC simultaneously digitizes 3 channels, each with a DR of 86 dB over a 20-kHz BW using a 75-MHz clock. Channel latency is <;40 ns and inter-channel gain mismatch is <;0.2%. The ADC occupies only 0.1 mm2 in a 0.16-μm CMOS process. The small area is enabled by channel multiplexing, allowing component sharing among the channels, and by the large oversampling ratio (OSR), allowing for smaller capacitors.
{"title":"A 0.1-mm2 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR","authors":"F. Sebastiano, R. V. Veldhoven","doi":"10.1109/ESSCIRC.2013.6649151","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649151","url":null,"abstract":"Front-ends for automotive sensors must digitize multiple channels with high resolution while minimizing their silicon area to save costs. Both channel latency and inter-channel gain mismatch must be minimized to be able to serve multiple sensor applications, ranging from ABS to power steering, with the same front-end. The proposed ΣΔ ADC simultaneously digitizes 3 channels, each with a DR of 86 dB over a 20-kHz BW using a 75-MHz clock. Channel latency is <;40 ns and inter-channel gain mismatch is <;0.2%. The ADC occupies only 0.1 mm2 in a 0.16-μm CMOS process. The small area is enabled by channel multiplexing, allowing component sharing among the channels, and by the large oversampling ratio (OSR), allowing for smaller capacitors.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130834539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649080
W. Yan, T. Christen
A CMOS bandgap voltage reference is presented, which achieves a low integrated noise of 150nVrms within a 0.1-10Hz bandwidth and a 37.8nV/√Hz wideband noise floor above 100Hz. The low noise performance is accomplished by employing a multi-stage bandgap topology, which results in an inherent noise advantage compared to a conventional CMOS bandgap. Fabricated in a 0.35μm HV CMOS technology, the bandgap voltage reference consumes 443μA from a nominal 3.4-V supply and occupies 0.5mm2 chip area.
提出了一种CMOS带隙基准电压，在0.1 ~ 10hz带宽范围内实现了150nVrms的低集成噪声，在100Hz以上实现了37.8nV/√Hz的宽带本底噪声。低噪声性能是通过采用多级带隙拓扑来实现的，这与传统的CMOS带隙相比具有固有的噪声优势。该带隙基准电压采用0.35μ v CMOS工艺，标称3.4 v电源功耗为443μA，芯片面积为0.5mm2。
{"title":"A 443-µA 37.8-nV/√Hz CMOS multi-stage bandgap voltage reference","authors":"W. Yan, T. Christen","doi":"10.1109/ESSCIRC.2013.6649080","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649080","url":null,"abstract":"A CMOS bandgap voltage reference is presented, which achieves a low integrated noise of 150nVrms within a 0.1-10Hz bandwidth and a 37.8nV/√Hz wideband noise floor above 100Hz. The low noise performance is accomplished by employing a multi-stage bandgap topology, which results in an inherent noise advantage compared to a conventional CMOS bandgap. Fabricated in a 0.35μm HV CMOS technology, the bandgap voltage reference consumes 443μA from a nominal 3.4-V supply and occupies 0.5mm2 chip area.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124103438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649135
Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae, Nan Xing, J. Woo, Suhwan Kim
In this paper, we propose a time-to-digital converter (TDC) that uses a multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) to compensate for the process and ambient variations. The two PLLs share a single reference clock and have different frequency-division ratios. It also improves the resolution of the TDC. A prototype chip, designed and fabricated in 0.18μm CMOS technology with an active area of 0.40mm2, achieves a 3.4ps of resolution and an input range of 100ns at 2.5M samples/s, while consuming 32mW from a 1.8V supply.
{"title":"High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line","authors":"Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae, Nan Xing, J. Woo, Suhwan Kim","doi":"10.1109/ESSCIRC.2013.6649135","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649135","url":null,"abstract":"In this paper, we propose a time-to-digital converter (TDC) that uses a multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) to compensate for the process and ambient variations. The two PLLs share a single reference clock and have different frequency-division ratios. It also improves the resolution of the TDC. A prototype chip, designed and fabricated in 0.18μm CMOS technology with an active area of 0.40mm2, achieves a 3.4ps of resolution and an input range of 100ns at 2.5M samples/s, while consuming 32mW from a 1.8V supply.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129183046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649077
K. Statnikov, E. Öjefors, J. Grzyb, P. Chevalier, U. Pfeiffer
This paper presents a 0.32 THz high-resolution radar system for short-range applications. It utilizes a homodyne FMCW radar architecture based on a low-cost SiGe HBT chip-set. It is implemented in a 0.13-μm SiGe engineering technology version with cutoff frequencies fT /fmax of 300/350 GHz and offers lens-integrated on-chip antennas. The measured maximum radiated power of the packaged transmitter is -5 dBm (14 dBm EIRP) at 0.311 THz. The 6-dB operational bandwidth of the chip-set is 27 GHz around the center frequency of 0.325 THz. The conversion gain of the receiver including antenna efficiency is -16 to -8 dB and its noise figure is 30-37 dB over the operational bandwidth. The FMCW radar functionality is demonstrated in a face-to-face chip-set configuration.
{"title":"A 0.32 THz FMCW radar system based on low-cost lens-integrated SiGe HBT front-ends","authors":"K. Statnikov, E. Öjefors, J. Grzyb, P. Chevalier, U. Pfeiffer","doi":"10.1109/ESSCIRC.2013.6649077","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649077","url":null,"abstract":"This paper presents a 0.32 THz high-resolution radar system for short-range applications. It utilizes a homodyne FMCW radar architecture based on a low-cost SiGe HBT chip-set. It is implemented in a 0.13-μm SiGe engineering technology version with cutoff frequencies fT /fmax of 300/350 GHz and offers lens-integrated on-chip antennas. The measured maximum radiated power of the packaged transmitter is -5 dBm (14 dBm EIRP) at 0.311 THz. The 6-dB operational bandwidth of the chip-set is 27 GHz around the center frequency of 0.325 THz. The conversion gain of the receiver including antenna efficiency is -16 to -8 dB and its noise figure is 30-37 dB over the operational bandwidth. The FMCW radar functionality is demonstrated in a face-to-face chip-set configuration.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"56 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649088
J. Pernillo, M. Flynn
A 9b 2GS/s ADC architecture interleaves a pair of two-stage pipeline ADCs to achieve high performance with a shared low-gain op-amp and a shared low-accuracy 2nd stage sub-ADC. This technique reduces area and eliminates the need to correct for gain and offset mismatch between channels. The ADC achieves a measured ENOB of 7.07b for a 1GHz signal input sampled at 2GS/s and consumes 45mW from a 1.0V supply, yielding an FOM of 167fJ/conversion-step.
{"title":"A 9b 2GS/s 45mW 2X-interleaved ADC","authors":"J. Pernillo, M. Flynn","doi":"10.1109/ESSCIRC.2013.6649088","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649088","url":null,"abstract":"A 9b 2GS/s ADC architecture interleaves a pair of two-stage pipeline ADCs to achieve high performance with a shared low-gain op-amp and a shared low-accuracy 2nd stage sub-ADC. This technique reduces area and eliminates the need to correct for gain and offset mismatch between channels. The ADC achieves a measured ENOB of 7.07b for a 1GHz signal input sampled at 2GS/s and consumes 45mW from a 1.0V supply, yielding an FOM of 167fJ/conversion-step.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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