Pub Date : 2025-07-19DOI: 10.1016/j.mee.2025.112382
Z. Jahanshah Rad, M. Miettinen, R. Punkkinen, P. Suomalainen, M. Punkkinen, P. Laukkanen, K. Kokko
Ultrahigh vacuum (UHV) environment with the background pressure in the range of 1‧10−15–1‧10−11 bar is common in surface-science experiments, but UHV-based material treatments are rarely used in the current silicon technology. UHV methods might however provide a clear benefit to the technology when atomic-level cleanliness and crystalline order of Si surfaces (interfaces) as well as dry-cleaning methods for the surfaces become relevant to the development of Si devices. We have studied effects of some UHV-based treatments on the properties of Si surfaces and of thin oxide films on Si. Exposing Si, pre-cleaned by the RCA recipe with the final HF dip, to mere hydrogen (H2) gas in UHV chamber at the Si temperature of 200 °C increases a crystalline degree of the Si surface according to low-energy electron diffraction. Effects of postheating in UHV are also studied for different oxidized Si surfaces. Wet chemically oxidized (RCA without HF dip) Si was heated step-by-step up to 800 °C in UHV until the oxide removal is strongly enhanced. Both crystalline degree of the RCA chemical oxide and surface roughness increase with the UHV post-heating at 500–800 °C. Exposing native-oxide covered sidewalls of Si diodes to mere oxygen (O2) gas in UHV chamber at Si temperature of 350 °C (i) increases amount of SiO2 at the sidewalls according to x-ray photoelectron spectroscopy, (ii) decreases amount of the band-gap electron levels at the sidewalls according to scanning tunneling spectroscopy, and (iii) provides a durable decrease in the diode leakage current.
{"title":"Potential of ultrahigh-vacuum based surface treatments in silicon technology","authors":"Z. Jahanshah Rad, M. Miettinen, R. Punkkinen, P. Suomalainen, M. Punkkinen, P. Laukkanen, K. Kokko","doi":"10.1016/j.mee.2025.112382","DOIUrl":"10.1016/j.mee.2025.112382","url":null,"abstract":"<div><div>Ultrahigh vacuum (UHV) environment with the background pressure in the range of 1‧10<sup>−15</sup>–1‧10<sup>−11</sup> bar is common in surface-science experiments, but UHV-based material treatments are rarely used in the current silicon technology. UHV methods might however provide a clear benefit to the technology when atomic-level cleanliness and crystalline order of Si surfaces (interfaces) as well as dry-cleaning methods for the surfaces become relevant to the development of Si devices. We have studied effects of some UHV-based treatments on the properties of Si surfaces and of thin oxide films on Si. Exposing Si, pre-cleaned by the RCA recipe with the final HF dip, to mere hydrogen (H<sub>2</sub>) gas in UHV chamber at the Si temperature of 200 °C increases a crystalline degree of the Si surface according to low-energy electron diffraction. Effects of postheating in UHV are also studied for different oxidized Si surfaces. Wet chemically oxidized (RCA without HF dip) Si was heated step-by-step up to 800 °C in UHV until the oxide removal is strongly enhanced. Both crystalline degree of the RCA chemical oxide and surface roughness increase with the UHV post-heating at 500–800 °C. Exposing native-oxide covered sidewalls of Si diodes to mere oxygen (O<sub>2</sub>) gas in UHV chamber at Si temperature of 350 °C (i) increases amount of SiO<sub>2</sub> at the sidewalls according to x-ray photoelectron spectroscopy, (ii) decreases amount of the band-gap electron levels at the sidewalls according to scanning tunneling spectroscopy, and (iii) provides a durable decrease in the diode leakage current.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112382"},"PeriodicalIF":2.6,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-17DOI: 10.1016/j.mee.2025.112379
Zhoujie Pan , DingYi Zhang , Yanming Liu , He Tian
This paper introduces a new paradigm of memristor-based in-memory stateful logic computing. Based on multi-level co-optimization. In device level, with the aid of Mirrored RRAM Device (MRD), we develop a scheme to build basic logics by a single device in a reconfigurable manner. Furthermore, we also proposed a method for cascading logic to construct more complex logic. Compared to existing architectures, our MRD based method exhibits robustness against voltage and device variations, and eliminates the need for multiple reference voltages. Our method also support execution of more complex logic operations, such as 1-bit full adders, through a cascaded configuration in just three steps using four MRD devices. SPICE simulations have been conducted to validate the feasibility of our approach. These advancements position the MRD as a promising candidate for scalable and efficient in-memory computing applications.
{"title":"A robust and efficient new paradigm for building in-memory stateful logic system with memristor: Based on multi-level co-optimization","authors":"Zhoujie Pan , DingYi Zhang , Yanming Liu , He Tian","doi":"10.1016/j.mee.2025.112379","DOIUrl":"10.1016/j.mee.2025.112379","url":null,"abstract":"<div><div>This paper introduces a new paradigm of memristor-based in-memory stateful logic computing. Based on multi-level co-optimization. In device level, with the aid of Mirrored RRAM Device (MRD), we develop a scheme to build basic logics by a single device in a reconfigurable manner. Furthermore, we also proposed a method for cascading logic to construct more complex logic. Compared to existing architectures, our MRD based method exhibits robustness against voltage and device variations, and eliminates the need for multiple reference voltages. Our method also support execution of more complex logic operations, such as 1-bit full adders, through a cascaded configuration in just three steps using four MRD devices. SPICE simulations have been conducted to validate the feasibility of our approach. These advancements position the MRD as a promising candidate for scalable and efficient in-memory computing applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112379"},"PeriodicalIF":2.6,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study showcases the improvement in conventional SOI n-FinFET devices with the incorporation of a high-K spacer and gate stack (GS) engineering at 10 nm gate length. Three FinFET configurations were considered for comparison, and the simulated results show significant improvements in the analog and RF performance of the proposed configuration. Analog parameters such as the ION/IOFF ratio increased almost 104 times, subthreshold swing reduced by ∼60 %; transconductance increased by ∼92 %, QF improved by ∼382 %, TGF enhanced by ∼302 %, intrinsic gain increased by almost 8 times, and early voltage by almost 5 times, indicating the proposed device is suitable for high-performance CMOS circuits. Further, the RF analysis is performed with parameters like cut-off frequency, GFP, TFP, etc., exhibiting considerable improvement for the proposed configuration. Thus, gate stacking and spacer engineering significantly improve the FinFET performance, enhancing the analog and RF capabilities of semiconductor devices for more efficient integrated circuits.
{"title":"Performance enhancement of a spacer-engineered GS SOI n-FinFET with 10 nm gate length","authors":"Bhavya Kumar , Anurag Somayajula , Vishnu Sajith , Tanish Aggarwal , Rishu Chaujar","doi":"10.1016/j.mee.2025.112383","DOIUrl":"10.1016/j.mee.2025.112383","url":null,"abstract":"<div><div>This study showcases the improvement in conventional SOI n-FinFET devices with the incorporation of a high-K spacer and gate stack (GS) engineering at 10 nm gate length. Three FinFET configurations were considered for comparison, and the simulated results show significant improvements in the analog and RF performance of the proposed configuration. Analog parameters such as the I<sub>ON</sub>/I<sub>OFF</sub> ratio increased almost 10<sup>4</sup> times, subthreshold swing reduced by ∼60 %; transconductance increased by ∼92 %, QF improved by ∼382 %, TGF enhanced by ∼302 %, intrinsic gain increased by almost 8 times, and early voltage by almost 5 times, indicating the proposed device is suitable for high-performance CMOS circuits. Further, the RF analysis is performed with parameters like cut-off frequency, GFP, TFP, etc., exhibiting considerable improvement for the proposed configuration. Thus, gate stacking and spacer engineering significantly improve the FinFET performance, enhancing the analog and RF capabilities of semiconductor devices for more efficient integrated circuits.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112383"},"PeriodicalIF":2.6,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
All semiconductor manufacturers are driving to advance their process efficiency and effectiveness to deliver improved performance. To achieve such improvements with each generation of new semiconductor devices while maintaining high reliability and yield, strict contamination control must be established for process chemicals and gases. Contaminants in these materials can be present in various forms, such as organics, gels, solid particles, anions, cations, polymers, etc., and are typically controlled using membrane-based filtration. To ensure that the appropriate filtration solutions are implemented, a two-step process is required. First, one must identify/characterize the contaminants present in the semiconductor grade chemistry using multiple analytical techniques to develop a diverse profile of contaminants and then use that knowledge to optimize filtration schemes across the supply chain to ensure end-to-end impurity control. In this paper, a hybrid metrology approach was utilized to first understand the contamination profile of semiconductor grade hydrogen peroxide (H2O2) at 30 % concentration then evaluate the effectiveness of different filter membranes in removing these contaminants from the chemical.
{"title":"Use of a hybrid metrology approach to develop holistic filtration solutions in hydrogen peroxide","authors":"Kusum Maharjan , Nicole Williams , Sally Huang , Siddarth Sampath , Briana Dufek , Suhas Ketkar , Austin Schultz","doi":"10.1016/j.mee.2025.112381","DOIUrl":"10.1016/j.mee.2025.112381","url":null,"abstract":"<div><div>All semiconductor manufacturers are driving to advance their process efficiency and effectiveness to deliver improved performance. To achieve such improvements with each generation of new semiconductor devices while maintaining high reliability and yield, strict contamination control must be established for process chemicals and gases. Contaminants in these materials can be present in various forms, such as organics, gels, solid particles, anions, cations, polymers, etc., and are typically controlled using membrane-based filtration. To ensure that the appropriate filtration solutions are implemented, a two-step process is required. First, one must identify/characterize the contaminants present in the semiconductor grade chemistry using multiple analytical techniques to develop a diverse profile of contaminants and then use that knowledge to optimize filtration schemes across the supply chain to ensure end-to-end impurity control. In this paper, a hybrid metrology approach was utilized to first understand the contamination profile of semiconductor grade hydrogen peroxide (H<sub>2</sub>O<sub>2</sub>) at 30 % concentration then evaluate the effectiveness of different filter membranes in removing these contaminants from the chemical.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112381"},"PeriodicalIF":2.6,"publicationDate":"2025-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144604603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-10DOI: 10.1016/j.mee.2025.112378
Hala Mohammad , Bochao Li , Jamilu Tijjani Baraya , Zhenlong Zhao , Xiaowei Song , Jingquan Lin
Extreme ultraviolet (EUV) lithography is crucial for advanced semiconductor manufacturing, relying on sophisticated mask technology to transfer intricate patterns onto silicon wafers. The integrity of the EUV mask blanks is essential for producing high-quality masks and semiconductor devices. However, defects in mask blanks, particularly multilayer phase defects, can significantly degrade lithographic quality, affecting device yield and performance. Actinic blank inspection (ABI) has emerged as the most effective strategy for evaluating the initial quality of EUV mask blanks and identifying defects that may compromise the wafer integrity. Additionally, defect characterization helps determine the nature of the defect, its printability, and its potential for repair. This review surveys recent advancements in ABI and defect characterization, covering a range of methodologies, commercial inspection tools and related research efforts that aimed at improving the detection and characterization of multilayer defects.
{"title":"Actinic defect inspection and characterization for extreme ultraviolet mask blanks","authors":"Hala Mohammad , Bochao Li , Jamilu Tijjani Baraya , Zhenlong Zhao , Xiaowei Song , Jingquan Lin","doi":"10.1016/j.mee.2025.112378","DOIUrl":"10.1016/j.mee.2025.112378","url":null,"abstract":"<div><div>Extreme ultraviolet (EUV) lithography is crucial for advanced semiconductor manufacturing, relying on sophisticated mask technology to transfer intricate patterns onto silicon wafers. The integrity of the EUV mask blanks is essential for producing high-quality masks and semiconductor devices. However, defects in mask blanks, particularly multilayer phase defects, can significantly degrade lithographic quality, affecting device yield and performance. Actinic blank inspection (ABI) has emerged as the most effective strategy for evaluating the initial quality of EUV mask blanks and identifying defects that may compromise the wafer integrity. Additionally, defect characterization helps determine the nature of the defect, its printability, and its potential for repair. This review surveys recent advancements in ABI and defect characterization, covering a range of methodologies, commercial inspection tools and related research efforts that aimed at improving the detection and characterization of multilayer defects.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112378"},"PeriodicalIF":2.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144589063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-09DOI: 10.1016/j.mee.2025.112380
A. Revathy , S. Ravi , A. Lakshmi Narayana , K. Nirmala Devi , Raji Pandurangan
GaN High Electron Mobility Transistors represent a breakthrough technology for biosensing applications, offering exceptional sensitivity through their unique two-dimensional electron gas channel positioned close to the sensing surface. This comprehensive review provides the first systematic analysis of the complete GaN HEMT biosensor ecosystem, distinguishing itself from previous reviews through: (i) Comprehensive coverage of emerging architectural innovations including novel heterostructures, dimensional variants, and advanced gate engineering approaches; (ii) Detailed analysis of MOS-HEMT configurations and their superior performance in physiological media; and (iii) Critical assessment of commercialization challenges and practical implementation strategies. The fundamental advantage of GaN HEMTs lies in their ability to detect minute charge variations from biomolecular interactions with detection limits reaching attomolar concentrations, enabled by the 2DEG channel's proximity (20–30 nm) to the sensing surface. The review systematically examines device architectures ranging from conventional AlGaN/GaN structures to advanced MOS-HEMT designs with dielectric layers that provide 2–3× sensitivity enhancement while improving stability in high ionic strength media. Novel heterostructures including InAlN/GaN systems and N-polar configurations offer up to 4× sensitivity improvements compared to conventional designs. Different gate engineering approaches are analyzed, encompassing dual-gate architectures for differential sensing, recessed designs for enhanced control, and extended-gate configurations for harsh environments.
This review uniquely addresses the critical interface between device physics and practical biosensing through comprehensive analysis of surface functionalization strategies, charge screening mitigation techniques, and biocompatibility considerations. Current limitations including signal drift (0.1–2.0 mV/h), selectivity challenges in complex biological matrices, and manufacturing reproducibility (5–15 % coefficient of variation) are critically evaluated alongside emerging solutions involving differential measurements, anti-fouling surface modifications, and machine learning algorithms. Future developments focus on transformative trends not comprehensively covered in previous reviews: self-powered sensors with integrated energy harvesting, multi-modal detection platforms combining optical and electrochemical sensing, IoT-connected monitoring networks for population-level healthcare, and expanding environmental monitoring applications. These advances position GaN HEMT biosensors as enabling technologies for next-generation healthcare diagnostics, environmental monitoring, and smart sensing ecosystems.
{"title":"Advanced gallium nitride high electron mobility transistors for biosensing applications: Progress, challenges, and future perspectives","authors":"A. Revathy , S. Ravi , A. Lakshmi Narayana , K. Nirmala Devi , Raji Pandurangan","doi":"10.1016/j.mee.2025.112380","DOIUrl":"10.1016/j.mee.2025.112380","url":null,"abstract":"<div><div>GaN High Electron Mobility Transistors represent a breakthrough technology for biosensing applications, offering exceptional sensitivity through their unique two-dimensional electron gas channel positioned close to the sensing surface. This comprehensive review provides the first systematic analysis of the complete GaN HEMT biosensor ecosystem, distinguishing itself from previous reviews through: (i) Comprehensive coverage of emerging architectural innovations including novel heterostructures, dimensional variants, and advanced gate engineering approaches; (ii) Detailed analysis of MOS-HEMT configurations and their superior performance in physiological media; and (iii) Critical assessment of commercialization challenges and practical implementation strategies. The fundamental advantage of GaN HEMTs lies in their ability to detect minute charge variations from biomolecular interactions with detection limits reaching attomolar concentrations, enabled by the 2DEG channel's proximity (20–30 nm) to the sensing surface. The review systematically examines device architectures ranging from conventional AlGaN/GaN structures to advanced MOS-HEMT designs with dielectric layers that provide 2–3× sensitivity enhancement while improving stability in high ionic strength media. Novel heterostructures including InAlN/GaN systems and N-polar configurations offer up to 4× sensitivity improvements compared to conventional designs. Different gate engineering approaches are analyzed, encompassing dual-gate architectures for differential sensing, recessed designs for enhanced control, and extended-gate configurations for harsh environments.</div><div>This review uniquely addresses the critical interface between device physics and practical biosensing through comprehensive analysis of surface functionalization strategies, charge screening mitigation techniques, and biocompatibility considerations. Current limitations including signal drift (0.1–2.0 mV/h), selectivity challenges in complex biological matrices, and manufacturing reproducibility (5–15 % coefficient of variation) are critically evaluated alongside emerging solutions involving differential measurements, anti-fouling surface modifications, and machine learning algorithms. Future developments focus on transformative trends not comprehensively covered in previous reviews: self-powered sensors with integrated energy harvesting, multi-modal detection platforms combining optical and electrochemical sensing, IoT-connected monitoring networks for population-level healthcare, and expanding environmental monitoring applications. These advances position GaN HEMT biosensors as enabling technologies for next-generation healthcare diagnostics, environmental monitoring, and smart sensing ecosystems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112380"},"PeriodicalIF":2.6,"publicationDate":"2025-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144614334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-03DOI: 10.1016/j.mee.2025.112377
Yixian Song , Hao Cai , Dawei Gao , Kai Xu
Bipolar-CMOS-DMOS (BCD) is the mainstream manufacturing technology for power management integrated circuits (PMIC), with laterally diffused metal-oxide semiconductor (LDMOS) devices serving as the core component. This review provides a comprehensive overview of LDMOS device structures, manufacturing processes, and applications. It discusses the fundamental structure and working principles, encompassing the manufacturing processes, critical technological features, and industry-specific module descriptions. Furthermore, it introduces device optimization strategies
tailored to various application scenarios. By integrating insights from both industry and academia, this review highlights emerging trends and challenges in the field, offering a forward-looking perspective on LDMOS advancements and future research directions.
{"title":"A review on structure and manufacturing optimization of LDMOS devices","authors":"Yixian Song , Hao Cai , Dawei Gao , Kai Xu","doi":"10.1016/j.mee.2025.112377","DOIUrl":"10.1016/j.mee.2025.112377","url":null,"abstract":"<div><div>Bipolar-CMOS-DMOS (BCD) is the mainstream manufacturing technology for power management integrated circuits (PMIC), with laterally diffused metal-oxide semiconductor (LDMOS) devices serving as the core component. This review provides a comprehensive overview of LDMOS device structures, manufacturing processes, and applications. It discusses the fundamental structure and working principles, encompassing the manufacturing processes, critical technological features, and industry-specific module descriptions. Furthermore, it introduces device optimization strategies</div><div>tailored to various application scenarios. By integrating insights from both industry and academia, this review highlights emerging trends and challenges in the field, offering a forward-looking perspective on LDMOS advancements and future research directions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112377"},"PeriodicalIF":2.6,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1016/j.mee.2025.112376
L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán
This work presents a comprehensive analysis of the variability and reliability of the resistive switching (RS) behavior in Prussian Blue (a mixed-valence iron(III/II) hexacyanoferrate compound) thin films, used as the active layer. These films are fabricated through a simple and scalable electrochemical process, and exhibit robust bipolar resistive switching, making them suitable both for neuromorphic computing applications and hardware cryptography. A detailed statistical evaluation was conducted over 100 consecutive switching cycles using multiple parameter extraction techniques to assess cycle-to-cycle (C2C) variability in key RS parameters, including set/reset voltages and corresponding currents. One and two-dimensional coefficients of variation (1DCV and 2DCV) were calculated to quantify variability and identify application potential. Results demonstrate moderate variability compatible with neuromorphic computing and cryptographic functionalities, including physical unclonable functions and true random number generation. These findings position Prussian Blue-based memristors as promising candidates for low-cost, stable, and multifunctional memory.
{"title":"Variability analysis in memristors based on electrodeposited prussian blue","authors":"L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán","doi":"10.1016/j.mee.2025.112376","DOIUrl":"10.1016/j.mee.2025.112376","url":null,"abstract":"<div><div>This work presents a comprehensive analysis of the variability and reliability of the resistive switching (RS) behavior in Prussian Blue (a mixed-valence iron(III/II) hexacyanoferrate compound) thin films, used as the active layer. These films are fabricated through a simple and scalable electrochemical process, and exhibit robust bipolar resistive switching, making them suitable both for neuromorphic computing applications and hardware cryptography. A detailed statistical evaluation was conducted over 100 consecutive switching cycles using multiple parameter extraction techniques to assess cycle-to-cycle (C2C) variability in key RS parameters, including set/reset voltages and corresponding currents. One and two-dimensional coefficients of variation (1DCV and 2DCV) were calculated to quantify variability and identify application potential. Results demonstrate moderate variability compatible with neuromorphic computing and cryptographic functionalities, including physical unclonable functions and true random number generation. These findings position Prussian Blue-based memristors as promising candidates for low-cost, stable, and multifunctional memory.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112376"},"PeriodicalIF":2.6,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144510669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-16DOI: 10.1016/j.mee.2025.112374
Giulio Galderisi , Thomas Mikolajick , Jens Trommer
Assessing the reliability of emerging device technologies is of fundamental importance to facilitate their adoption in larger scale electronic circuits and systems. This is even more true for all those devices whose unique behavior paves the way towards innovative circuit solutions, but also poses new reliability concerns that are not well known as in established technologies such as CMOS. In this paper, we thoroughly discuss the bias temperature instability (BTI) reliability features of three-independent-gate reconfigurable field effect transistors (RFETs). This multi-gate transistor technology is characterized by the unique feature of providing volatile polarity and threshold control within an individual device. While these devices are subjected to positive and negative BTI in alternating fashion during circuit operation, we identified negative BTI to be the worst-case condition with respect to performance degradation of RFETs in terms of threshold voltage shift and sub-threshold slope reduction. In addition we could reveal clear phenomenological differences in the degradation if the stress profiles are applied to the gates that turn on and off the transistors, rather than when they are applied to the ones that program their polarity. Positive BTI generally produces negligible effects on the threshold voltage shifts, while it has a certain impact on the sub-threshold slope degradation of one of the operational modes of the considered transistors.
{"title":"Impact of Bias temperature instability on reconfigurable field effect transistors and circuits","authors":"Giulio Galderisi , Thomas Mikolajick , Jens Trommer","doi":"10.1016/j.mee.2025.112374","DOIUrl":"10.1016/j.mee.2025.112374","url":null,"abstract":"<div><div>Assessing the reliability of emerging device technologies is of fundamental importance to facilitate their adoption in larger scale electronic circuits and systems. This is even more true for all those devices whose unique behavior paves the way towards innovative circuit solutions, but also poses new reliability concerns that are not well known as in established technologies such as CMOS. In this paper, we thoroughly discuss the bias temperature instability (BTI) reliability features of three-independent-gate reconfigurable field effect transistors (RFETs). This multi-gate transistor technology is characterized by the unique feature of providing volatile polarity and threshold control within an individual device. While these devices are subjected to positive and negative BTI in alternating fashion during circuit operation, we identified negative BTI to be the worst-case condition with respect to performance degradation of RFETs in terms of threshold voltage shift and sub-threshold slope reduction. In addition we could reveal clear phenomenological differences in the degradation if the stress profiles are applied to the gates that turn on and off the transistors, rather than when they are applied to the ones that program their polarity. Positive BTI generally produces negligible effects on the threshold voltage shifts, while it has a certain impact on the sub-threshold slope degradation of one of the operational modes of the considered transistors.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112374"},"PeriodicalIF":2.6,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of nanotechnology has had a significant impact on thermoelectric generators (TEGs), which are expected to play a vital role in meeting sustainable energy requirements. In an integrated micro-thermoelectric device, any change in peripheral parts such as metal/semiconductor contacts may affect thermoelectric (TE) power generation. In this study, we evaluated the TE performance of silicon-based micro-TEGs by varying the metal/Silicon contact arrays on the hot and cold side pads to investigate the effect of the contact array in TE devices. The results show that the device's performance has been influenced by a variation of temperature gradient that happened through the silicon-nanowires due to the alternation of contact arrays.
{"title":"Impact of metal/semiconductor contact layout on the performance of an integrated silicon cavity-free micro thermoelectric generator","authors":"Md Mehdee Hasan Mahfuz, Shuhei Arai, Yuma Miyake, Takeo Matsuki, Takanobu Watanabe","doi":"10.1016/j.mee.2025.112365","DOIUrl":"10.1016/j.mee.2025.112365","url":null,"abstract":"<div><div>The development of nanotechnology has had a significant impact on thermoelectric generators (TEGs), which are expected to play a vital role in meeting sustainable energy requirements. In an integrated micro-thermoelectric device, any change in peripheral parts such as metal/semiconductor contacts may affect thermoelectric (TE) power generation. In this study, we evaluated the TE performance of silicon-based micro-TEGs by varying the metal/Silicon contact arrays on the hot and cold side pads to investigate the effect of the contact array in TE devices. The results show that the device's performance has been influenced by a variation of temperature gradient that happened through the silicon-nanowires due to the alternation of contact arrays.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112365"},"PeriodicalIF":2.6,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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