Microelectronic Engineering最新文献

The resistive RAM (RRAM) based in-memory computation is a promising technology to overcome the Von-Neumann bottleneck to provide fast and efficient computation. The RRAM is the most appropriate choice for cryptographic applications like encryption/decryption in which the data is computed and stored in the memory itself which enhances the security. The variability issue of RRAM namely switching or device parameter variations and cycle-to-cycle variations deteriorates the functionality of RRAM based circuits. In this paper, the XOR gate with V/R-R logic and a 4-bit encryption/decryption process are implemented using the RRAM Stanford model integrated in the Cadence circuit simulator. The output voltage variations of XOR gate and the encryption/decryption by varying switching and cycle-to-cycle parameters are analyzed. The range of switching parameters of the model that provides the accurate outputs of XOR gate and encryption/decryption is determined.

In the lithography process, mask defect is inevitably replicated on chips hence the yield and quality of the product are directly related to the mask quality. Mask microscopy resolution is then an essential specification. In this work, a high-efficiency method for enhancing the resolution of mask defect is proposed based on illumination optimization and Wiener deconvolution. To validate this approach, we established a verification apparatus designed to achieve a theoretical resolution of 3.0 μm with visible light. Remarkably, the empirical results demonstrated that the actual resolution attained is as low as 2.5 μm. The verification demonstrates a significant improvement for various periodic fringes. Moreover, the augmented capability of the apparatus facilitates the identification of mask defects. Although the experiment is carried out for the visible wavelength, the research is specifically designed for the working conditions suitable for EUV mask detection based on the preparatory work for the EUV.

Two-dimensional (2D) materials may be used to fabricate electronic devices and circuits with enhanced electronic properties. Memristors made of hexagonal boron nitride (h-BN) have shown potential for many applications; however, in most cases they are tested using the current limitation tool of the semiconductor parameter analyzer, which does not match real circuit implementations and produces current overshoots. In this article, we present the first all-2D materials-based one-transistor- one-memristor (1T1M) cells exhibiting threshold-type RS. We connect 4 μm² molybdenum disulfide (MoS₂) transistors in series with 0.3 μm² h-BN memristors, leading 1T1M cells able to self-limiting the current. The switching is observed at low voltages below 1 V for >1000 cycles. Our results are a step forward towards the use of 2D materials in electronic devices and circuits.

Reservoir computing (RC) system, featured by its recursive structure, has been utilized for temporal signal processing, offering both low power consumption and high computational speed. This work reports on a novel input delay reservoir computing (ID-RC) system based on the oxide memristors, which can be applied to temporal signal prediction. The particle swarm optimization (PSO) algorithm is employed in the ID-RC system to obtain optimal hyperparameters for multi-step prediction in the Mackey-Glass task, with a normalized root-mean-square error (NRMSE) of only 0.09 at the 20th step. Significantly, by employing the ID-RC system in temporal signal prediction of the Hénon map and the nonlinear autoregressive moving average (NARMA10), small NRMSEs of 0.047 and 0.017 were achieved, respectively. The memristor-based ID-RC system turns out to be highly promising in forecasting of chaotic time series.

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (V_BL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (${\sigma }_{\mathrm{var}}$), and bias voltages (V_Bias). Our results reveal that the RWM increases as the V_BL approaches the V_BL-max. Larger arrays lead to an increased leakage current difference, while larger ${\sigma }_{\mathrm{var}}$ values result in decreased cell current difference and V_BL-max. The decrease in V_BL-max further deteriorates the RWM. Additionally, we analyze the optimal V_Bias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal V_Bias depends on OTS devices and array sizes.

Electrical characteristics of Si_0.7Ge_0.3/Si heterostructure-based n-type gate-all-around MOSFETs (GAA MOSFETs) are reported in this work through experimental and numerical simulation data. N-type GAA MOSFETs of varying lengths (60 nm to 160 nm) and widths (20 nm to 42 nm) are fabricated and measured to extract key electrical parameters like ON current, ON-to-OFF current ratio, threshold voltage, DIBL, and subthreshold swing. Moreover, the influence of tensile strain on carrier transport parameters in the buried Si layer is examined in this work. The Ge mole fraction in SiGe is raised from 0.2 to 0.3, and the corresponding changes in XX-stress, and current density are analyzed using a TCAD simulator. The performance of the proposed device has also been compared with unstrained SiGe/Si, all Si, and SiGe-based GAA MOSFETs.

Molybdenum disulfide (MoS₂) serves as the representative transition metal dichalcogenide material, showing promise for diverse applications owing to its outstanding properties. Extensive research has been conducted on the growth of large-scale MoS₂ films using chemical vapor deposition (CVD) with seeding accelerators for various device applications. In this study, we investigated the growth of large-scale MoS₂ films for potential applications, in which our approach utilized CVD with a homogeneous nanosheet promoter (MoS₂ flakes) and effectively minimized residue creation. Optical and structural analyses confirmed the successful synthesis of a large-scale MoS₂ layer. Moreover, the decoration of metallic nanoparticles on the MoS₂ surface was employed to enhance the functionalities of application devices such as optical sensors and gas sensors. The capability of MoS₂ to act as a nucleation site for nanoparticles during synthesis offered an intriguing pathway for augmenting the attachment and performance of nanoparticles on the MoS₂ surface. The photodetector, integrating a hybrid MoS₂ layer and Cu nanoparticles, exhibited superior photodetection properties, attributed to the increased excitons at the interface between the metal electrodes and MoS₂ films. Furthermore, in order to enhance the characteristics of the gas sensor, Pd nanoparticles were incorporated during the synthesis of MoS₂ layers. This dynamic interface between Pd particles and MoS₂ films presents an opportunity to explore novel materials with enhanced catalytic properties.

This paper investigates the dependence of frequency stability over temperature on support tethers in dual-beam piezoresistive length-extensional (LE) mode microelectromechanical systems (MEMS) resonators. The designed dual-beam resonator consists of two identical single-crystal silicon beams, which are mechanically coupled and excited into vibrating in opposite phase to eliminate the inherent capacitive feedthrough signals. Both straight and folded beams are adopted as the support tethers for the reported dual-beam piezoresistive resonators. Quality factor (Q) and temperature distribution across the resonators with various support tethers are investigated by finite element method (FEM) analysis. It is found that folded beam tethers can reduce the support loss and hence improve the Q for the designed dual-beam resonator, while it comes with a tradeoff of high temperature rise on resonator body. The reported dual-beam resonator with straight beam tethers has low temperature rise on the resonator body, which is less sensitive to environmental temperature fluctuations, compared to its counterpart with folded beam tethers. Experimental results show that the fabricated dual-beam piezoresistive resonator with four straight beam tethers achieves a 0.5 ppm frequency shifts in the temperature-control chamber, which is nearly four times better than those with folded beam tethers.

The vacuum channel transistor has emerged as a promising candidate for next-generation technology due to its intriguing features compared to the conventional field effect transistor. Nanoscale vacuum channel transistors have a particular advantage due to the promise of vacuum-like ballistic transport, radiation insensitivity, and nanoscale dimensions. Unlike field emission devices, nanoscale vacuum channel transistors can induce electron emission at a desired temperature; sharp and thin emitters on the cathode are desired to increase field emission. This article provides a comprehensive overview of recent research advancements. It begins with a brief introduction to vacuum transistors and their miniaturization to the nanoscale. Then, recent advancements in different architectures with vacuum gaps, including their physical properties, fabrication methods, and device applications, are discussed. Finally, this review concludes by highlighting some challenges and perspectives in this emerging field.

SnZn (tin‑zinc) solder has been regarded as a promising lead-free solder material with a low melting point of 198 °C, serving as a suitable alternative to both SnPb solder due to its lack of hazardous substances and Sn-Ag-Cu solder because of the high cost associated with silver. Nonetheless, its susceptibility to oxidation hinders solderability and increases soldering defects such as bridging, insufficient fillings, and voids, limiting its use in commercial production. Devices designed with through-hole technology, in contrast to surface-mounted ones, continue to exhibit superior interconnection reliability in such applications. In this investigation on wave soldering, a newly developed lead-free solder, composed of 87% tin, 9% zinc, 2.5% bismuth, and 1.5% indium by weight, was employed under two conditions related to nitrogen content: 1) Ensuring that static oxygen content remained below 3000 ppm. 2) Maintaining soldering section oxygen content below 600 ppm at a conveyor speed of 1200 mm/min. The soldering results were examined at various temperatures of preheating and soldering. It proves that the measured peak temperature of liquid solder T_pL over 230 °C makes the bridging defect rate lower than 0.30%. Additionally, setting the peak temperature of solder joint T_pZ above 220 °C, along with specific preheating temperatures (105/115/135/145 °C), archives 100% vertical filling without significant voids in the solder joints. Moreover, optimizing wave soldering settings, specifically adjusting the wave soldering setting temperature T_s to 235 °C, conveyor speed v_c to 1000 mm/min, resolves soldering defects associated with Sn-9Zn-2.5Bi-1.5In alloy in wave process.

Relevance summary

• 1.

  T_pL surpasses 230 °C, the total number of bridging defects per board decreases to fewer than 6, approximately 0.30%. T_pZ values of 220 °C or higher results in 100% vertical fill and no significant large voids, demonstrating optimal filling effects

• 2.

  Under the conditions of T_S = 235 °C and v_c = 1000 mm/min yield T_pL > 230 °C and T_pZ > 210.9 °C, it leads to a reduction in bridging defects.

• 3.

  To maintain flux efficiency and minimize internal voids, an optimal selection of preheating temperatures (105/115/135/145 °C) is demonstrated.

• 4.

  An integrated nitrogen content-controlled system is utilized to eliminate oxygen from the solder pot, aiming to prevent oxidation.