Microelectronic Engineering最新文献

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On the mechanical properties of ultrathin titanium nitride films under different gas ratios of PVD process 论 PVD 工艺中不同气体比例下超薄氮化钛薄膜的力学性能

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-11-03 DOI: 10.1016/j.mee.2024.112283

Yao-Zih Lai , Weileun Fang

Titanium Nitride (TiN_x) thin film has numerous applications in semiconductors, nanotechnology, and various aspects of daily life. This study presents an approach to adjusting the mechanical properties of TiN_x ultrathin films, including Young's modulus, residual stress, and coefficients of thermal expansion (CTE), by varying the gas ratio of N₂ and Ar during the Physical Vapor Deposition (PVD) process (DC magnetron sputtering). In the experiment, TiN_x films with three different gas ratios R_N (= N₂/(N₂ + Ar)) were investigated. To demonstrate the feasibility of this approach, TiN_x films with different R_N values (0.3, 0.5, and 0.8) were deposited on SiO₂ beams to form composite test cantilevers. Measurements reveal significant changes (ranging from 33 % to 2-fold) in Young's modulus, residual stress, and CTE of the TiN_x films by varying the gas ratio during the PVD process. As a result, this study provides a straightforward approach and guidelines for users to tailor TiN_x films according to specific application requirements.

氮化钛（TiNx）薄膜在半导体、纳米技术和日常生活的各个方面有着广泛的应用。本研究提出了一种在物理气相沉积（PVD）过程（直流磁控溅射）中通过改变 N2 和 Ar 的气体比例来调整 TiNx 超薄薄膜机械性能的方法，包括杨氏模量、残余应力和热膨胀系数（CTE）。实验中研究了三种不同气体比例 RN（= N2/（N2 + Ar））的 TiNx 薄膜。为了证明这种方法的可行性，在二氧化硅梁上沉积了不同 RN 值（0.3、0.5 和 0.8）的 TiNx 薄膜，以形成复合测试悬臂。测量结果表明，通过在 PVD 过程中改变气体比例，TiNx 薄膜的杨氏模量、残余应力和 CTE 都发生了显著变化（从 33% 到 2 倍不等）。因此，这项研究为用户根据特定应用要求定制 TiNx 薄膜提供了直接的方法和指导。

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引用次数: 0

A 10 kHz bandwidth low-power active negative feedback front-end amplifier based on unipolar IZO TFT technology 基于单极 IZO TFT 技术的 10 kHz 带宽低功耗有源负反馈前端放大器

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-11-01 DOI: 10.1016/j.mee.2024.112282

Mingjian Zhao, Yunfang Wang, Xinge Shi, Bin Li, Rongsheng Chen, Zhaohui Wu

In this paper, we present a wide-bandwidth low-power front-end amplifier based on thin-film transistors (TFTs). The amplifier with the active negative feedback structure in the form of the common source is proposed, which achieves wide bandwidth under the condition of low power consumption. In addition, the capacitor bootstrap load structure is used in the core operational transconductance amplifier (OTA) circuit, which improves the loop gain. The proposed amplifier adopts the 10 μm channel length unipolar n-type indium‑zinc-oxide (IZO) TFT technology, with an area of 2 mm². The test results show a gain of 36.3 dB, a bandwidth of 10 kHz, and a power consumption of 0.04 mW at a supply voltage of 10 V. The proposed amplifier is advanced in bandwidth, power, and area, has successfully obtained and amplified real-time electrocardiogram (ECG) and electromyography (EMG) signals, and also has excellent noise efficiency factor (NEF) and power efficiency factor (PEF). Therefore, the design has potential in the field of flexible bioelectrical signal detection and other wearable electronic devices in the future.

本文提出了一种基于薄膜晶体管（TFT）的宽带低功耗前端放大器。该放大器采用共源形式的有源负反馈结构，在低功耗条件下实现了宽带宽。此外，在核心运算跨导放大器（OTA）电路中采用了电容自举负载结构，从而提高了环路增益。所提出的放大器采用 10 μm 沟道长度的单极 n 型氧化铟锌（IZO）TFT 技术，面积为 2 mm2。测试结果表明，在 10 V 电源电压下，放大器的增益为 36.3 dB，带宽为 10 kHz，功耗为 0.04 mW。所提出的放大器在带宽、功耗和面积方面都很先进，成功地获取并放大了实时心电图（ECG）和肌电图（EMG）信号，还具有出色的噪声效率因子（NEF）和功率效率因子（PEF）。因此，该设计在未来的柔性生物电信号检测和其他可穿戴电子设备领域具有潜力。

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引用次数: 0

Dynamics of set and reset processes in HfO2 -based bipolar resistive switching devices 基于 HfO2 的双极电阻开关器件中的设定和复位过程的动态变化

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-10-28 DOI: 10.1016/j.mee.2024.112281

G. Vinuesa , H. García , M.B. González , F. Campabadal , H. Castán , S. Dueñas

The temporal evolution of the set and reset processes in TiN/Ti/HfO₂/W metal-insulator-metal devices exhibiting resistive switching behavior is investigated in depth. To this end, current transients were recorded by applying different voltages, which allowed us to change the conductance of the device. While both set and reset transitions are faster with increasing applied voltage, they clearly exhibit different time responses. The set transition is characterized by a monotonic increase in current after a sudden initial rise in its value, while the reset transition is characterized by a notably nonlinear response that resembles a sigmoidal function. We have successfully modeled the reset current transient with a bi-dose function and defined its time constant (Time-to-Reset) as the time where the current variation reaches its maximum value. Our findings show that varying the initial conditions of the reset process, such as increasing the temperature and/or decreasing the initial resistance value, significantly affect the reset transient, exponentially increasing the reset time constant value. This allows us to model its dependencies with the equation of a plane.

我们深入研究了表现出电阻开关行为的 TiN/Ti/HfO2/W 金属绝缘体-金属器件中设定和复位过程的时间演变。为此，我们通过施加不同的电压来记录瞬态电流，从而改变器件的电导率。虽然设定和复位转换随着施加电压的增加而加快，但它们明显表现出不同的时间响应。设定转换的特点是电流值在最初突然上升后单调上升，而复位转换的特点则是明显的非线性响应，类似于正余弦函数。我们成功地用双剂量函数模拟了复位电流瞬态，并将其时间常数（复位时间）定义为电流变化达到最大值的时间。我们的研究结果表明，改变复位过程的初始条件（如提高温度和/或降低初始电阻值）会显著影响复位瞬态，并以指数形式增加复位时间常数值。因此，我们可以用平面方程来模拟其相关性。

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引用次数: 0

A novel high-Q Lamé mode bulk acoustic resonator 新型高 Q 值拉美模式体声谐振器

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-10-22 DOI: 10.1016/j.mee.2024.112279

Zeyu Wu , Bo Niu , Yiyi Hong , Junyuan Zhao , Yinfang Zhu , Jinling Yang

This study introduces a novel high-Q Lamé mode MEMS resonator, optimized through support beam structures and etching hole distributions to minimize anchor losses and thermal elastic dissipation (TED). Fabricated using a Silicon-On-Insulator (SOI) process, the resonators achieved Q values of 129,200 and 102,100 in different designs, demonstrating significant improvements in vacuum conditions and highlighting air damping as a key loss mechanism. Nonlinear analysis revealed material nonlinearity dominance. These findings offer valuable guidelines for developing high-end MEMS devices, such as low phase noise oscillators and high-resolution sensors, by showcasing substantial reductions in energy dissipation and enhanced Q factors through structural optimizations.

本研究介绍了一种新型高 Q 值拉美模式 MEMS 谐振器，该谐振器通过支撑梁结构和蚀刻孔分布进行了优化，以最大限度地减少锚损耗和热弹性耗散 (TED)。谐振器采用绝缘体上硅（SOI）工艺制造，在不同的设计中分别达到了 129,200 和 102,100 的 Q 值，显示出真空条件下的显著改善，并突出了空气阻尼这一关键损耗机制。非线性分析表明材料非线性占主导地位。这些发现为开发高端 MEMS 器件（如低相位噪声振荡器和高分辨率传感器）提供了宝贵的指导，通过结构优化大幅降低了能量耗散并提高了 Q 值。

引用次数: 0

Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices 基于三端氧化物电阻开关器件的非易失性逻辑门和全加法器

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-10-21 DOI: 10.1016/j.mee.2024.112280

Jifang Cao , Jiabao Ye , Tao Wang , Yong Ding , Ran Cheng , Dong Liu , Bing Chen

Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.

当今的片上计算能力受到冯-诺依曼瓶颈造成的 "内存墙 "和 "电源墙 "的限制。作为一种潜在的解决方案，这项研究开发了基于场效应三端氧化物电阻开关存储器件（3T-RRAM）的非易失性逻辑门。该研究提出了一个使用多项式控制源 (PCS) 的紧凑型电路模型，用于描述所制造的 3T-RRAM 的行为。3T-RRAM 可被视为用于构建非易失性逻辑门的非易失性传输门。此外，仅使用 8 个 3T-RRAM （4 个非易失性逻辑门）就设计出了具有输入存储功能的全加法器，并提出了基于 3T-RRAM 逻辑门阵列的二值化神经网络 (BNN)。这证明了非易失性逻辑门在内存计算应用中的巨大潜力。

引用次数: 0

Simulations of X-ray focusing by zone plates in rotationally symmetric optical field utilizing the matrix-free Finite Difference Beam Propagation Method 利用无矩阵有限差分光束传播法模拟旋转对称光场中区板聚焦 X 射线的过程

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-10-19 DOI: 10.1016/j.mee.2024.112278

Hao Quan, Xujie Tong, Qingxin Wu, Qiucheng Chen, Yifang Chen

We present the use of a finite difference method based on Crank-Nicholson scheme and recurrence scheme for computationally efficient simulation of the X-ray propagation through a zone plate. By introducing boundary and central conditions and by avoiding large matrix operations, the method achieves considerable speed, little memory occupation and low background noise. Accommodating refractive index profiles of arbitrary shape, it can be applied to assist optimizing X-ray zone plates and understanding focusing mechanism.

我们介绍了一种基于 Crank-Nicholson 方案和递推方案的有限差分法，用于高效计算模拟 X 射线在区块板上的传播。通过引入边界条件和中心条件以及避免大型矩阵运算，该方法实现了相当快的速度、较少的内存占用和较低的背景噪声。该方法适用于任意形状的折射率剖面，可用于协助优化 X 射线区板和了解聚焦机制。

引用次数: 0

Electron trapping in HfO2 layer deposited over a HF last treated silicon substrate 沉积在经过高频最后处理的硅衬底上的二氧化铪层中的电子陷阱

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-10-09 DOI: 10.1016/j.mee.2024.112277

L. Sambuco Salomone , M.V. Cassani , M. Garcia-Inza , S. Carbonetto , E. Redin , F. Campabadal , A. Faigón

Electron trapping in HfO₂-based MOS structures was studied through pulsed capacitance-voltage (C-V) technique. 10 nm HfO₂ layer was deposited by atomic layer deposition over a HF last treated Si substrate. The C-V curves were observed to shift to positive voltages driven by the positive applied voltage along the pulses, consistent with electron trapping due to tunneling transitions between the substrate and pre-existing defects within the oxide and the subsequent lattice relaxation through electron-phonon interaction. The dependences of the voltage shift for a given capacitance value (ΔV_C) with stress bias and time, allowed to distinguish two mechanisms. An initial trapping process occurs for times shorter than the microsecond, probably associated with a thin non-stoichiometric SiO_x interfacial layer, which is followed by a trapping process that starts after tens of μs and progressively slowed down, associated with traps within the HfO₂ layer. Numerical simulations yield for the HfO₂ traps an energy of 1.3 eV below the conduction band edge, decreasing exponentially with the distance from the Si interface with a characteristic length of 1.7 nm; and phonon and relaxation energies of 50 meV and 1 eV, respectively. These physical parameters are consistent with previous reports of electron trapping in HfO₂ layers deposited on a controlled interfacial layer, suggesting that trapping properties of defects inside the HfO₂ layer are insensitive to the treatment of the Si surface before HfO₂ deposition. On the other hand, the observed large initial trapping suggests that the non-controlled SiO_x interfacial region is more defective than a controlled one.

通过脉冲电容-电压（C-V）技术研究了基于 HfO2 的 MOS 结构中的电子捕获。在经过高频最后处理的硅基底上通过原子层沉积沉积了 10 nm 的 HfO2 层。在脉冲正向施加电压的驱动下，C-V 曲线向正电压方向移动，这与基底和氧化物内部预先存在的缺陷之间的隧道转换导致的电子捕获以及随后通过电子-声子相互作用产生的晶格弛豫是一致的。在给定电容值（ΔVC）下，电压偏移与应力偏置和时间的关系可以区分两种机制。最初的捕获过程发生在短于微秒的时间内，可能与薄的非化学计量 SiOx 界面层有关；随后的捕获过程在几十微秒后开始，并逐渐减慢，与 HfO2 层内的捕获有关。数值模拟结果显示，HfO2 陷阱的能量低于导带边缘 1.3 eV，随着与硅界面距离的增加呈指数递减，特征长度为 1.7 nm；声子能量和弛豫能量分别为 50 meV 和 1 eV。这些物理参数与之前关于沉积在受控界面层上的 HfO2 层中电子捕获的报道一致，表明 HfO2 层内缺陷的捕获特性对 HfO2 沉积前硅表面的处理不敏感。另一方面，观察到的大量初始捕获表明，非受控氧化硅界面区比受控界面区缺陷更大。

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引用次数: 0

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash 为三级单元 3D NAND 闪存设计超晶格铁电-金属场效应晶体管

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-09-24 DOI: 10.1016/j.mee.2024.112276

Sola Woo , Gihun Choe , Asif Islam Khan , Suman Datta , Shimeng Yu

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

研究了基于超晶格铁电-金属场效应晶体管（SL-FeMFET）的三维 NAND 架构（3D NAND），用于三电平单元（TLC）操作。SL-FeMFET 展示了一种使用铁电/介电/铁电超晶格设计栅极堆栈的新方法，可实现 3D NAND 架构的大内存窗口 ∼ 3.48 V，程序/擦除电压为 ±7 V。通过 TCAD 建模，我们演示了 SL-FeMFET 的 TLC 运行，改善了存储器窗口，并减轻了 FeMFET 结构中浮动金属层引起的变化。此外，当垂直栅极堆叠从 256 层增加到 512 层时，我们使用页面缓冲电路对 TLC 检测的读出电流和 7 次读取操作中的最坏情况进行了研究。仿真结果表明，基于 SL-FeMFET 的 3D NAND 架构可以在 512 层上运行，并为 TLC 运行提供足够的感应裕量。

引用次数: 0

Optimizing dose parameters for enhanced maskless lithography in MoS2-based devices 优化剂量参数以增强基于 MoS2 器件的无掩模光刻技术

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-09-19 DOI: 10.1016/j.mee.2024.112275

Hyun Min Park, Hyeon Woo Park, Muhammad Suleman, Minwook Kim, Sunil Kumar, Yongho Seo

Maskless lithography simplifies the fabrication process and reduces costs compared to electron beam (E-beam) lithography, making it a more efficient choice for patterning nano-devices. Maskless lithography presents a promising avenue for expediting device fabrication by eliminating the need for masks. This technique can streamline the production of basic electronic devices, offering an efficient and low-cost alternative to traditional lithographic methods, like E-beam lithography. This study utilized a 405 nm photodiode to achieve pattern-writing with a minimum linewidth of 1 μm. Exploring optimal parameters includes adjustments in beam intensity, scan speed, and step size. Maskless lithography was applied to 2D transition metal dichalcogenides (TMDCs) material, MoS₂, to investigate their electrical transport characteristics. The fabricated device exhibits an ON/OFF ratio of ∼1.7 × 10⁶ and a mobility of ∼0.833 cm²/V·s, indicating a high switching efficiency. The results demonstrate optimized maskless lithography's potential for swift and cost-effective fabrication, offering intermediate-resolution patterning capabilities.

与电子束（E-beam）光刻法相比，无掩膜光刻法简化了制造过程并降低了成本，使其成为纳米器件图案化的更有效选择。无掩模光刻技术无需掩模，为加快器件制造提供了一条大有可为的途径。这种技术可以简化基本电子器件的生产，为电子束光刻等传统光刻方法提供了一种高效、低成本的替代方法。这项研究利用 405 纳米光电二极管实现了最小线宽为 1 微米的图案刻写。探索最佳参数包括调整光束强度、扫描速度和步长。无掩模光刻技术应用于二维过渡金属二卤化物（TMDCs）材料 MoS2，以研究其电传输特性。制备的器件的导通/关断比为 1.7 × 106，迁移率为 0.833 cm2/V-s，显示出很高的开关效率。这些结果表明，优化的无掩模光刻技术具有快速、经济地制造器件的潜力，并能提供中等分辨率的图案化能力。

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引用次数: 0

High density nanofluidic channels by self-sealing for metallic nanoparticles detection 用于金属纳米粒子检测的自密封高密度纳米流体通道

IF 2.6 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2024-09-10 DOI: 10.1016/j.mee.2024.112264

Wentao Yuan , Qingxin Wu , Shuoqiu Tian , Jinyu Guo , Kangping Liu , Yifang Chen

High density nanofluidic channels were successfully fabricated by a novel process, nicknamed as self-sealing process, for the detection of metal nanoparticles dispersed in water using color changes excited by polarized electromagnetic waves. The permittivities of aqueous solutions with various concentrations of metal nanoparticles were calculated by a corrected plasma model. Systematic simulations using finite difference time domain method were carried out in investigating the detection capabilities of the nanofluidic channels for silver, beryllium and copper nanoparticles in water. The pronounced color shifts indicates that the channels possess high sensitivity in the metal nanoparticles detection. The designed nanofluidic channels were then fabricated by a direct flood deposition of a silica film on a pre-replicated hydrogen silsesquioxan (HSQ) grating using electron beam lithography (EBL). The self-sealing technique possesses advantages in simplified processing, encapsulation free and potential of multi-layer nanochannels.

通过一种昵称为 "自密封工艺 "的新工艺成功制造了高密度纳米流体通道，用于利用偏振电磁波激发的颜色变化检测分散在水中的金属纳米颗粒。采用修正等离子体模型计算了含有不同浓度金属纳米颗粒的水溶液的介电常数。在研究纳米流体通道对水中银、铍和铜纳米粒子的检测能力时，使用有限差分时域法进行了系统模拟。明显的颜色偏移表明，纳米流体通道在金属纳米颗粒检测方面具有很高的灵敏度。然后，利用电子束光刻（EBL）技术，在预先复制的氢硅烷基二氧杂环丁烷（HSQ）光栅上直接淹没沉积二氧化硅薄膜，从而制造出设计的纳米流体通道。自密封技术具有简化加工、无封装和多层纳米通道潜力等优点。

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