This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm2.
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