Pub Date : 2025-10-06DOI: 10.1016/j.mee.2025.112422
R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria
In this work, dielectric breakdown (BD) and post-BD conduction in ultimate FDSOI nanowire (NW) transistors with Ω-gate and high-k dielectric have been investigated. The experiments show that BD in largely scaled NW transistors differ significantly from that in bulk planar transistors. Several types of post-BD behaviours have been observed, some of which not only hinder the device performance, but also jeopardize the integrity of the nanowire structure and materials. A comprehensive study of the phenomena has been performed on pMOS and nMOS with different widths and lengths, under different temperature conditions.
{"title":"A statistical characterization of dielectric breakdown in FDSOI nanowire transistors","authors":"R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria","doi":"10.1016/j.mee.2025.112422","DOIUrl":"10.1016/j.mee.2025.112422","url":null,"abstract":"<div><div>In this work, dielectric breakdown (BD) and post-BD conduction in ultimate FDSOI nanowire (NW) transistors with Ω-gate and high-k dielectric have been investigated. The experiments show that BD in largely scaled NW transistors differ significantly from that in bulk planar transistors. Several types of post-BD behaviours have been observed, some of which not only hinder the device performance, but also jeopardize the integrity of the nanowire structure and materials. A comprehensive study of the phenomena has been performed on pMOS and nMOS with different widths and lengths, under different temperature conditions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112422"},"PeriodicalIF":3.1,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145321082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-27DOI: 10.1016/j.mee.2025.112419
Xin Wang , Haoyan Liu , Longyu Sun , Jiayi Zhang , Xiaofeng Jia , Xiaotong Mao , Huaizhi Luo , Fei Zhao , Yongliang Li
In this work, a novel H-shaped pFET (pHFET) is proposed to address the n/p driven current mismatch in the complementary field effect transistor (CFET) architecture. It is realized through secondary fin patterning and selective lateral epitaxy, forming dual (110) dominant oriented fins to enlarge effective channel area (Aeff) and enhance hole mobility. The performance of H-shaped FETs (HFETs) for both nFET and pFET is evaluated through TCAD simulations. Detailed comparison with conventional NSFETs confirms the application potential of pHFETs. Following the principles of design-technology co-optimization (DTCO), key structural parameters, including Hfin and Tfin, are optimized to enhance device performance. Under the optimized dimensions, the proposed pHFET achieves a 24 % ION improvement and 6.2 % reduction in intrinsic delay over conventional NSFETs. Circuit-level implementations in RO, Inverter, and 6 T-SRAM confirm its superior performance, especially for high-speed applications. Additionally, the ladder-FETs, which formed by stacking HFET, are also presented and discussed to extend the scalability and practical applicability of HFETs.
{"title":"A novel H-shaped FET for enhanced CFET performance at advanced technology node","authors":"Xin Wang , Haoyan Liu , Longyu Sun , Jiayi Zhang , Xiaofeng Jia , Xiaotong Mao , Huaizhi Luo , Fei Zhao , Yongliang Li","doi":"10.1016/j.mee.2025.112419","DOIUrl":"10.1016/j.mee.2025.112419","url":null,"abstract":"<div><div>In this work, a novel H-shaped pFET (pHFET) is proposed to address the n/p driven current mismatch in the complementary field effect transistor (CFET) architecture. It is realized through secondary fin patterning and selective lateral epitaxy, forming dual (110) dominant oriented fins to enlarge effective channel area (A<sub>eff</sub>) and enhance hole mobility. The performance of H-shaped FETs (HFETs) for both nFET and pFET is evaluated through TCAD simulations. Detailed comparison with conventional NSFETs confirms the application potential of pHFETs. Following the principles of design-technology co-optimization (DTCO), key structural parameters, including H<sub>fin</sub> and T<sub>fin</sub>, are optimized to enhance device performance. Under the optimized dimensions, the proposed pHFET achieves a 24 % I<sub>ON</sub> improvement and 6.2 % reduction in intrinsic delay over conventional NSFETs. Circuit-level implementations in RO, Inverter, and 6 T-SRAM confirm its superior performance, especially for high-speed applications. Additionally, the ladder-FETs, which formed by stacking HFET, are also presented and discussed to extend the scalability and practical applicability of HFETs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112419"},"PeriodicalIF":3.1,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145155588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Development of ultra-compact, low-to-medium precision analog-to-digital converters (ADCs) with unprecedented energy-efficiency is essential to meet the ever-increasing demand for data converters in advanced computing systems including neuromorphic accelerators based on emerging non-volatile memories. To this end, in this work, for the first time, we propose a feedforward neural network ADC based on a network of highly scalable, CMOS-compatible, and energy efficient ferroelectric-FinFET (Fe-FinFET) synaptic elements. Our lower triangular neural network (LTNN) ADC design, implemented using 7-nm technology along with an experimentally calibrated compact model for Fe-FinFETs, consumes of power, 2.66 of area while operating at a speed of 1.23 megasamples per second for 4-bit precision. The proposed neural network ADC may pave the way for realization of highly efficient neuromorphic processing engines and neuro-optimizers based on cross-point array of emerging non-volatile memories.
{"title":"Ultra-compact neural network ADC exploiting ferroelectric FETs","authors":"Ayan Banerjee , Sagnik Bhattacharya , Arka Chakraborty, Yogesh Singh Chauhan, Shubham Sahay","doi":"10.1016/j.mee.2025.112404","DOIUrl":"10.1016/j.mee.2025.112404","url":null,"abstract":"<div><div>Development of ultra-compact, low-to-medium precision analog-to-digital converters (ADCs) with unprecedented energy-efficiency is essential to meet the ever-increasing demand for data converters in advanced computing systems including neuromorphic accelerators based on emerging non-volatile memories. To this end, in this work, for the first time, we propose a feedforward neural network ADC based on a network of highly scalable, CMOS-compatible, and energy efficient ferroelectric-FinFET (Fe-FinFET) synaptic elements. Our lower triangular neural network (LTNN) ADC design, implemented using 7-nm technology along with an experimentally calibrated compact model for Fe-FinFETs, consumes <span><math><mrow><mn>5</mn><mo>.</mo><mn>44</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span> of power, 2.66 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> of area while operating at a speed of 1.23 megasamples per second for 4-bit precision. The proposed neural network ADC may pave the way for realization of highly efficient neuromorphic processing engines and neuro-optimizers based on cross-point array of emerging non-volatile memories.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112404"},"PeriodicalIF":3.1,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145155590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1016/j.mee.2025.112405
R. O’Meara , V. Dhyani , B.R. Tak , A. McClelland , G. Dawson , C. Storey , A.P.G. Robinson , B. Holst , R.G. Hobbs
Helium-ion-beam lithography has many advantages relevant to the fabrication of dense arrays of nanostructures such as a small probe size, large depth of field, and reduced proximity effect. Here, we calculate and measure the lithographic point-spread functions (PSFs) of 30 keV He ions in negative-tone polymethyl methacrylate (PMMA) and a fullerene-derivative resist on ultrathin silicon nitride membranes and compare the results to similar work by Manfrinato et al. (2017) measuring the PSF of 200 keV electrons in PMMA using an aberration-corrected scanning transmission electron microscope (STEM). PSFs were calculated using the method reported previously by Winston et al. (2012). Our results show that both the He ion/PMMA and He ion/fullerene-derivative resist PSFs decay more rapidly with distance, r, from the point of incidence of the beam than the corresponding aberration-corrected electron beam/PMMA PSF. In fact, the He ion PSFs decay approximately with r−4 while the aberration-corrected EBL PSF decays approximately with r−2. This result implies that the lateral area exposed by the focused beam increases more rapidly with dose for e beams than He beams. Effectively, this should result in reduced proximity effect in helium-ion-beam lithography. This work provides further evidence that HIBL offers distinct advantages over EBL for high-resolution and high-density patterning as well as highlighting some benefits of the fullerene-derivative resist over PMMA.
{"title":"Measurement of the lithographic point-spread function of a focused helium ion beam in negative-tone PMMA and fullerene resists on ultrathin membranes","authors":"R. O’Meara , V. Dhyani , B.R. Tak , A. McClelland , G. Dawson , C. Storey , A.P.G. Robinson , B. Holst , R.G. Hobbs","doi":"10.1016/j.mee.2025.112405","DOIUrl":"10.1016/j.mee.2025.112405","url":null,"abstract":"<div><div>Helium-ion-beam lithography has many advantages relevant to the fabrication of dense arrays of nanostructures such as a small probe size, large depth of field, and reduced proximity effect. Here, we calculate and measure the lithographic point-spread functions (PSFs) of 30 keV He<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> ions in negative-tone polymethyl methacrylate (PMMA) and a fullerene-derivative resist on ultrathin silicon nitride membranes and compare the results to similar work by Manfrinato et al. (2017) measuring the PSF of 200 keV electrons in PMMA using an aberration-corrected scanning transmission electron microscope (STEM). PSFs were calculated using the method reported previously by Winston et al. (2012). Our results show that both the He<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> ion/PMMA and He<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> ion/fullerene-derivative resist PSFs decay more rapidly with distance, <em>r</em>, from the point of incidence of the beam than the corresponding aberration-corrected electron beam/PMMA PSF. In fact, the He<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> ion PSFs decay approximately with <em>r</em><sup>−4</sup> while the aberration-corrected EBL PSF decays approximately with <em>r</em><sup>−2</sup>. This result implies that the lateral area exposed by the focused beam increases more rapidly with dose for e<span><math><msup><mrow></mrow><mrow><mo>−</mo></mrow></msup></math></span> beams than He<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> beams. Effectively, this should result in reduced proximity effect in helium-ion-beam lithography. This work provides further evidence that HIBL offers distinct advantages over EBL for high-resolution and high-density patterning as well as highlighting some benefits of the fullerene-derivative resist over PMMA.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112405"},"PeriodicalIF":3.1,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1016/j.mee.2025.112418
R. Shankari , G. Supraja , V.S. Krushnasamy , D. Haripriya , K. Elangovan
The rapid advancement of power electronics demands revolutionary semiconductor technologies that transcend the fundamental limitations of silicon-based devices. Vertical gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) have emerged as transformative solutions, leveraging the exceptional material properties of GaN through innovative three-dimensional device architectures that enable unprecedented performance scaling. This comprehensive review examines the current state and future prospects of vertical GaN MOSFET technology, encompassing fundamental device physics, advanced architectural innovations, fabrication methodologies, and commercial implementation pathways. The unique advantages of vertical current conduction in GaN devices address critical limitations of conventional lateral architectures, including non-uniform electric field distributions, surface sensitivity, and voltage-current trade-off constraints. Recent technological breakthroughs have demonstrated remarkable achievements: breakdown voltages exceeding 1400 V, specific on-resistance values below 1.4 mΩ·cm2, current densities surpassing 200 A/cm2, and channel mobilities approaching 250 cm2/V·s. These performance metrics establish vertical GaN MOSFETs as competitive alternatives to silicon carbide devices while offering superior switching characteristics and system integration capabilities. This review systematically analyzes diverse device architectures, from conventional trench-gate structures to advanced three-dimensional concepts including FinFET-inspired designs, nanowire arrays, and dual-channel configurations. Manufacturing approaches spanning epitaxial regrowth techniques, all-ion implantation processes, and hybrid fabrication methodologies are evaluated for their impact on device performance and commercial viability. Critical challenges including substrate technology limitations, process integration complexity, reliability concerns, and cost optimization are comprehensively examined alongside emerging solutions and breakthrough innovations.
{"title":"Vertical gallium nitride MOSFETs: Advanced architectures, fabrication technologies, and performance breakthroughs for high-power applications","authors":"R. Shankari , G. Supraja , V.S. Krushnasamy , D. Haripriya , K. Elangovan","doi":"10.1016/j.mee.2025.112418","DOIUrl":"10.1016/j.mee.2025.112418","url":null,"abstract":"<div><div>The rapid advancement of power electronics demands revolutionary semiconductor technologies that transcend the fundamental limitations of silicon-based devices. Vertical gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) have emerged as transformative solutions, leveraging the exceptional material properties of GaN through innovative three-dimensional device architectures that enable unprecedented performance scaling. This comprehensive review examines the current state and future prospects of vertical GaN MOSFET technology, encompassing fundamental device physics, advanced architectural innovations, fabrication methodologies, and commercial implementation pathways. The unique advantages of vertical current conduction in GaN devices address critical limitations of conventional lateral architectures, including non-uniform electric field distributions, surface sensitivity, and voltage-current trade-off constraints. Recent technological breakthroughs have demonstrated remarkable achievements: breakdown voltages exceeding 1400 V, specific on-resistance values below 1.4 mΩ·cm<sup>2</sup>, current densities surpassing 200 A/cm<sup>2</sup>, and channel mobilities approaching 250 cm<sup>2</sup>/V·s. These performance metrics establish vertical GaN MOSFETs as competitive alternatives to silicon carbide devices while offering superior switching characteristics and system integration capabilities. This review systematically analyzes diverse device architectures, from conventional trench-gate structures to advanced three-dimensional concepts including FinFET-inspired designs, nanowire arrays, and dual-channel configurations. Manufacturing approaches spanning epitaxial regrowth techniques, all-ion implantation processes, and hybrid fabrication methodologies are evaluated for their impact on device performance and commercial viability. Critical challenges including substrate technology limitations, process integration complexity, reliability concerns, and cost optimization are comprehensively examined alongside emerging solutions and breakthrough innovations.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112418"},"PeriodicalIF":3.1,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145155589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1016/j.mee.2025.112407
N. Baghban-Bousari , D. Eric , G. Palau , A. Crespo-Yepes , M. Porti , E. Ramon , S. Ogier , M. Nafria
Pre-stressed commercial Organic Thin Film Transistors (OTFT) have been characterized to evaluate their suitability for Physical Unclonable Functions (PUFs) implementation, when the variability of the drain current (ID) is used as entropy source. Different kinds of electrical pre-stresses have been considered, to study their impact on the PUF reproducibility. Uniqueness and Uniformity of the resulting PUFs have also been evaluated. The proposed pre-stressed OTFTs based PUFs show a reproducibility up to 0.99, with a uniformity and uniqueness of 0.52 and 0.50, respectively.
{"title":"Feasibility of Physical Unclonable Functions from Pre-stressed Organic Thin Film Transistors for Secure Microelectronics","authors":"N. Baghban-Bousari , D. Eric , G. Palau , A. Crespo-Yepes , M. Porti , E. Ramon , S. Ogier , M. Nafria","doi":"10.1016/j.mee.2025.112407","DOIUrl":"10.1016/j.mee.2025.112407","url":null,"abstract":"<div><div>Pre-stressed commercial Organic Thin Film Transistors (OTFT) have been characterized to evaluate their suitability for Physical Unclonable Functions (PUFs) implementation, when the variability of the drain current (I<sub>D</sub>) is used as entropy source. Different kinds of electrical pre-stresses have been considered, to study their impact on the PUF reproducibility. Uniqueness and Uniformity of the resulting PUFs have also been evaluated. The proposed pre-stressed OTFTs based PUFs show a reproducibility up to 0.99, with a uniformity and uniqueness of 0.52 and 0.50, respectively.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112407"},"PeriodicalIF":3.1,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1016/j.mee.2025.112408
Hao Sun , Yafeng Zhang , Hao Chen , Xiaoran Hao
The conventional artificial neural network is not suitable for the development trend of edge artificial intelligence due to its high computational energy requirements. In this study, we propose an energy-efficient system using spiking neural networks based on a memristor crossbar. A novel window function is introduced, which overcomes the shortcomings of conventional window functions. Additionally, a dynamic learning rate matrix approach is suggested to decrease the influence of conductance drift and conductance noise on neural networks, efficiently eliminate noise, and adjust the learning rate for each individual synapse. We evaluate the performance of the proposed method using an energy consumption evaluation model. Experimental results show that the proposed window function outperforms state-of-the-art window functions in terms of accuracy and test time. Furthermore, the dynamic learning rate matrix algorithm achieves 97.27% accuracy on the MNIST dataset. Memristor-based spiking neural networks have a significant energy consumption advantage over conventional artificial neural networks, making this approach suitable for resource-constrained edge artificial intelligence devices.
{"title":"Energy-efficient memristor-based spiking neural network for edge devices with a novel window function","authors":"Hao Sun , Yafeng Zhang , Hao Chen , Xiaoran Hao","doi":"10.1016/j.mee.2025.112408","DOIUrl":"10.1016/j.mee.2025.112408","url":null,"abstract":"<div><div>The conventional artificial neural network is not suitable for the development trend of edge artificial intelligence due to its high computational energy requirements. In this study, we propose an energy-efficient system using spiking neural networks based on a memristor crossbar. A novel window function is introduced, which overcomes the shortcomings of conventional window functions. Additionally, a dynamic learning rate matrix approach is suggested to decrease the influence of conductance drift and conductance noise on neural networks, efficiently eliminate noise, and adjust the learning rate for each individual synapse. We evaluate the performance of the proposed method using an energy consumption evaluation model. Experimental results show that the proposed window function outperforms state-of-the-art window functions in terms of accuracy and test time. Furthermore, the dynamic learning rate matrix algorithm achieves 97.27% accuracy on the MNIST dataset. Memristor-based spiking neural networks have a significant energy consumption advantage over conventional artificial neural networks, making this approach suitable for resource-constrained edge artificial intelligence devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112408"},"PeriodicalIF":3.1,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-11DOI: 10.1016/j.mee.2025.112417
Han Jiang , Yang Wang , Ziyu Liu , Yabin Sun , Qingqing Sun , David Wei Zhang
Nano-scale through‑silicon vias (n-TSVs) plays the key role in connecting the active front-side of devices and the backside power delivery network (BS-PDN) in the three-dimensional integrated circuit (3D IC). High-quality Cu filling is the most important in the n-TSVs fabrication. As the diameter decreases and the aspect ratio (AR) increases, the challenges associated with seed layer deposition, surface pre-wetting, and electrochemical deposition (ECD) will intensify. In this study, the electron beam induced deposition (EBID) method has been first proposed to deposit the seed layer for high-AR n-TSVs. Additionally, isopropanol pre-wetting is proposed to enhance surface wettability, thereby eliminating air bubbles within the via and ensuring complete filling of the electrolyte. Finally, the effect of electrolyte additives and current density on the ECD process have also been extensively investigated. The thickness of seed layer deposited by EBID exhibits high step coverage, uniformity and continuity at the top and the bottom of via. Meanwhile, the wettability of seed layer surface treated by isopropanol has been greatly increased. During the ECD process, the deposition rate of Cu is main affected by the suppressor. Besides, the current density should be chosen within a moderate value (≥ 0.03 A/dm2 and ≤ 0.3 A/dm2), which can increase the deposition rate and avoid the premature closing of the via opening. With the optimized processes above, the n-TSVs of Type-I (440-nm-diameter and 4.81:1-AR) and Type-II (150-nm-diameter and 9.25:1-AR) have been conformally filled without voids and breaks.
在三维集成电路（3D IC）中，纳米级硅通孔（n- tsv）在连接器件的有源前端和背面电力输送网络（BS-PDN）方面起着关键作用。高质量的Cu填充是n- tsv制备中最重要的环节。随着直径的减小和宽高比（AR）的增加，与种子层沉积、表面预润湿和电化学沉积（ECD）相关的挑战将会加剧。在本研究中，首次提出了电子束诱导沉积（EBID）方法沉积高ar n- tsv的种子层。此外，异丙醇预湿可以提高表面润湿性，从而消除通孔内的气泡，确保电解质完全填充。最后，电解质添加剂和电流密度对ECD过程的影响也得到了广泛的研究。EBID沉积的种子层厚度具有较高的台阶覆盖度、均匀性和孔道顶部和底部的连续性。同时，异丙醇处理后种子层表面的润湿性大大提高。在ECD过程中，铜的沉积速率主要受抑制因子的影响。电流密度应选择在一个适中的范围内（≥0.03 a /dm2和≤0.3 a /dm2），这样可以提高沉积速率，避免过孔过早闭合。通过上述优化工艺，i型（440-nm直径，4.81:1-AR）和ii型（150-nm直径，9.25:1-AR）的n- tsv均得到了保形填充，无空洞和断裂。
{"title":"A novel cu filling method for high-aspect-ratio (AR) nano-scale TSVs","authors":"Han Jiang , Yang Wang , Ziyu Liu , Yabin Sun , Qingqing Sun , David Wei Zhang","doi":"10.1016/j.mee.2025.112417","DOIUrl":"10.1016/j.mee.2025.112417","url":null,"abstract":"<div><div>Nano-scale through‑silicon vias (n-TSVs) plays the key role in connecting the active front-side of devices and the backside power delivery network (BS-PDN) in the three-dimensional integrated circuit (3D IC). High-quality Cu filling is the most important in the n-TSVs fabrication. As the diameter decreases and the aspect ratio (AR) increases, the challenges associated with seed layer deposition, surface pre-wetting, and electrochemical deposition (ECD) will intensify. In this study, the electron beam induced deposition (EBID) method has been first proposed to deposit the seed layer for high-AR n-TSVs. Additionally, isopropanol pre-wetting is proposed to enhance surface wettability, thereby eliminating air bubbles within the via and ensuring complete filling of the electrolyte. Finally, the effect of electrolyte additives and current density on the ECD process have also been extensively investigated. The thickness of seed layer deposited by EBID exhibits high step coverage, uniformity and continuity at the top and the bottom of via. Meanwhile, the wettability of seed layer surface treated by isopropanol has been greatly increased. During the ECD process, the deposition rate of Cu is main affected by the suppressor. Besides, the current density should be chosen within a moderate value (≥ 0.03 A/dm<sup>2</sup> and ≤ 0.3 A/dm<sup>2</sup>), which can increase the deposition rate and avoid the premature closing of the via opening. With the optimized processes above, the n-TSVs of Type-I (440-nm-diameter and 4.81:1-AR) and Type-II (150-nm-diameter and 9.25:1-AR) have been conformally filled without voids and breaks.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112417"},"PeriodicalIF":3.1,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-09DOI: 10.1016/j.mee.2025.112403
Jinbao Su , Yaobin Ma , Yihong Liu , Yiyang Xie
Oxide thin film transistors (TFTs) have been one of the promising transistors in high-resolution displays. Unfortunately, their electrical performance, especially mobility, is limited by oxygen related defects in the active layers. Here, a homojunction dual-active-layer architecture using sputtering oxygen strategy is employed to enhance the electrical performance of InSnZnO (ITZO) TFTs. The ITZO dual active layers with varying oxygen contents are sequentially sputtered by adjusting the oxygen gas flow rate. The oxygen effects on the electrical performance of the ITZO TFTs are investigated. As the oxygen content increases, the mobility decreases while the threshold voltage increases. The dual-active-layer architecture, composed of ITZO films with varying oxygen contents, significantly improves the mobility. The dual-layer ITZO TFT shows excellent performance with a mobility of 50.51 ± 4.16 cm2/V·s, a subthreshold swing of 0.59 ± 0.19 V/dec, a threshold voltage of −0.77 ± 1.40 V, an off-state current of ∼10−12 A, and an on/off-state current ratio of more than 108. The gate bias stress stability of the ITZO TFTs is investigated. Under negative bias stress, the threshold voltage shift in single-layer TFTs improves from −14 to −8 V as the oxygen flow rate increases from 1 to 7 SCCM. The dual-layer TFTs show a reasonable threshold voltage shift under bias stress. This work demonstrates that the ITZO TFTs exhibit great potential for next-generation electronic applications.
{"title":"Performance enhancement of InSnZnO thin-film transistors by dual-active-layer architecture with various oxygen flow rates","authors":"Jinbao Su , Yaobin Ma , Yihong Liu , Yiyang Xie","doi":"10.1016/j.mee.2025.112403","DOIUrl":"10.1016/j.mee.2025.112403","url":null,"abstract":"<div><div>Oxide thin film transistors (TFTs) have been one of the promising transistors in high-resolution displays. Unfortunately, their electrical performance, especially mobility, is limited by oxygen related defects in the active layers. Here, a homojunction dual-active-layer architecture using sputtering oxygen strategy is employed to enhance the electrical performance of InSnZnO (ITZO) TFTs. The ITZO dual active layers with varying oxygen contents are sequentially sputtered by adjusting the oxygen gas flow rate. The oxygen effects on the electrical performance of the ITZO TFTs are investigated. As the oxygen content increases, the mobility decreases while the threshold voltage increases. The dual-active-layer architecture, composed of ITZO films with varying oxygen contents, significantly improves the mobility. The dual-layer ITZO TFT shows excellent performance with a mobility of 50.51 ± 4.16 cm<sup>2</sup>/V·s, a subthreshold swing of 0.59 ± 0.19 V/dec, a threshold voltage of −0.77 ± 1.40 V, an off-state current of ∼10<sup>−12</sup> A, and an on/off-state current ratio of more than 10<sup>8</sup>. The gate bias stress stability of the ITZO TFTs is investigated. Under negative bias stress, the threshold voltage shift in single-layer TFTs improves from −14 to −8 V as the oxygen flow rate increases from 1 to 7 SCCM. The dual-layer TFTs show a reasonable threshold voltage shift under bias stress. This work demonstrates that the ITZO TFTs exhibit great potential for next-generation electronic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112403"},"PeriodicalIF":3.1,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-05DOI: 10.1016/j.mee.2025.112401
Phi Cuong Ly , Ngoc Thuy Thi Nguyen , Tongil Park , Hana Choi , Doyeon Bang , Jong-Oh Park , Byungjeon Kang , Kim Tien Nguyen , Jayoung Kim
{"title":"Corrigendum to “Frequency-selective and high-performance wireless power transmission system for a multifunctional capsule endoscope: A feasibility study” [Microelectronic Engineering 301 (2026) 112387]","authors":"Phi Cuong Ly , Ngoc Thuy Thi Nguyen , Tongil Park , Hana Choi , Doyeon Bang , Jong-Oh Park , Byungjeon Kang , Kim Tien Nguyen , Jayoung Kim","doi":"10.1016/j.mee.2025.112401","DOIUrl":"10.1016/j.mee.2025.112401","url":null,"abstract":"","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112401"},"PeriodicalIF":3.1,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144996764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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