Microelectronic Engineering最新文献

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IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-01-01

引用次数: 0

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-01-01

引用次数: 0

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-01-01

引用次数: 0

Design and characterization of 2-GaN MIS-HEMT integrated cascode power module 2-GaN miss - hemt集成级联码功率模块的设计与表征

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-12-31 DOI: 10.1016/j.mee.2025.112439

Surya Elangovan , Stone Cheng , Edward Yi Chang , Tejender Singh Rawat , Yi-Kai Hsiao , Chang-Ching Tu , Hao-Chung Kuo

A cascode gallium nitride (GaN) switch integrating two paralleled GaN depletion-mode metal-insulator-semiconductor (MIS) high-electron-mobility transistors (HEMT) and a silicon MOSFET (Si-MOSFET) are presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the novel cascode switch. The developed GaN cascode switch was verified for validity through both static and dynamic characterizations in an optimized package. Static characterization reveals a significant reduction in RDS-ON from 282 mΩ (single MIS-HEMT) to 146 mΩ (dual-GaN cascode) with a threshold voltage shift to 4.2 V, confirming safe and reliable enhancement-mode operation. Dynamic switching performance, evaluated using double-pulse testing, demonstrates that the dual-GaN configuration maintains fast turn-on/off times with minimal increase relative to a single-GaN cascode. Voltage- and current-dependent measurements indicate a moderate increase in dynamic RDS-ON due to charge trapping and hot carrier injection, which stabilizes at higher voltages. These results highlight the feasibility of paralleling GaN HEMTs in a cascode configuration to enhance performance, reliability, and scalability in high-power applications.

提出了一种将两个并联的氮化镓耗尽型金属绝缘体半导体（MIS）高电子迁移率晶体管（HEMT）和硅MOSFET （Si-MOSFET）集成在一起的级联式氮化镓开关。每个GaN芯片通过导线连接成一个多芯片电源模块，以扩大额定功率。新型级联开关采用了优化的对称结构和整体封装的线键合。通过优化封装的静态和动态特性验证了所开发的GaN级联码开关的有效性。静态特性显示，RDS-ON从282 mΩ（单miss - hemt）显著降低到146 mΩ（双gan级联码），阈值电压移至4.2 V，证实了安全可靠的增强模式操作。使用双脉冲测试评估的动态开关性能表明，相对于单gan级联码，双gan配置保持了快速的开/关时间，且增加最小。电压和电流相关的测量表明，由于电荷捕获和热载流子注入，动态RDS-ON适度增加，在更高的电压下稳定。这些结果强调了在级联码配置中并行GaN hemt的可行性，以提高高功率应用中的性能、可靠性和可扩展性。

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引用次数: 0

Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs 热致裂纹对tgv力学和电学性能的影响

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-12-30 DOI: 10.1016/j.mee.2025.112441

Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas

Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.

由于其低电损耗、尺寸稳定性和面板级可制造性，玻璃通孔（tgv）在2.5D/3D封装中越来越重要。然而，在温度变化过程中，铜（Cu）和玻璃之间的热膨胀系数（CTE）的大不匹配会引起显著的热机械应力，导致裂纹萌生、能量释放和电降解。本文建立了有限元法和断裂力学框架相结合的方法来分析充铜tgv的可靠性。该研究评估了在孔内和铜玻璃界面的不同位置存在裂纹时的应力分布、变形和电流密度。利用能量释放率（ERR）对裂缝驱动力进行量化，并根据基于有限元的j积分计算验证了分析公式。结果表明，ERR与通孔直径成线性关系，与温度变化幅度成二次关系，裂纹长度约为通孔直径的1 / 4时出现峰值；衬底材料强烈影响可靠性，熔融石英产生最高的应力和ERR，而陶瓷玻璃提供更好的可靠性。聚合物缓冲层的引入显著降低了TGV中的应力，证明了它们在减轻错配引起的故障方面的有效性。总之，结合FEM-ERR框架为连接应力、断裂和电气退化提供了统一的基础，并为优化基于tgv的中介器提供了实用的设计指南。

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引用次数: 0

Resistive switching characteristics of ZnO/HfO2 RRAM using TiN/Ti electrode with a graphene interlayer 石墨烯中间层TiN/Ti电极制备ZnO/HfO2 RRAM的电阻开关特性

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-12-30 DOI: 10.1016/j.mee.2025.112443

So-Yeon Kwon, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Do-Yeon Lee, Hi-Deok Lee, Ga-Won Lee

In this study, the structure with a graphene interlayer in a ZnO/HfO₂ bilayer Resistive Random-Access Memory (RRAM) is proposed. Two types of devices were fabricated to compare the effect of graphene interlayer: one with a TiN/Ti/graphene Top Electrode (TE) device and another with a TiN/Ti TE device. The condition of the single-layer graphene was confirmed using Raman spectroscopy. The TiN/Ti/graphene TE device demonstrates an enhanced uniformity of both the set voltage (V_set) and reset voltage (V_reset). The window for the switching voltage decreases by 2.1 V, and the average on/off ratio increases by 20.09 times. The structure also exhibits self-compliance characteristics. These results highlight both the advantages of the graphene interlayer and the oxygen-scavenging properties of TiN/Ti TE. Detailed mechanisms of oxygen ion blocking by graphene interlayer are analyzed using the standard Gibbs free energy of formation (∆G_f°). The switching characteristics are analyzed by the structure's work function. And the conduction mechanism is analyzed by the space-charge limited current (SCLC), related to traps.

在这项研究中，提出了一种具有石墨烯中间层的ZnO/HfO2双层电阻随机存取存储器（RRAM）结构。我们制作了两种类型的器件来比较石墨烯中间层的效果：一种是TiN/Ti/石墨烯顶部电极（TE）器件，另一种是TiN/Ti TE器件。用拉曼光谱法证实了单层石墨烯的形成条件。TiN/Ti/石墨烯TE器件显示了设置电压（Vset）和复位电压（Vreset）的增强均匀性。开关电压窗口减小2.1 V，平均开/关比增加20.09倍。该结构还具有自顺应特性。这些结果突出了石墨烯中间层的优点和TiN/Ti TE的扫氧性能。利用标准吉布斯生成自由能（∆Gf°）分析了石墨烯中间层阻挡氧离子的详细机理。根据结构的功函数分析了开关特性。并利用与陷阱有关的空间电荷限制电流（SCLC）分析了导电机理。

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引用次数: 0

Comprehensive statistical analysis of random telegraph noise: Impact of gate voltage, temperature, and Bias time 随机电报噪声的综合统计分析：栅极电压、温度和偏置时间的影响

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-12-13 DOI: 10.1016/j.mee.2025.112437

J. Martin-Martinez , N. Baghban-Bousari , R. Castro-Lopez , D. Eric , E. Roca , R. Rodriguez , M. Porti , F.V. Fernandez , M. Nafria

This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number of detectable traps and the associated current step amplitudes. Results show that the average number of detectable traps increases with voltage and temperature but decreases after some bias time due to a transient trap population. The average current step amplitude grows with voltage and shows negligible dependence on temperature. These findings support improved RTN modeling and are relevant for both reliability analysis and cryptographic applications.

这项工作提出了纳米级mosfet中随机电报噪声（RTN）的统计分析，来自基于阵列的表征芯片上在不同电压，温度和偏置时间下测量的13,000多条走线。利用加权时滞图（WTLP），我们提取了可探测陷阱的平均数量和相关的电流阶跃幅值。结果表明，可探测陷阱的平均数量随着电压和温度的增加而增加，但由于瞬态陷阱数量在一定偏置时间后减少。平均电流阶跃幅值随电压增长，对温度的依赖性可以忽略不计。这些发现支持改进的RTN建模，并且与可靠性分析和密码学应用相关。

引用次数: 0

Evaluation of the robustness of the defect-centric model for defect parameter extraction from RTN and BTI analysis using Comphy 缺陷中心模型在RTN和BTI分析中缺陷参数提取的鲁棒性评价

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-12-05 DOI: 10.1016/j.mee.2025.112436

Martin E.M. Loesener , Tobias Zinsler , Bernhard Stampfer , Florian Wimmer , Eleftherios Ioannidis , Walter Pflanzl , Rainer Minixhofer , Tibor Grasser , Michael Waltl

Advanced reliability simulators like Comphy capture much of the state-of-the-art modeling behind charge trapping processes. An alternative approach to Comphy is to apply stochastic models, e.g. the defect-centric model, directly to the experimental data to extract the impact of defects on the device behavior and trap densities. In order to efficiently design defect characterization experiments, however, it is of utmost importance to understand the robustness of the defect-centric model under a variety of pre-conditions. In this work, we evaluate the requirements to employ the defect-centric model for data analysis, using simulated data from Comphy based on a real 400 nm × 180 nm pMOS device. Our results show that the number of devices from wafer-level tests does not suffice for statistical evaluation of RTN analysis. Here, preferably array chips should be used. For BTI studies, both wafer-level and array-chip tests enable us to extract good estimates for defect parameters with little computational effort.

像Comphy这样的高级可靠性模拟器可以捕获电荷捕获过程背后的许多最先进的模型。Comphy的另一种方法是将随机模型（例如以缺陷为中心的模型）直接应用于实验数据，以提取缺陷对器件行为和陷阱密度的影响。然而，为了有效地设计缺陷表征实验，了解以缺陷为中心的模型在各种前提条件下的鲁棒性至关重要。在这项工作中，我们评估了采用以缺陷为中心的模型进行数据分析的需求，使用了基于真实400 nm × 180 nm pMOS器件的Comphy模拟数据。我们的研究结果表明，晶圆级测试的器件数量不足以对RTN分析进行统计评估。在这里，最好使用阵列芯片。对于BTI研究，晶圆级和阵列芯片测试都使我们能够以很少的计算量提取出良好的缺陷参数估计。

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引用次数: 0

A DC − 24 GHz SPDT switch design in 22 nm FD-SOI CMOS for 5G FR1 and FR3 bands 基于22 nm FD-SOI CMOS的5G FR1和FR3频段DC - 24 GHz SPDT开关设计

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-11-29 DOI: 10.1016/j.mee.2025.112428

F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez

A fully-monolithic DC - 24 GHz SPDT (single-pole-double-throw) RF (radio-frequency) switch IC (integrated circuit) is designed and taped out in a 22 nm FD-SOI (fully-depleted silicon-on-insulator) CMOS process, targeting 5G FR1 and FR3 band applications. The first-generation switch (SW1) has measured insertion loss of about 1.9/2.8/3.8 dB at 10/18/24 GHz, reasonably close to the simulation data within 0.5 dB, and measured receive-antenna (RX-ANT) isolation of around 28.2/23.2/20.7 dB at 10/18/24 GHz. However, we found both the post-layout parasitic (PEX) RCC simulations (accounting for resistance, capacitance, and coupling capacitance) and the EM (electromagnetic) simulations underestimated the switch's insertion loss compared with measurement data, especially at frequencies above 30 GHz. To reduce this loss and to design a switch that may operate at the higher frequency FR2 band (i.e., 24.25–52.6 GHz), a second-generation switch (SW2) with improved transistor sizing and a matching network is proposed. PEX-RCC simulations indicate that the SW2 may reduce the insertion loss by up to ∼1 dB at 24 GHz vs. SW1, while maintaining the TX-RX isolation above 30 dB.

针对5G FR1和FR3频段应用，设计了全单片DC - 24 GHz SPDT（单极双掷）RF（射频）开关IC（集成电路），并采用22 nm FD-SOI（完全耗尽绝缘体上硅）CMOS工艺进行封装。第一代交换机（SW1）在10/18/24 GHz时测量到的插入损耗约为1.9/2.8/3.8 dB，与仿真数据在0.5 dB内相当接近，在10/18/24 GHz时测量到的接收天线（RX-ANT）隔离度约为28.2/23.2/20.7 dB。然而，我们发现，与测量数据相比，布局后寄生（PEX） RCC模拟（考虑电阻、电容和耦合电容）和EM（电磁）模拟都低估了开关的插入损耗，特别是在频率高于30 GHz时。为了减少这种损耗并设计一种可以在更高频率FR2频段（即24.25-52.6 GHz）工作的开关，提出了具有改进晶体管尺寸和匹配网络的第二代开关（SW2）。PEX-RCC仿真表明，与SW1相比，SW2在24 GHz时可将插入损耗降低高达1 dB，同时保持TX-RX隔离度在30 dB以上。

{"title":"A DC − 24 GHz SPDT switch design in 22 nm FD-SOI CMOS for 5G FR1 and FR3 bands","authors":"F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez","doi":"10.1016/j.mee.2025.112428","DOIUrl":"10.1016/j.mee.2025.112428","url":null,"abstract":"<div><div>A fully-monolithic DC - 24 GHz SPDT (single-pole-double-throw) RF (radio-frequency) switch IC (integrated circuit) is designed and taped out in a 22 nm FD-SOI (fully-depleted silicon-on-insulator) CMOS process, targeting 5G FR1 and FR3 band applications. The first-generation switch (SW1) has measured insertion loss of about 1.9/2.8/3.8 dB at 10/18/24 GHz, reasonably close to the simulation data within 0.5 dB, and measured receive-antenna (RX-ANT) isolation of around 28.2/23.2/20.7 dB at 10/18/24 GHz. However, we found both the post-layout parasitic (PEX) RCC simulations (accounting for resistance, capacitance, and coupling capacitance) and the EM (electromagnetic) simulations underestimated the switch's insertion loss compared with measurement data, especially at frequencies above 30 GHz. To reduce this loss and to design a switch that may operate at the higher frequency FR2 band (i.e., 24.25–52.6 GHz), a second-generation switch (SW2) with improved transistor sizing and a matching network is proposed. PEX-RCC simulations indicate that the SW2 may reduce the insertion loss by up to ∼1 dB at 24 GHz vs. SW1, while maintaining the TX-RX isolation above 30 dB.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112428"},"PeriodicalIF":3.1,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on evaluation method of data retention capability of STT-MRAM chips STT-MRAM芯片数据保留能力评估方法研究

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2025-11-25 DOI: 10.1016/j.mee.2025.112427

Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye

Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting E_Bmeff and Δ_eff, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of E_Beff on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.

数据保持时间是自旋传递转矩磁随机存储器（STT-MRAM）可靠性的关键参数，它表征了数据保持稳定存储时间的能力。评估数据保留时间的方法经常面临测试时间过长和精度有限的问题。本研究采用高温加速和磁场加速两种方法对STT-MRAM芯片的数据保留能力进行了研究，显著提高了测试效率和准确性。两种加速方法在预测EBmeff和Δeff时具有较高的一致性，在- 25°C时相对偏差仅为10%。此外，观测到的EBeff对磁场的依赖性与从畴壁模型得出的理论预测很好地吻合。实验结果表明，STT-MRAM芯片可以在105°C下实现超过20年的数据保留时间，满足工业级存储器应用所需的严格可靠性标准。这些发现为支持STT-MRAM集成到下一代存储器架构中提供了关键的实验验证和技术见解。

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