Pub Date : 2024-12-20DOI: 10.1016/j.mee.2024.112307
Byeong Hwa Jeong , Dong Woo Kim , Da Hee Park , Shin Kim , Yong Seok Jang , Yasuyuki Taura , Yutaka Kokaze , Sang Ho Lee , Geun Young Yeom
This study aims to demonstrate the deposition of high-performance Cu-seed layers using a very high frequency–direct current (VHF–DC) superimposed magnetron sputtering system for sub-20-nm dual-damascene interconnects. Plasma diagnostics revealed substantial improvements in plasma properties with electron densities measured at ne ≈ 1.71 × 1016 m−3 for direct current magnetron sputtering (DCMS), ne ≈ 3.08 × 1016 m−3 for 40.68 MHz VHF–DC, and ne ≈ 1.63 × 1017 m−3 for 60 MHz VHF–DC. These enhancements enabled superior step coverage and thin-film uniformity, particularly in high-aspect-ratio structures, achieving a bottom-to-top coverage ratio exceeding 100 % at an RF bias of 200 W. Comparative analysis using X-ray diffraction and X-ray photoelectron spectroscopy showed that CuMn films deposited via VHF–DC superimposed sputtering exhibited improved Cu (111) crystallinity, reduced void formation, and enhanced adhesion compared to conventional DCMS. These findings reveal VHF–DC superimposed sputtering as a critical technological advancement, offering enhanced process reliability and scalability for next-generation semiconductor devices.
{"title":"High-performance copper-seed-layer deposition using 60-MHz high-frequency–direct current superimposed magnetron sputtering","authors":"Byeong Hwa Jeong , Dong Woo Kim , Da Hee Park , Shin Kim , Yong Seok Jang , Yasuyuki Taura , Yutaka Kokaze , Sang Ho Lee , Geun Young Yeom","doi":"10.1016/j.mee.2024.112307","DOIUrl":"10.1016/j.mee.2024.112307","url":null,"abstract":"<div><div>This study aims to demonstrate the deposition of high-performance Cu-seed layers using a very high frequency–direct current (VHF–DC) superimposed magnetron sputtering system for sub-20-nm dual-damascene interconnects. Plasma diagnostics revealed substantial improvements in plasma properties with electron densities measured at <em>n</em><sub><em>e</em></sub> ≈ 1.71 × 10<sup>16</sup> <!-->m<sup>−3</sup> for direct current magnetron sputtering (DCMS), <em>n</em><sub><em>e</em></sub> ≈ 3.08 × 10<sup>16</sup> <!-->m<sup>−3</sup> for 40.68 MHz VHF–DC, and <em>n</em><sub><em>e</em></sub> ≈ 1.63 × 10<sup>17</sup> <!-->m<sup>−3</sup> for 60 MHz VHF–DC. These enhancements enabled superior step coverage and thin-film uniformity, particularly in high-aspect-ratio structures, achieving a bottom-to-top coverage ratio exceeding 100 % at an RF bias of 200 W. Comparative analysis using X-ray diffraction and X-ray photoelectron spectroscopy showed that Cu<img>Mn films deposited via VHF–DC superimposed sputtering exhibited improved Cu (111) crystallinity, reduced void formation, and enhanced adhesion compared to conventional DCMS. These findings reveal VHF–DC superimposed sputtering as a critical technological advancement, offering enhanced process reliability and scalability for next-generation semiconductor devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112307"},"PeriodicalIF":2.6,"publicationDate":"2024-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-18DOI: 10.1016/j.mee.2024.112304
Antoine Pacco , Teppei Nakano , Jana Loyo Prado , Ju-Geng Lai , Hikaru Kawarazaki , Efrain Altamirano Sanchez
In this work, an etching process for the controlled and partial recess of tungsten metal was developed. The process comprises two steps which can be repeated: a thermal oxidation of the tungsten followed by the oxide dissolution in an acidic or basic solution. During the first step the W metal is heated in the presence of O3 gas in the temperature range of 210–290 °C forming a WO3 oxide. During the second step this thermally grown oxide is then selectively dissolved towards the underlying W metal. Both NH4OH and H3PO4 were down selected as the best wet chemical dissolution agents in terms of dissolution rate and selectivity. By utilizing this combined thermal/wet-chemical cyclic etch process, the total W recess can be tuned on the nanoscale based on oxidation temperature and total number of cycles. This process was then applied for the deep recess (∼180 nm) of narrow (∼20 nm) tungsten trenches for the fabrication of the bottom contacts in complementary field-effect transistors (CFET).
{"title":"Etching of tungsten via a combination of thermal oxide formation and wet-chemical oxide dissolution","authors":"Antoine Pacco , Teppei Nakano , Jana Loyo Prado , Ju-Geng Lai , Hikaru Kawarazaki , Efrain Altamirano Sanchez","doi":"10.1016/j.mee.2024.112304","DOIUrl":"10.1016/j.mee.2024.112304","url":null,"abstract":"<div><div>In this work, an etching process for the controlled and partial recess of tungsten metal was developed. The process comprises two steps which can be repeated: a thermal oxidation of the tungsten followed by the oxide dissolution in an acidic or basic solution. During the first step the W metal is heated in the presence of O<sub>3</sub> gas in the temperature range of 210–290 °C forming a WO<sub>3</sub> oxide. During the second step this thermally grown oxide is then selectively dissolved towards the underlying W metal. Both NH<sub>4</sub>OH and H<sub>3</sub>PO<sub>4</sub> were down selected as the best wet chemical dissolution agents in terms of dissolution rate and selectivity. By utilizing this combined thermal/wet-chemical cyclic etch process, the total W recess can be tuned on the nanoscale based on oxidation temperature and total number of cycles. This process was then applied for the deep recess (∼180 nm) of narrow (∼20 nm) tungsten trenches for the fabrication of the bottom contacts in complementary field-effect transistors (CFET).</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112304"},"PeriodicalIF":2.6,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1016/j.mee.2024.112305
Muhammad Bilal Yaseen , Fayu Wan , Fareeha Siddique , Atul Thakur
This review article provides a thorough analysis of recent progress in Gallium Nitride radio frequency components and power amplifiers, highlighting their essential contributions to the advancement of fifth-generation communication systems. Over the last two decades, Gallium Nitride High Electron Mobility Transistors have been at the cutting edge of technological development, demonstrating significant advancements and their crucial role in silicon substrate applications for radio frequency power. These advancements underscore the transformative impact and continued importance of Gallium Nitride technologies in enhancing performance and efficiency in modern communication systems. This review evaluates various material structures, device architectures, and fabrication techniques, detailing their impact on enhancing power density and efficiency within 5G systems. Key findings include effective methodologies for mitigating RF leakage from substrates and interfaces, which are vital for sustaining high power density and efficiency. Noteworthy progress in the L-band demonstrates significant improvements in output power and power-added efficiency, highlighting GaN technology's transformative potential in wireless communications. This review integrates critical insights into the current state of GaN RF technology and provides a forward-looking perspective on the challenges and future directions necessary to fully exploit GaN's capabilities for 5G network applications.
{"title":"GaN radiofrequency components and power amplifiers for next-generation 5G communications","authors":"Muhammad Bilal Yaseen , Fayu Wan , Fareeha Siddique , Atul Thakur","doi":"10.1016/j.mee.2024.112305","DOIUrl":"10.1016/j.mee.2024.112305","url":null,"abstract":"<div><div>This review article provides a thorough analysis of recent progress in Gallium Nitride radio frequency components and power amplifiers, highlighting their essential contributions to the advancement of fifth-generation communication systems. Over the last two decades, Gallium Nitride High Electron Mobility Transistors have been at the cutting edge of technological development, demonstrating significant advancements and their crucial role in silicon substrate applications for radio frequency power. These advancements underscore the transformative impact and continued importance of Gallium Nitride technologies in enhancing performance and efficiency in modern communication systems. This review evaluates various material structures, device architectures, and fabrication techniques, detailing their impact on enhancing power density and efficiency within 5G systems. Key findings include effective methodologies for mitigating RF leakage from substrates and interfaces, which are vital for sustaining high power density and efficiency. Noteworthy progress in the L-band demonstrates significant improvements in output power and power-added efficiency, highlighting GaN technology's transformative potential in wireless communications. This review integrates critical insights into the current state of GaN RF technology and provides a forward-looking perspective on the challenges and future directions necessary to fully exploit GaN's capabilities for 5G network applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112305"},"PeriodicalIF":2.6,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143128950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-16DOI: 10.1016/j.mee.2024.112306
Parth S. Thorat , Dhananjay D. Kumbhar , Ruchik D. Oval , Sanjay Kumar , Manik Awale , T.V. Ramanathan , Atul C. Khot , Tae Geun Kim , Tukaram D. Dongale , Santosh S. Sutar
Resistive switching (RS) based memory or memristive devices have emerged as promising candidates for resistive random-access memory (RRAM) and neuromorphic computing applications. However, the integration of RS devices into commercial production faces significant challenges due to substantial variations in RS parameters, which include cycle-to-cycle (C2C) and device-to-device (D2D) fluctuations. In this context, we propose a multivariate time series analysis framework to investigate the variability exhibited by RS devices. We present a detailed description of the statistical methodology and procedures for conducting both univariate and multivariate time series analysis, along with recommended tests and protocols. Specifically, we focus on utilizing Ti3C2 MXene oxide-based RS devices as a case study for this analysis. Our findings reveal that employing the multivariate method yields superior prediction results compared to the univariate approach. This conclusion is based on our observation that the Vector Autoregressive Moving Average (VARMA) model, which concurrently considers multiple variables (VSET and VRESET), more effectively explains a larger portion of the variability in the data compared to the univariate model. This underscores the importance of considering multiple factors simultaneously, as it provides a more comprehensive understanding of the underlying patterns within the dataset, thereby enhancing the accuracy of predictions. Consequently, we advocate for adopting the multivariate approach due to its ability to capture the complexity and interactions inherent in the dataset, resulting in enhanced model performance. The proposed model demonstrated superior performance in capturing the variability present in VSET and VRESET data, thereby producing the most optimal outcomes.
{"title":"On the time series analysis of resistive switching devices","authors":"Parth S. Thorat , Dhananjay D. Kumbhar , Ruchik D. Oval , Sanjay Kumar , Manik Awale , T.V. Ramanathan , Atul C. Khot , Tae Geun Kim , Tukaram D. Dongale , Santosh S. Sutar","doi":"10.1016/j.mee.2024.112306","DOIUrl":"10.1016/j.mee.2024.112306","url":null,"abstract":"<div><div>Resistive switching (RS) based memory or memristive devices have emerged as promising candidates for resistive random-access memory (RRAM) and neuromorphic computing applications. However, the integration of RS devices into commercial production faces significant challenges due to substantial variations in RS parameters, which include cycle-to-cycle (C2C) and device-to-device (D2D) fluctuations. In this context, we propose a multivariate time series analysis framework to investigate the variability exhibited by RS devices. We present a detailed description of the statistical methodology and procedures for conducting both univariate and multivariate time series analysis, along with recommended tests and protocols. Specifically, we focus on utilizing Ti<sub>3</sub>C<sub>2</sub> MXene oxide-based RS devices as a case study for this analysis. Our findings reveal that employing the multivariate method yields superior prediction results compared to the univariate approach. This conclusion is based on our observation that the Vector Autoregressive Moving Average (VARMA) model, which concurrently considers multiple variables (V<sub>SET</sub> and V<sub>RESET</sub>), more effectively explains a larger portion of the variability in the data compared to the univariate model. This underscores the importance of considering multiple factors simultaneously, as it provides a more comprehensive understanding of the underlying patterns within the dataset, thereby enhancing the accuracy of predictions. Consequently, we advocate for adopting the multivariate approach due to its ability to capture the complexity and interactions inherent in the dataset, resulting in enhanced model performance. The proposed model demonstrated superior performance in capturing the variability present in V<sub>SET</sub> and V<sub>RESET</sub> data, thereby producing the most optimal outcomes.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112306"},"PeriodicalIF":2.6,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-29DOI: 10.1016/j.mee.2024.112293
Eun-Su Jang, Jeong-Won Yoon
Flip-chip bonding technology has been extensively applied in the semiconductor packaging field given the recent increase in demand for electronic products requiring miniaturization and high performance. In this study, a high-temperature long-term reliability evaluation was performed to evaluate the metallurgical reaction and mechanical properties at the Sn-2.3Ag (wt%) flip-chip solder bump joints. Isothermal aging was performed for up to 2000 h at 150 °C. A Ni3Sn4 intermetallic compound (IMC) was formed at the interface of the solder joints, and the thickness of the IMC layer increased as the isothermal aging time increased; however, the thickness of Ni under bump metallization (Ni UBM) layer was decreased during the growth of the IMC. Linear regression analysis showed that the growth thickness of the IMC layer and the consumption thickness of the Ni UBM layer varied linearly as functions of the square root of the isothermal aging time. Based on this analysis, the growth rate constant of the IMC layer and consumption rate constant of the Ni UBM layer were 0.000756 and 0.000303 μm/s1/2, respectively. Thereafter, shear tests were performed to evaluate the mechanical properties of the solder joints. As the isothermal aging time increased, the variation of shear strength was not large. However, the shear strength decreased slightly and then remained constant. As a result of the analysis of the fractured surface, most conditions exhibited ductile fracture behavior inside the solder bump, while in the case of specimens isothermally aged for 500, 1000, 1500, and 2000 h, cratering occurred. By observing the changes in the fracture mode, the ductile fracture behavior became less prominent, and the occurrence of cratering tended to become more prominent as the isothermal aging time increased.
近年来，随着电子产品小型化和高性能的需求不断增加，倒装键合技术在半导体封装领域得到了广泛的应用。在本研究中，进行了高温长期可靠性评估，以评估Sn-2.3Ag （wt%）倒装芯片凸点的冶金反应和力学性能。在150℃下等温时效2000 h。在焊点界面处形成Ni3Sn4金属间化合物（IMC），随着等温时效时间的延长，IMC层的厚度增加；而随着IMC的生长，凹凸金属化层（Ni UBM）的厚度逐渐减小。线性回归分析表明，IMC层的生长厚度和Ni UBM层的消耗厚度随等温时效时间的平方根呈线性变化。结果表明，IMC层的生长速率常数为0.000756 μm， Ni UBM层的消耗速率常数为0.000303 μm/s1/2。然后，进行剪切试验来评估焊点的力学性能。随着等温时效时间的延长，抗剪强度变化不大。但抗剪强度略有下降后保持不变。通过对断口表面的分析，大多数情况下，焊点凸起内部表现出延性断裂行为，而在等温时效500、1000、1500和2000小时的情况下，试样出现了凹坑。通过观察断裂方式的变化，随着等温时效时间的延长，韧性断裂行为变得不那么突出，而凹坑的出现有变得更加突出的趋势。
{"title":"Metallurgical reactions and high-temperature long-term reliability of the Sn-2.3Ag flip-chip solder bump","authors":"Eun-Su Jang, Jeong-Won Yoon","doi":"10.1016/j.mee.2024.112293","DOIUrl":"10.1016/j.mee.2024.112293","url":null,"abstract":"<div><div>Flip-chip bonding technology has been extensively applied in the semiconductor packaging field given the recent increase in demand for electronic products requiring miniaturization and high performance. In this study, a high-temperature long-term reliability evaluation was performed to evaluate the metallurgical reaction and mechanical properties at the Sn-2.3Ag (wt%) flip-chip solder bump joints. Isothermal aging was performed for up to 2000 h at 150 °C. A Ni<sub>3</sub>Sn<sub>4</sub> intermetallic compound (IMC) was formed at the interface of the solder joints, and the thickness of the IMC layer increased as the isothermal aging time increased; however, the thickness of Ni under bump metallization (Ni UBM) layer was decreased during the growth of the IMC. Linear regression analysis showed that the growth thickness of the IMC layer and the consumption thickness of the Ni UBM layer varied linearly as functions of the square root of the isothermal aging time. Based on this analysis, the growth rate constant of the IMC layer and consumption rate constant of the Ni UBM layer were 0.000756 and 0.000303 μm/s<sup>1/2</sup>, respectively. Thereafter, shear tests were performed to evaluate the mechanical properties of the solder joints. As the isothermal aging time increased, the variation of shear strength was not large. However, the shear strength decreased slightly and then remained constant. As a result of the analysis of the fractured surface, most conditions exhibited ductile fracture behavior inside the solder bump, while in the case of specimens isothermally aged for 500, 1000, 1500, and 2000 h, cratering occurred. By observing the changes in the fracture mode, the ductile fracture behavior became less prominent, and the occurrence of cratering tended to become more prominent as the isothermal aging time increased.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"296 ","pages":"Article 112293"},"PeriodicalIF":2.6,"publicationDate":"2024-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142746270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1016/j.mee.2024.112294
Yongshuan Wu , Kefan Liu , Pengcheng She , Junhui Li
Planar magnetron sputtering reactors are widely utilized in the semiconductor industry due to their high deposition rate, low substrate temperature, and capability for large-area coating. Careful control of the reactor's flow field and magnetic field is essential to ensure appropriate thickness uniformity of the thin film and uniform etching of the target. Utilizing finite element analysis software, simulations were conducted to obtain numerical solutions for the airflow and magnetic field. An increase in the inlet diameter from 4 mm to 5 mm resulted in a 63.4 % decrease in the gas distribution unevenness coefficient. Conversely, increasing the outlet diameter from 1 mm to 2 mm led to a 636.6 % increase in the coefficient. At a pitch of 11.7 mm, the horizontal magnetic field component on the target surface peaked at 0.24 T, covering a larger area. A dual-runway structure reduced the circumferential component of the horizontal magnetic field by more than half. Analysis of the results precipitated the optimization of key component structures, resulting in an optimal solution: an air ring diameter of 5 mm, an outlet diameter of 1 mm, outlet spacing of 12 mm, double inlets, and 38 outlets on each side of the air ring. Further optimization determined the optimal magnet-to-target surface spacing of 11.7 mm, with the dual-runway structure effectively improving the uniformity of the radial magnetic field distribution and increasing the target etching area. This study provides a theoretical basis for optimizing planar magnetron sputtering reactors.
{"title":"Simulation and optimization of reactor airflow and magnetic field for enhanced thin film uniformity in physical vapor deposition","authors":"Yongshuan Wu , Kefan Liu , Pengcheng She , Junhui Li","doi":"10.1016/j.mee.2024.112294","DOIUrl":"10.1016/j.mee.2024.112294","url":null,"abstract":"<div><div>Planar magnetron sputtering reactors are widely utilized in the semiconductor industry due to their high deposition rate, low substrate temperature, and capability for large-area coating. Careful control of the reactor's flow field and magnetic field is essential to ensure appropriate thickness uniformity of the thin film and uniform etching of the target. Utilizing finite element analysis software, simulations were conducted to obtain numerical solutions for the airflow and magnetic field. An increase in the inlet diameter from 4 mm to 5 mm resulted in a 63.4 % decrease in the gas distribution unevenness coefficient. Conversely, increasing the outlet diameter from 1 mm to 2 mm led to a 636.6 % increase in the coefficient. At a pitch of 11.7 mm, the horizontal magnetic field component on the target surface peaked at 0.24 T, covering a larger area. A dual-runway structure reduced the circumferential component of the horizontal magnetic field by more than half. Analysis of the results precipitated the optimization of key component structures, resulting in an optimal solution: an air ring diameter of 5 mm, an outlet diameter of 1 mm, outlet spacing of 12 mm, double inlets, and 38 outlets on each side of the air ring. Further optimization determined the optimal magnet-to-target surface spacing of 11.7 mm, with the dual-runway structure effectively improving the uniformity of the radial magnetic field distribution and increasing the target etching area. This study provides a theoretical basis for optimizing planar magnetron sputtering reactors.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"296 ","pages":"Article 112294"},"PeriodicalIF":2.6,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142722999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-22DOI: 10.1016/j.mee.2024.112292
Alexey F. Kardo-Sysoev , Maksim N. Cherenev , Alexander G. Lyublinsky , Shaira A. Yusupova , Elena I. Belyakova , Mikhail I. Vexler
A new method for the comprehensive characterization of the picosecond-range switching process in semiconductor structures biased with a high DC voltage and triggered by a fast-rise voltage pulse has been proposed. The delayed impact ionization and switching of a p+-n-n+ silicon diode structure with 500 μm thick base layer were investigated. Experiments demonstrated an improvement in the switching characteristics with an increase in both the DC reverse bias and the fast-rise steep pulse. A voltage rise rate of up to 43 kV/ns was recorded, which was formed by a single diode based switch.
{"title":"The effect of DC bias and fast-rise pulse voltage on delayed impact ionization in a silicon diode structure","authors":"Alexey F. Kardo-Sysoev , Maksim N. Cherenev , Alexander G. Lyublinsky , Shaira A. Yusupova , Elena I. Belyakova , Mikhail I. Vexler","doi":"10.1016/j.mee.2024.112292","DOIUrl":"10.1016/j.mee.2024.112292","url":null,"abstract":"<div><div>A new method for the comprehensive characterization of the picosecond-range switching process in semiconductor structures biased with a high DC voltage and triggered by a fast-rise voltage pulse has been proposed. The delayed impact ionization and switching of a p<sup>+</sup>-n-n<sup>+</sup> silicon diode structure with 500 μm thick base layer were investigated. Experiments demonstrated an improvement in the switching characteristics with an increase in both the DC reverse bias and the fast-rise steep pulse. A voltage rise rate of up to 43 kV/ns was recorded, which was formed by a single diode based switch.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112292"},"PeriodicalIF":2.6,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1016/j.mee.2024.112291
Zepeng Wang , Qianzhen Su , Chao Zhang , Bo Zhang , Xiaolong Wen , Haoyuan Zhao , Dandan Liu , Jingliang Li , Jianhua Li
Due to their low parasitic capacitance, minimal substrate losses, and high inductance values, three-dimensional MEMS inductors are increasingly used in microelectronics applications, such as MEMS sensors, RF MEMS, and energy storage devices. Conventional fabrication techniques, including UV-LIGA lithography and through‑silicon vias (TSV), are commonly employed to create high-aspect-ratio structures for 3D inductors. However, these processes are often complex and challenging. To simplify the process, we proposed a novel fabrication method for arched inductors utilizing non-photosensitive polyimide. The high viscosity of polyimide facilitates the formation of sloped sidewalls during development, eliminating the need for high-aspect-ratio structures in the inductor fabrication. By controlling the development time, we achieve the desired polyimide sidewall morphology. Additionally, to achieve high inductance, a high-permeability Co-based amorphous alloy wire was used as the magnetic core of the inductor. The maximum inductance of the inductor can reach 1710 nH at an excitation frequency of 71.4 MHz.
{"title":"High inductance 3D arch inductor based on non-photosensitive polyimide","authors":"Zepeng Wang , Qianzhen Su , Chao Zhang , Bo Zhang , Xiaolong Wen , Haoyuan Zhao , Dandan Liu , Jingliang Li , Jianhua Li","doi":"10.1016/j.mee.2024.112291","DOIUrl":"10.1016/j.mee.2024.112291","url":null,"abstract":"<div><div>Due to their low parasitic capacitance, minimal substrate losses, and high inductance values, three-dimensional MEMS inductors are increasingly used in microelectronics applications, such as MEMS sensors, RF MEMS, and energy storage devices. Conventional fabrication techniques, including UV-LIGA lithography and through‑silicon vias (TSV), are commonly employed to create high-aspect-ratio structures for 3D inductors. However, these processes are often complex and challenging. To simplify the process, we proposed a novel fabrication method for arched inductors utilizing non-photosensitive polyimide. The high viscosity of polyimide facilitates the formation of sloped sidewalls during development, eliminating the need for high-aspect-ratio structures in the inductor fabrication. By controlling the development time, we achieve the desired polyimide sidewall morphology. Additionally, to achieve high inductance, a high-permeability Co-based amorphous alloy wire was used as the magnetic core of the inductor. The maximum inductance of the inductor can reach 1710 nH at an excitation frequency of 71.4 MHz.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"296 ","pages":"Article 112291"},"PeriodicalIF":2.6,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142705613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-08DOI: 10.1016/j.mee.2024.112263
Robert Fraser Armstrong , Philip Shields
Aluminium nitride (AlN) is a wide bandgap semiconductor with far reaching realised and potential applications in electronics and optoelectronic technology. For example, gallium nitride (GaN) quantum dots (QDs) housed within an AlN matrix are attractive due to the large bandgap offsets. However, making suitable AlN sites to house GaN QDs is challenging due to the difficulty in fashioning 3D AlN structures. This results from AlN's strong bonds that are difficult to chemically etch.
Whilst dry etching of AlN nanostructures has been explored, wet etching at the nanoscale has been limited by the common exposed facet of AlN being etch-resistant. Hence, wet etching of AlN to create uniform arrays of periodic nanohole nanostructures has, thus far, not been heavily explored.
In this paper, an initial dry etching of a 2D AlN planar template is used to expose alternative wet-etchable facets so that periodic arrays of nanohole structures are revealed by wet-etching. Both a study of different initial dry etched structures, including tapered nanoholes, and wet etching time were performed. A model to describe the dynamics of wet etching on the different dry etched nanohole structures is proposed. Periodic arrays of uniform nanohole features are realised that hold promise for applications such as the housing of site-controlled quantum dots.
{"title":"Fabrication of uniform, periodic arrays of exotic AlN nanoholes by combining dry etching and hot selective wet etching, accessing geometries unrealisable from wet etching of planar AlN","authors":"Robert Fraser Armstrong , Philip Shields","doi":"10.1016/j.mee.2024.112263","DOIUrl":"10.1016/j.mee.2024.112263","url":null,"abstract":"<div><div>Aluminium nitride (AlN) is a wide bandgap semiconductor with far reaching realised and potential applications in electronics and optoelectronic technology. For example, gallium nitride (GaN) quantum dots (QDs) housed within an AlN matrix are attractive due to the large bandgap offsets. However, making suitable AlN sites to house GaN QDs is challenging due to the difficulty in fashioning 3D AlN structures. This results from AlN's strong bonds that are difficult to chemically etch.</div><div>Whilst dry etching of AlN nanostructures has been explored, wet etching at the nanoscale has been limited by the common exposed facet of AlN being etch-resistant. Hence, wet etching of AlN to create uniform arrays of periodic nanohole nanostructures has, thus far, not been heavily explored.</div><div>In this paper, an initial dry etching of a 2D AlN planar template is used to expose alternative wet-etchable facets so that periodic arrays of nanohole structures are revealed by wet-etching. Both a study of different initial dry etched structures, including tapered nanoholes, and wet etching time were performed. A model to describe the dynamics of wet etching on the different dry etched nanohole structures is proposed. Periodic arrays of uniform nanohole features are realised that hold promise for applications such as the housing of site-controlled quantum dots.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112263"},"PeriodicalIF":2.6,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142660680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-06DOI: 10.1016/j.mee.2024.112284
Mor Mordechai Dahan , Halid Mulaosmanovic , Or Levit , Stefan Dünkel , Johannes Müller , Sven Beyer , Eilam Yalon
FeFET technology offers the potential for fast, energy-efficient, low-cost, and high-capacity non-volatile memory and neuromorphic devices. However, charge trapping significantly affects device operation, leading to issues like read-after-write delay and limited endurance. Therefore, a detailed understanding of charge trapping, charge origin and its role in polarization switching is crucial. In this study, we uncover the spectral energy origin of polarization charges in Si:HfO2 N-FeFET by probing electron (conduction band) and hole (valence band) currents separately during polarization-voltage (P–V) measurements. We utilize a fast (∼20 ns) and modified positive-up-negative-down (PUND) technique, where bulk, source, and drain currents of the FeFET are measured separately. The nanosecond timescale of the measurement results in measurable currents in FeFETs having dimensions of a few μm. This charge separation shows that program (PRG, VGS > 0) charge originates from the conduction band, whereas erase (ERS, VGS < 0) originates from the valence band of the Si. Moreover, the polarization curve (P–V) of a cycled device (following 5000 PRG/ERS pulses) shows measurable hysteresis even though the transfer curve of the same device shows that the memory window in the threshold voltage vanishes. Therefore, the FeFET polarization state can be read without delay after write operation by the fast PUND measurement, both for pristine and cycled FeFETs.
{"title":"Origin of charges in bulk Si:HfO2 FeFET probed by nanosecond polarization measurements","authors":"Mor Mordechai Dahan , Halid Mulaosmanovic , Or Levit , Stefan Dünkel , Johannes Müller , Sven Beyer , Eilam Yalon","doi":"10.1016/j.mee.2024.112284","DOIUrl":"10.1016/j.mee.2024.112284","url":null,"abstract":"<div><div>FeFET technology offers the potential for fast, energy-efficient, low-cost, and high-capacity non-volatile memory and neuromorphic devices. However, charge trapping significantly affects device operation, leading to issues like read-after-write delay and limited endurance. Therefore, a detailed understanding of charge trapping, charge origin and its role in polarization switching is crucial. In this study, we uncover the spectral energy origin of polarization charges in Si:HfO<sub>2</sub> N-FeFET by probing electron (conduction band) and hole (valence band) currents separately during polarization-voltage (<em>P–V</em>) measurements. We utilize a fast (∼20 ns) and modified positive-up-negative-down (PUND) technique, where bulk, source, and drain currents of the FeFET are measured separately. The nanosecond timescale of the measurement results in measurable currents in FeFETs having dimensions of a few μm. This charge separation shows that program (PRG, <em>V</em><sub>GS</sub> > 0) charge originates from the conduction band, whereas erase (ERS, <em>V</em><sub>GS</sub> < 0) originates from the valence band of the Si. Moreover, the polarization curve (<em>P–V</em>) of a cycled device (following 5000 PRG/ERS pulses) shows measurable hysteresis even though the transfer curve of the same device shows that the memory window in the threshold voltage vanishes. Therefore, the FeFET polarization state can be read without delay after write operation by the fast PUND measurement, both for pristine and cycled FeFETs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"296 ","pages":"Article 112284"},"PeriodicalIF":2.6,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142593419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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