Pub Date : 2025-09-04DOI: 10.1016/j.mee.2025.112406
Wei Hu , Zhiming Dai , Chunlin Wu , Jiajun Lin , Chenxiao Ji , Fanyang Li , Faxiang Wang
The device mismatch of non-volatile resistive random access memory (nvRRAM) and the performance limitations of conventional analog readout circuits cause low quantization precision and high power consumption in current RRAM-based computation circuits. To address these issues, we propose a Single-Reference Successive Approximation Current-Sense Amplifier (SRSA-CSA) based on single-reference source reuse and a closed-loop feedback architecture. Compared to state-of-the-art RS-CSA designs (Ye et al., 2023 [1]), SRSA-CSA achieves a 2.83× faster readout latency (30 ns vs. 85 ns) and 23.4 % lower power consumption (64.67 μW vs. 84.6 μW) under 180 nm CMOS technology, offering a new paradigm for energy-efficient computation-in-memory chip design.
非易失性电阻随机存取存储器（nvRRAM）的器件失配和传统模拟读出电路的性能限制，导致当前基于非易失性电阻随机存取存储器的计算电路量化精度低、功耗高。为了解决这些问题，我们提出了一种基于单参考源复用和闭环反馈架构的单参考逐次逼近电流检测放大器（SRSA-CSA）。与最先进的RS-CSA设计（Ye et al., 2023[1]）相比，SRSA-CSA在180 nm CMOS技术下实现了2.83倍的读出延迟（30 ns vs. 85 ns）和23.4%的低功耗（64.67 μW vs. 84.6 μW），为节能的内存中计算芯片设计提供了新的范例。
{"title":"Low power current-sense amplifier with single-reference reuse and closed-loop feedback for energy-efficient RRAM computing-in-memory","authors":"Wei Hu , Zhiming Dai , Chunlin Wu , Jiajun Lin , Chenxiao Ji , Fanyang Li , Faxiang Wang","doi":"10.1016/j.mee.2025.112406","DOIUrl":"10.1016/j.mee.2025.112406","url":null,"abstract":"<div><div>The device mismatch of non-volatile resistive random access memory (nvRRAM) and the performance limitations of conventional analog readout circuits cause low quantization precision and high power consumption in current RRAM-based computation circuits. To address these issues, we propose a Single-Reference Successive Approximation Current-Sense Amplifier (SRSA-CSA) based on single-reference source reuse and a closed-loop feedback architecture. Compared to state-of-the-art RS-CSA designs (Ye et al., 2023 [<span><span>1</span></span>]<sup>)</sup>, SRSA-CSA achieves a 2.83× faster readout latency (30 ns vs. 85 ns) and 23.4 % lower power consumption (64.67 μW vs. 84.6 μW) under 180 nm CMOS technology, offering a new paradigm for energy-efficient computation-in-memory chip design.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112406"},"PeriodicalIF":3.1,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145026340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-04DOI: 10.1016/j.mee.2025.112400
Jiayi Zhang , Huaizhi Luo , Haoyan Liu , Fei Zhao , Yongliang Li
In this work, O3 passivation technology for the novel stacked SiGe/Si FinFET input-output (I/O) devices was investigated. First, the O3 passivation technology was validated based on SiGe MOS capacitance (CAP) structure., with results indicating that interface state density (Dit) can be reduced to 5.12 × 1012 eV−1 cm−2. Then, to improve the electrical performance of the stacked SiGe/Si FinFET I/O device, the O3 passivation technology was introduced between the SiGe/Si fin and gate oxide. As a result, the electrical performance for the stacked SiGe/Si FinFET I/O device was significantly improved. For example, SS could be reduced from the 168 mV/dec to 113 mV/dec, and gm could be improved from the 62 μS to 94 μS, which was mainly attributed to the O3 passivation resulting in the reduction of Dit. Furthermore, its reliability assessment was also performed. The result confirmed that threshold voltage (VTH) drift under negative bias temperature instability (NBTI) and hot carrier injection (HCI) stress were improved by 52.1 % and 60.3 %, respectively. Meanwhile, its maximum operating voltage (Vmax) for a 10 years lifetime at a failure rate of 0.01 % could reach to 2.65 V. Therefore, the O3 passivation process is practical for the stacked SiGe/Si I/O FinFET device in advanced GAA platforms.
{"title":"Improving electrical performance and reliability of stacked SiGe/Si FinFETs using O3 passivation for I/O devices","authors":"Jiayi Zhang , Huaizhi Luo , Haoyan Liu , Fei Zhao , Yongliang Li","doi":"10.1016/j.mee.2025.112400","DOIUrl":"10.1016/j.mee.2025.112400","url":null,"abstract":"<div><div>In this work, O<sub>3</sub> passivation technology for the novel stacked SiGe/Si FinFET input-output (I/O) devices was investigated. First, the O<sub>3</sub> passivation technology was validated based on SiGe MOS capacitance (CAP) structure., with results indicating that interface state density (D<sub>it</sub>) can be reduced to 5.12 × 10<sup>12</sup> eV<sup>−1</sup> cm<sup>−2</sup>. Then, to improve the electrical performance of the stacked SiGe/Si FinFET I/O device, the O<sub>3</sub> passivation technology was introduced between the SiGe/Si fin and gate oxide. As a result, the electrical performance for the stacked SiGe/Si FinFET I/O device was significantly improved. For example, SS could be reduced from the 168 mV/dec to 113 mV/dec, and g<sub>m</sub> could be improved from the 62 μS to 94 μS, which was mainly attributed to the O<sub>3</sub> passivation resulting in the reduction of D<sub>it</sub>. Furthermore, its reliability assessment was also performed. The result confirmed that threshold voltage (V<sub>TH</sub>) drift under negative bias temperature instability (NBTI) and hot carrier injection (HCI) stress were improved by 52.1 % and 60.3 %, respectively. Meanwhile, its maximum operating voltage (V<sub>max</sub>) for a 10 years lifetime at a failure rate of 0.01 % could reach to 2.65 V. Therefore, the O<sub>3</sub> passivation process is practical for the stacked SiGe/Si I/O FinFET device in advanced GAA platforms.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112400"},"PeriodicalIF":3.1,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-03DOI: 10.1016/j.mee.2025.112402
Jing Yuan , Xiaojuan Chen , Yichuan Zhang , Ying Luo , Binhao Guo , Ke Wei , Yankui Li , Weijun Luo , Weichao Wu , Sen Huang
The SiNx/AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on silicon have been fabricated for low-supply-voltage applications. The devices, featuring a gate length (Lg) of approximately 140 nm, exhibited excellent DC characteristics: a contact resistance (Rc) of 0.24 Ω·mm, a maximum saturated drain current (Idmax) of 1.86 A/mm at a gate voltage (Vgs) of 2 V, an on-resistance (Ron) of 1.4 Ω·mm, and a peak transconductance (Gmmax) of 466 mS/mm at a drain voltage (Vds) of 6 V. In RF measurements, the devices achieved ultra-low minimum noise figure (NFmin) of 0.54 (0.66) dB at Vds of 5 (6) V at 30 GHz, along with a good two-tone linearity, the ratio of output third-order intercept point (OIP3) to direct current output power (Pdc), denoted as OIP3/Pdc is 12.4 (9.9) dB at Vds of 5 (6) V. Pulsed-wave (PW) power measurements indicated the devices have both high output power (Pout) of 1.1 (1.6) W/mm and power-added efficiency (PAE) of 50.2 (49.4 %) at Vds of 5 (6) V. These results demonstrate the SiNx/AlN/GaN MIS-HEMTs on silicon have promising potential in low-supply-voltage mm-wave low-noise and high-power applications.
硅基SiNx/AlN/GaN金属-绝缘体-半导体高电子迁移率晶体管（mis - hemt）已制备成功。该器件栅极长度（Lg）约为140 nm，具有优异的直流特性：接触电阻（Rc）为0.24 Ω·mm，栅极电压（Vgs）为2 V时最大饱和漏极电流（Idmax）为1.86 a /mm，导通电阻（Ron）为1.4 Ω·mm，漏极电压（Vds）为6 V时峰值跨导（Gmmax）为466 mS/mm。在射频测量中，该器件在30 GHz的Vds为5 (6)V时实现了0.54 (0.66)dB的超低最小噪声系数（NFmin），同时具有良好的双音线性度，输出三阶截距点（OIP3）与直流输出功率（Pdc）的比值。脉冲波（PW）功率测量表明，该器件在Vds为5 (6)v时具有1.1 (1.6)W/mm的高输出功率（Pout）和50.2（49.4%）的功率附加效率（PAE）。这些结果表明，硅基SiNx/AlN/GaN miss - hemt在低电源电压毫米波低噪声和高功率应用中具有广阔的潜力。
{"title":"Low-noise and high-power AlN/GaN MIS-HEMTs on silicon for mm-wave low-voltage applications","authors":"Jing Yuan , Xiaojuan Chen , Yichuan Zhang , Ying Luo , Binhao Guo , Ke Wei , Yankui Li , Weijun Luo , Weichao Wu , Sen Huang","doi":"10.1016/j.mee.2025.112402","DOIUrl":"10.1016/j.mee.2025.112402","url":null,"abstract":"<div><div>The SiN<sub>x</sub>/AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on silicon have been fabricated for low-supply-voltage applications. The devices, featuring a gate length (<em>L</em><sub>g</sub>) of approximately 140 nm, exhibited excellent DC characteristics: a contact resistance (<em>R</em><sub>c</sub>) of 0.24 Ω·mm, a maximum saturated drain current (<em>I</em><sub>dmax</sub>) of 1.86 A/mm at a gate voltage (<em>V</em><sub>gs</sub>) of 2 V, an on-resistance (<em>R</em><sub>on</sub>) of 1.4 Ω·mm, and a peak transconductance (<em>Gm</em><sub>max</sub>) of 466 mS/mm at a drain voltage (<em>V</em><sub>ds</sub>) of 6 V. In RF measurements, the devices achieved ultra-low minimum noise figure (<em>NF</em><sub>min</sub>) of 0.54 (0.66) dB at <em>V</em><sub>ds</sub> of 5 (6) V at 30 GHz, along with a good two-tone linearity, the ratio of output third-order intercept point (<em>OIP</em><sub>3</sub>) to direct current output power (<em>P</em><sub>dc</sub>), denoted as <em>OIP</em><sub>3</sub>/<em>P</em><sub>dc</sub> is 12.4 (9.9) dB at <em>V</em><sub>ds</sub> of 5 (6) V. Pulsed-wave (PW) power measurements indicated the devices have both high output power (<em>P</em><sub>out</sub>) of 1.1 (1.6) W/mm and power-added efficiency (PAE) of 50.2 (49.4 %) at <em>V</em><sub>ds</sub> of 5 (6) V. These results demonstrate the SiN<sub>x</sub>/AlN/GaN MIS-HEMTs on silicon have promising potential in low-supply-voltage mm-wave low-noise and high-power applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112402"},"PeriodicalIF":3.1,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145047638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-02DOI: 10.1016/j.mee.2025.112386
Sebastian Onder, Jürgen Burin, Philipp Gaggl, Andreas Gsponer, Thomas Bergauer, Simon Waid
Future collider experiments demand a new generation of tracking detectors with excellent spatial and temporal resolution, along with enhanced radiation hardness. Monolithic active pixel sensors (MAPS) based on silicon CMOS technology are proven to provide fine spatial and temporal resolution while being cost-effective. In terms of radiation hardness, however, wide band-gap semiconductors such as silicon carbide (SiC) promise superior performance. In this work, we make a first step towards MAPS development based on SiC-CMOS technology. We used the Fraunhofer IISB 2 µm SiC-CMOS process to design the first stage in the electronic read-out chain of a MAPS, a charge-sensitive amplifier (CSA). Circuit simulations show that an equivalent noise charge of to is attainable for an input capacitance in the range of to at room temperature. The attained bandwidth of was primarily limited by the large size of the MOSFETs in the used SiC-CMOS technology. We believe that a further increase in integration density could make SiC-MAPS a compelling alternative to its silicon-based counterparts.
{"title":"Towards silicon carbide monolithic active pixel radiation sensors","authors":"Sebastian Onder, Jürgen Burin, Philipp Gaggl, Andreas Gsponer, Thomas Bergauer, Simon Waid","doi":"10.1016/j.mee.2025.112386","DOIUrl":"10.1016/j.mee.2025.112386","url":null,"abstract":"<div><div>Future collider experiments demand a new generation of tracking detectors with excellent spatial and temporal resolution, along with enhanced radiation hardness. Monolithic active pixel sensors (MAPS) based on silicon CMOS technology are proven to provide fine spatial and temporal resolution while being cost-effective. In terms of radiation hardness, however, wide band-gap semiconductors such as silicon carbide (SiC) promise superior performance. In this work, we make a first step towards MAPS development based on SiC-CMOS technology. We used the Fraunhofer IISB 2<!--> <!-->µm SiC-CMOS process to design the first stage in the electronic read-out chain of a MAPS, a charge-sensitive amplifier (CSA). Circuit simulations show that an equivalent noise charge of <span><math><mrow><mn>95</mn><mspace></mspace><mstyle><mi>e</mi></mstyle></mrow></math></span> to <span><math><mrow><mn>205</mn><mspace></mspace><mstyle><mi>e</mi></mstyle></mrow></math></span> is attainable for an input capacitance in the range of <span><math><mrow><mn>0</mn><mo>.</mo><mn>5</mn><mspace></mspace><mstyle><mi>p</mi><mi>F</mi></mstyle></mrow></math></span> to <span><math><mrow><mn>4</mn><mo>.</mo><mn>5</mn><mspace></mspace><mstyle><mi>p</mi><mi>F</mi></mstyle></mrow></math></span> at room temperature. The attained bandwidth of <span><math><mrow><mn>31</mn><mspace></mspace><mstyle><mi>k</mi><mi>H</mi><mi>z</mi></mstyle></mrow></math></span> was primarily limited by the large size of the MOSFETs in the used SiC-CMOS technology. We believe that a further increase in integration density could make SiC-MAPS a compelling alternative to its silicon-based counterparts.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112386"},"PeriodicalIF":3.1,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144925095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-02DOI: 10.1016/j.mee.2025.112399
Po-Hsun Chen , Yung-Fang Tan , Yen-Che Huang
In this study, a via-hole type thin-film transistor (TFT) device based on indium–gallium–zinc–oxide (IGZO) material with the drain-connected field plate (DCFP) structure is investigated. Compared to the traditional symmetric source/drain structure, the device with DCFP exhibits unsaturated output drain current properties during operation. Also, according to the electrical measurements and the simulation results, a high electrical field is generated on the etching stop layer (ESL) right underneath the extended field plate, resulting in the effect of drain-induced barrier lowering (DIBL) and the shifts of threshold voltage (Vt). On the other hand, the unsaturated output characteristics are applied as a variable resistor according to the given gate bias (Vg). Therefore, a high pass filter (HPF) circuit is demonstrated based on the TFT device with the DCFP structure, which suggests its potential application for variable resistors based on the gate bias in the future circuit designs.
{"title":"Investigating unsaturated output characteristics and potential applications of amorphous InGaZnO thin-film transistors with drain-connected field plate","authors":"Po-Hsun Chen , Yung-Fang Tan , Yen-Che Huang","doi":"10.1016/j.mee.2025.112399","DOIUrl":"10.1016/j.mee.2025.112399","url":null,"abstract":"<div><div>In this study, a via-hole type thin-film transistor (TFT) device based on indium–gallium–zinc–oxide (IGZO) material with the drain-connected field plate (DCFP) structure is investigated. Compared to the traditional symmetric source/drain structure, the device with DCFP exhibits unsaturated output drain current properties during operation. Also, according to the electrical measurements and the simulation results, a high electrical field is generated on the etching stop layer (ESL) right underneath the extended field plate, resulting in the effect of drain-induced barrier lowering (DIBL) and the shifts of threshold voltage (Vt). On the other hand, the unsaturated output characteristics are applied as a variable resistor according to the given gate bias (Vg). Therefore, a high pass filter (HPF) circuit is demonstrated based on the TFT device with the DCFP structure, which suggests its potential application for variable resistors based on the gate bias in the future circuit designs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112399"},"PeriodicalIF":3.1,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144996574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-29DOI: 10.1016/j.mee.2025.112398
Samuel Chef , Nagarajan Raghavan
{"title":"Introduction to the special issue on selected work from the 31st International Symposium on the physical and failure analysis of integrated circuits (IPFA 2024)","authors":"Samuel Chef , Nagarajan Raghavan","doi":"10.1016/j.mee.2025.112398","DOIUrl":"10.1016/j.mee.2025.112398","url":null,"abstract":"","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112398"},"PeriodicalIF":3.1,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-20DOI: 10.1016/j.mee.2025.112397
Maximilian Ell, Ahmet Büyükakyüz, Paul Werginz, Günther Zeck
CMOS-based microelectrode arrays (MEAs) are used to record the electrical activity in neural tissues down to micron-scale cellular structures at high spatiotemporal resolution. Continuous recording of extracellular voltages would, however generate large datasets with very sparse spatial and temporal information. Towards an efficient strategy, we propose here a Field Programmable Gate Array (FPGA) which filters the continuous CMOS MEA data stream sampled at 28 kHz and extracts electrophysiological relevant information.
In a first step, sensors of interest are selected based on the electrical label-free identification of those sensors covered by the neural tissue via adhesion noise spectroscopy. The adhesion noise-based electrical imaging is validated against light microscopic images. The FPGA finite impulse response (FIR)-filtered data is validated against software-based post-processed data.
In a second step, we implement a spike-triggered average (STA) algorithm to identify and visualize electrical activity at subcellular resolution in retinal neurons, which allows for the tracking of axonal signal propagation within the neural tissue.
This label-free, non-invasive method enables the localization of sensors of interest for electrophysiological recordings and the extraction of neuronal signals. It represents a significant advancement in neuroscience tools, which facilitates the study of neuronal network dynamics at unprecedented spatiotemporal resolution.
{"title":"Digital filter on FPGA for subcellular resolution electrophysiology using a high-density CMOS-based microelectrode array","authors":"Maximilian Ell, Ahmet Büyükakyüz, Paul Werginz, Günther Zeck","doi":"10.1016/j.mee.2025.112397","DOIUrl":"10.1016/j.mee.2025.112397","url":null,"abstract":"<div><div>CMOS-based microelectrode arrays (MEAs) are used to record the electrical activity in neural tissues down to micron-scale cellular structures at high spatiotemporal resolution. Continuous recording of extracellular voltages would, however generate large datasets with very sparse spatial and temporal information. Towards an efficient strategy, we propose here a Field Programmable Gate Array (FPGA) which filters the continuous CMOS MEA data stream sampled at 28 kHz and extracts electrophysiological relevant information.</div><div>In a first step, sensors of interest are selected based on the electrical label-free identification of those sensors covered by the neural tissue via adhesion noise spectroscopy. The adhesion noise-based electrical imaging is validated against light microscopic images. The FPGA finite impulse response (FIR)-filtered data is validated against software-based post-processed data.</div><div>In a second step, we implement a spike-triggered average (STA) algorithm to identify and visualize electrical activity at subcellular resolution in retinal neurons, which allows for the tracking of axonal signal propagation within the neural tissue.</div><div>This label-free, non-invasive method enables the localization of sensors of interest for electrophysiological recordings and the extraction of neuronal signals. It represents a significant advancement in neuroscience tools, which facilitates the study of neuronal network dynamics at unprecedented spatiotemporal resolution.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112397"},"PeriodicalIF":3.1,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144932174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-19DOI: 10.1016/j.mee.2025.112395
Fei-Le Xue , Li-Xing Li , Zhong-Da Zhang , Xu Gao , Jian-Long Xu , Ya-Nan Zhong , Sui-Dong Wang
Memcapacitors emerge as a promising electronic element for low-power artificial neural networks, whereas research on their applications remains limited due to the challenge of using capacitance-based state variables. We report the probing into transient responses of an organic memcapacitor and how the transient features endow the device with the function of multiply-and-accumulate operation. The neural network based on the organic memcapacitor array is capable of processing spatial and temporal signal recognition, as well demonstrated by its excellent performance in fashion image recognition and arrhythmia detection, achieving the classification accuracies of 87 % and 99 %, respectively. This work initiates a potential approach to adopting dynamic characteristics, rather than steady-state behaviors, of memcapacitors for implementing neuromorphic computing tasks.
{"title":"Organic memcapacitor-based neural network for diverse signal recognition","authors":"Fei-Le Xue , Li-Xing Li , Zhong-Da Zhang , Xu Gao , Jian-Long Xu , Ya-Nan Zhong , Sui-Dong Wang","doi":"10.1016/j.mee.2025.112395","DOIUrl":"10.1016/j.mee.2025.112395","url":null,"abstract":"<div><div>Memcapacitors emerge as a promising electronic element for low-power artificial neural networks, whereas research on their applications remains limited due to the challenge of using capacitance-based state variables. We report the probing into transient responses of an organic memcapacitor and how the transient features endow the device with the function of multiply-and-accumulate operation. The neural network based on the organic memcapacitor array is capable of processing spatial and temporal signal recognition, as well demonstrated by its excellent performance in fashion image recognition and arrhythmia detection, achieving the classification accuracies of 87 % and 99 %, respectively. This work initiates a potential approach to adopting dynamic characteristics, rather than steady-state behaviors, of memcapacitors for implementing neuromorphic computing tasks.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112395"},"PeriodicalIF":3.1,"publicationDate":"2025-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144863635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1016/j.mee.2025.112396
Huikang Liang , Zhiwen Shu , Yuting Jiang , Man Liu , Quan Wang , Lei Chen , YueQiang Hu , Ming Ji , Huigao Duan
The fabrication of high-resolution and high-dense Cr masks is critical for precise pattern transfer in reactive etching processes. Lift-off based on electron-beam lithography is a commonly used and simple method for fabricating Cr nanostructures below 100-nm scale. However, conventional wet lift-off method suffers from issues such as fragment residues and low yield. In this work, we propose a dry lift-off method leveraging the weak adhesion between sputtered materials and PMMA resist to achieve high-yield (∼100 %) fabrication of high-resolution (line width<100 nm) and high-dense (gap<100 nm) Cr nanostructures that wet lift-off can hardly achieve. We demonstrate the application capability of our method by fabricating silicon infrared metalens using Cr nanostructures as etching hard masks, showing its potential for nanodevices fabrication with high-resolution and high-dense requirements.
{"title":"Reliable fabrication of nanoscale Cr patterns with dry lift-off process for hard mask applications in microelectronics","authors":"Huikang Liang , Zhiwen Shu , Yuting Jiang , Man Liu , Quan Wang , Lei Chen , YueQiang Hu , Ming Ji , Huigao Duan","doi":"10.1016/j.mee.2025.112396","DOIUrl":"10.1016/j.mee.2025.112396","url":null,"abstract":"<div><div>The fabrication of high-resolution and high-dense Cr masks is critical for precise pattern transfer in reactive etching processes. Lift-off based on electron-beam lithography is a commonly used and simple method for fabricating Cr nanostructures below 100-nm scale. However, conventional wet lift-off method suffers from issues such as fragment residues and low yield. In this work, we propose a dry lift-off method leveraging the weak adhesion between sputtered materials and PMMA resist to achieve high-yield (∼100 %) fabrication of high-resolution (line width<100 nm) and high-dense (gap<100 nm) Cr nanostructures that wet lift-off can hardly achieve. We demonstrate the application capability of our method by fabricating silicon infrared metalens using Cr nanostructures as etching hard masks, showing its potential for nanodevices fabrication with high-resolution and high-dense requirements.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112396"},"PeriodicalIF":3.1,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144841379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-06DOI: 10.1016/j.mee.2025.112394
David G. Refaldi , Gerardo Malavena , Luca Colombo , Luca Chiavarone , Aurelio G. Mauri , Alessandro S. Spinelli , Christian Monzio Compagnoni
In this letter, we report clear experimental evidence of the existence of a turnaround in the temperature dependence of RTN in 3D nand Flash memories, showing up when entering the cryogenic regime. The origin of this phenomenology is traced back to the change of the dominant transport mechanism through the grain boundaries of the polysilicon channel of the memory cells, from thermionic emission to quantum-mechanical tunneling. This change decreases the impact of the charging/discharging of microscopic defects at the grain boundaries on cell current, making RTN in the cryogenic regime much more bearable than what expected from the extrapolation of room temperature data.
{"title":"Turnaround in the temperature dependence of RTN in 3D nand arrays entering the cryogenic regime","authors":"David G. Refaldi , Gerardo Malavena , Luca Colombo , Luca Chiavarone , Aurelio G. Mauri , Alessandro S. Spinelli , Christian Monzio Compagnoni","doi":"10.1016/j.mee.2025.112394","DOIUrl":"10.1016/j.mee.2025.112394","url":null,"abstract":"<div><div>In this letter, we report clear experimental evidence of the existence of a turnaround in the temperature dependence of RTN in 3D <span>nand</span> Flash memories, showing up when entering the cryogenic regime. The origin of this phenomenology is traced back to the change of the dominant transport mechanism through the grain boundaries of the polysilicon channel of the memory cells, from thermionic emission to quantum-mechanical tunneling. This change decreases the impact of the charging/discharging of microscopic defects at the grain boundaries on cell current, making RTN in the cryogenic regime much more bearable than what expected from the extrapolation of room temperature data.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112394"},"PeriodicalIF":3.1,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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