Microelectronic Engineering最新文献

Backside Power Delivery Network (BSPDN) is a crucial technology for integrated circuits at sub-3 nm technology nodes. The primary challenge resides in utilizing nano through silicon via (nano-TSV) to establish connections between the backside power network and buried power rails, thereby facilitating transistor powering. The key technology is to ensure a smooth sidewall morphology and prevent damage to buried power rails (BPR) due to over-etching. In this study, non-Bosch and Bosch techniques are compared using simulation. The results demonstrate that while the non-Bosch technique yields smooth sidewalls, it inevitably leads to over-etching, whereas Bosch effectively avoids over-etching. The etching of scallop-free nano-TSV is achieved by optimizing the Bosch process, which involves the use of inductively coupled plasma (ICP). Finally, metal filling of nano-TSV is successfully achieved. Thus, the nano-TSV etching method is established as viable for BSPDN.

In response to the urgent imperative of combating global warming and advancing sustainable energy solutions, an innovative approach has emerged, capitalizing on bicycles and road bike lane infrastructure. This solution integrates a Smart Lithium Battery Charging System with a Sustainable Energy Harvesting Pad (SEHP) designed for cyclists. The SEHP harnesses piezoelectric energy from mechanical vibrations and kinetic energy from lightweight vehicles. It produces clean, renewable electricity as an alternative to traditional power sources. Comprehensive assessments of the SEHP's energy generation performance at various proficiency levels have revealed impressive capabilities. An electronic emulator system is developed to support academic and research communities, simulating scenarios on bike lanes to efficiently charge 36.36 Wh lithium batteries at various cycling proficiency levels. The study involved specific circuit design, seamless integration with the custom Smart Lithium Battery Charging System, and optimization using Microcontroller hardware and software solutions. Practical prototypes verified the emulator's functionality and real-world applicability, making it an authentic replica of the SEHP's outcomes. This innovative technology enhances our understanding of SEHP and enables comparative analysis against other energy sources, contributing to a more sustainable future.

This paper presents a low-profile wide scan angle multibeam conformal antenna array system with a novel feeding network for $28$ GHz mm-wave 5G applications. The proposed antenna system utilizes two conventional branch-line couplers as its beamforming network. A novel feeding technique is applied to generate $7$ beams with these couplers that are usually capable of generating $2$ beams. The proposed solution provides a wide scanning range with a minimum realized gain of $5$ dBi from $-{90}^{°}$ to ${90}^{°}$ owing to this feeding approach and the peculiar placement of the array elements on a $0.15$ mm thick R-F775 bendable substrate. The generated beams at their steer direction have the minimum and maximum gain values of $6.5$ dBi and $9.7$ dBi, respectively. A low-cost PCB manufacturing technique based on soft lithography and wet etching is used. The system dimensions excluding extra connector sections are $67\times 15\times 3{\mathrm{mm}}^3$. The proposed flexible design is suitable for lightweight 5G communication systems and handsets with its compact low-complexity beamforming network, and wide ${180}^{°}$ continuous covering angle.

Control of surface molecular contamination (SMC) for components used in chemical vapor deposition (CVD), atomic layer deposition (ALD) and EUV photolithography is important to maintaining high yield and optimal tool operation at the latest process nodes in leading edge semiconductor manufacturing. High temperature thermal desorption spectroscopy (TDS) is a versatile tool for analyzing the cleanliness of surfaces, simulating thermal vacuum processes and studying the kinetics of desorption processes. A basic analysis of TD spectra allows for full characterization of volatile outgassing from surfaces, while detailed analysis can provide chemical information about the substrate surface.

In fundamental studies, TDS is often carried out from low temperatures to room temperature or for small samples. However, for microelectronics applications, high temperature studies of large (100 mm or greater) samples are of greater interest due to direct applications for cleanliness testing and thermal vacuum simulation. A limitation for TDS sensitivity is the outgassing of sample stage materials, particularly when analyzing gases that may be present in the chamber background such as water, CO and CO₂. Typical sample stages are often tested only for total pressure or at room temperature.

In this study, we present a simple ultra-high vacuum (UHV) compatible sample heating stage for trace outgassing analysis of 100 mm samples at high temperatures. Simulation results are presented to support the feasibility of the concept. Experimental results verify the cleanliness of the stage via room temperature residual gas analysis (RGA) analysis and X-ray photoelectron spectroscopy (XPS) of stage components. Finally, use of this stage in a TDS analysis of a 100 mm Si witness wafer and comparison to room temperature RGA demonstrates operational capability.

The sample heating stage is both shown to be clean at high temperature and capable of analyzing 100 mm wafers to higher sensitivity than room temperature RGA for all m/z at the 1 × 10⁻⁹ mbar level. Despite its high performance, the heating stage is also easily produced by any laser machining service, greatly improving the accessibility of UHV science for all researchers.

The new radiator incorporated with nanocomposites improve radiation characteristics of nonagon shaped antenna. The design comprise two nanocomposite materials loaded in slots that separately enhance lower and upper band radiation. The CPW antenna consists of nonagon shaped ring with heptagon radiating element that consists of inverted U and rigid shaped slots. The longer slot has been deliberately chosen to accommodate mid-frequency of two resonance frequencies and shorter slot isolates surface current distributed along radiating patch, left and right side. The Poly (3, 4 ethyelene dioxythiophene): Polystyrene Sulfonate-Silver nanowire (PEDOT:PSS-AgNW) nanocomposite filled in shorter slot improves gain, bandwidth and return loss of upper band, magnetite - Polyaniline (Fe₃O₄-PANI) filled in longer slot enhance lower band. The measured result proved to improve bandwidth, gain, radiation efficiency and polarization of lower, upper band. The flexible attributes of radiator studied extensively by wearable application by placing them on wrist and jeans. The fabricated antenna produce a bandwidth of 2.12–3.29 GHz in lower band, 4.51–6.00 GHz in upper band for 2.40/5.20/5.80 GHz WLAN, 2.50/5.50 GHz WiMAX, 2.40/4.90/5.20/5.50/5.80 GHz WiFi, 5G SUB-6 GHz and ISM bands.

Co thin films masked with SiO₂/Si₃N₄ layers were etched using a high-density plasma of a CH₃COCH₃/Ar gas mixture. As the concentration of CH₃COCH₃ increased, the etch rate of the Co thin films and etch selectivity decreased. Optimal etch profiles of the Co films without redeposition were achieved owing to the formation of Co compounds and a passivation layer, which facilitated a high degree of anisotropy. Moreover, the etch characteristics of the Co films were examined using the ICP RF power, dc-bias voltage to the substrate, and process pressure. The active species in plasmas and Co compounds formed during etching were investigated using optical emission spectroscopy and X-ray photoelectron spectroscopy. Finally, the Co thin films patterned with 300 nm lines were etched using a CH₃COCH₃/Ar gas mixture under optimized etch conditions. The findings suggest that a CH₃COCH₃/Ar gas mixture can serve as an effective etch gas for fabricating dry-etched Co thin films.

In this study, all-optical OR, exclusive OR (XOR), NOR, XNOR, AND, NAND, and NOT logic gates using metal-insulator-metal (MIM) waveguides with a rectangular ring resonator are designed and analyzed. The structure has a silver plate with three input waveguides, one output waveguide, and a rectangular ring resonator. One of the input ports is used as a control port. The finite-difference time-domain (FDTD) method is utilized to obtain the optical spectrum of the proposed structures. To realize all-optical logic gate properties of the designed structures, optical signals with the same phase or different phases are passed through the waveguides. Transmission spectrum (T), contrast ratio (CR), and modulation depth (MD) parameters are obtained to determine the performances of all-optical logic gates. To determine the logic 1 (ON) and logic 0 (OFF) states of the output ports, the threshold transmission value is accepted as 0.23 for all-optical logic gates. For the proposed designs, the highest transmission, contrast ratio, and modulation depth values are 217%, 6.75 dB, and 100%, respectively. The structure also supports a data rate of 24 Tb/s. The designed optical logic gates have valuable features for developing high-performance optical devices.

GaSe, a two-dimensional layered metal monochalcogenide, has recently attracted growing interest due to its unique electronic properties and potential technological applications. In this study, we investigate the oxidation mechanisms and properties of GaSe exposed to air for different durations, with the intensive use of Raman spectroscopy, combined with atomic force microscopy (AFM), photoluminescence (PL), and X-ray photoelectron spectroscopy (XPS). Raman analysis reveals the oxidation of GaSe, resulting in the formation of a thin layer comprising Ga₂Se₃, Ga₂O₃, and amorphous selenium. Utilizing these signatures, oxidation is then tracked. Raman spectroscopy reveals that GaSe layer becomes oxidized almost immediately after exposure to air. However, the oxidation is a self-limiting process, taking roughly 15 min to construct an 8 Å thick layer of Ga₂O₃. XPS analysis shows a good agreement with Raman analysis. The polarized Raman study suggests that the Ga₂Se₃ and Ga₂O₃ layers tend to reach an oriented structural state over time. In ambient conditions, the intensity of all Raman modes and the luminescence decreases, linked to reduction in GaSe thickness. By using various Raman excitation wavelengths, we highlight the depth-dependent oxidation dynamics in this 2D layered GaSe material.

This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si_0.75Ge_0.25 etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si_0.75Ge_0.25 or 10 nm Si_0.75Ge_0.25 boron doped (Si_0.75Ge_0.25:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH₄OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si_0.75Ge_0.25:B as an ESL considerably increases the selectivity of the last diluted NH₄OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si_0.75Ge_0.25 as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.

The development of Micro Electro Mechanical Systems (MEMS) flow sensor towards high level market applications generates various challenges, in particular also on the reliable functionality. With the advancement of reliability engineering technology, aging phenomenon of MEMS devices has been widely concerned. As a result, an aging evaluation method is essential. The accelerated aging testing (AAT) is the most widely used in traditional aging methods. However, its performance is limited by highly economic and time cost. In this paper, a novel aging effect model is proposed, in which a comprehensive approach that integrates AAT, lifetime distribution modeling, and either Finite Element Modeling Simulation (FEMS) or fatigue simulation (FS) as fundamental is explored. However, the difference from the conventional approach was that the AAT results is imported in FS, to confirm fatigue analysis, while FS predictions are instrumental in analyzing degradation or fatigue phenomena and estimation lifetime. In this way, aging performance is illustrated detailed with the lower aging cost and high efficiency. Meanwhile, the results of proposed FS are verified by a thermal cycle (TC) AAT. Specifically, the resistor degradation mechanism, the characteristic parameter degradation is calculated. Moreover, the lifetime evaluation was acquired by the Arrhenius model. Finally, the proposed aging performance evaluation method can be applied to both discrete devices and modules. Compared with the traditional aging method the high aging cost can be eliminated, and the proposed aging evaluation strategy can be used in various temperature conditions.