Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562684
K. Castellani-Coulié, M. Bocquet, H. Aziza, J. Portal, W. Rahajandraibe, C. Muller
As emerging non-volatile memories, based on resistive switching mechanisms, are attractive candidates to overcome future power issues, this paper proposes to analyze Single Event Effects in circuitry surrounding OxRRAMs. The impact of a particle crossing the circuit is presented. A threshold effect is pointed out even if the probability of SEE occurrence is shown to be low in common technologies.
{"title":"SPICE level analysis of Single Event Effects in an OxRRAM cell","authors":"K. Castellani-Coulié, M. Bocquet, H. Aziza, J. Portal, W. Rahajandraibe, C. Muller","doi":"10.1109/LATW.2013.6562684","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562684","url":null,"abstract":"As emerging non-volatile memories, based on resistive switching mechanisms, are attractive candidates to overcome future power issues, this paper proposes to analyze Single Event Effects in circuitry surrounding OxRRAMs. The impact of a particle crossing the circuit is presented. A threshold effect is pointed out even if the probability of SEE occurrence is shown to be low in common technologies.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562656
R. Ubar
The complexity of digital systems is constantly growing. This has resulted in an increasing trend in design errors and manufacturing faults in modern VLSI systems. As the result, verification and test will continue to dominate as crucial factors in time-to-market, reliability, and cost of VLSI systems.
{"title":"Diagnostic modeling of digital systems with low- and high-level decision diagrams","authors":"R. Ubar","doi":"10.1109/LATW.2013.6562656","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562656","url":null,"abstract":"The complexity of digital systems is constantly growing. This has resulted in an increasing trend in design errors and manufacturing faults in modern VLSI systems. As the result, verification and test will continue to dominate as crucial factors in time-to-market, reliability, and cost of VLSI systems.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562668
P. Petrashin, C. Dualibe, W. Lancioni, L. Toledo
This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.
{"title":"Low-cost DC BIST for analog circuits: A case study","authors":"P. Petrashin, C. Dualibe, W. Lancioni, L. Toledo","doi":"10.1109/LATW.2013.6562668","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562668","url":null,"abstract":"This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"684 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121702861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562682
S. Sondon, Alfredo Falcon, P. Mandolesi, P. Julián, N. Vega, F. Nesprias, J. Davidson, F. Palumbo, M. Debray
Testing of single event effects caused by heavy ions in a PLL implemented on a CMOS 90 nm technology is reported in this work. The diagnosis of the circuit vulnerability has been conducted with a heavy ion micro beam line facility at the TANDAR tandem accelerator facility. The accuracy of the positioning system has been evaluated and the radiation dose has been accurately characterized. Single event effects were induced in the circuit and a map of the spatial correlation for the most sensitive blocks has been obtained.
{"title":"Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeam","authors":"S. Sondon, Alfredo Falcon, P. Mandolesi, P. Julián, N. Vega, F. Nesprias, J. Davidson, F. Palumbo, M. Debray","doi":"10.1109/LATW.2013.6562682","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562682","url":null,"abstract":"Testing of single event effects caused by heavy ions in a PLL implemented on a CMOS 90 nm technology is reported in this work. The diagnosis of the circuit vulnerability has been conducted with a heavy ion micro beam line facility at the TANDAR tandem accelerator facility. The accuracy of the positioning system has been evaluated and the radiation dose has been accurately characterized. Single event effects were induced in the circuit and a map of the spatial correlation for the most sensitive blocks has been obtained.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131744659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562659
E. Chielle, J. Azambuja, Raul S. Barth, F. Kastensmidt
This paper presents an analysis of the impact of selective software-based techniques to detect faults in microprocessor systems. A set of algorithms is implemented, compiled to a microprocessor and selected variables of the code are hardened with software-based techniques. Seven different methods that choose which variables are hardened are introduced and compared. The system is implemented over a miniMIPS microprocessor and a fault injection campaign is performed in order to verify the feasibility and effectiveness of each selective fault tolerance approach. Results can lead designers to choose more wisely which variables of the code should be hardened considering detection rates and hardening overheads.
{"title":"Improving error detection with selective redundancy in software-based techniques","authors":"E. Chielle, J. Azambuja, Raul S. Barth, F. Kastensmidt","doi":"10.1109/LATW.2013.6562659","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562659","url":null,"abstract":"This paper presents an analysis of the impact of selective software-based techniques to detect faults in microprocessor systems. A set of algorithms is implemented, compiled to a microprocessor and selected variables of the code are hardened with software-based techniques. Seven different methods that choose which variables are hardened are introduced and compared. The system is implemented over a miniMIPS microprocessor and a fault injection campaign is performed in order to verify the feasibility and effectiveness of each selective fault tolerance approach. Results can lead designers to choose more wisely which variables of the code should be hardened considering detection rates and hardening overheads.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121589546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562688
F. Lavratti, L. Bolzani, A. Calimera, F. Vargas, E. Macii
Technology scaling has made possible the integration of millions of transistors into a small area. The consequent increase of memory's density generated new types of defects during the manufacturing process that have become important concerns for the testing of Nano-Scale Static Random Access Memories (SRAMs). The rapidly increasing need to store more information results in the fact that the memory elements occupy great part of the Systemon-Chip's (SoC) silicon area. In this context, a technique based on On-Chip Current Sensors (OCCS) and Neighbourhood Comparison Logic (NCL) to detect resistive-open defects in SRAMs is proposed. The main idea behind the hardware-based technique is to explore the evaluation throughout an analysis of the current of neighbouring SRAM cells in order to identify the presence of manufacturing defects. Experimental results obtained throughout simulations demonstrate the technique's efficiency. Finally, an analysis of the overheads makes possible the comparison with today's standard techniques.
{"title":"Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs","authors":"F. Lavratti, L. Bolzani, A. Calimera, F. Vargas, E. Macii","doi":"10.1109/LATW.2013.6562688","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562688","url":null,"abstract":"Technology scaling has made possible the integration of millions of transistors into a small area. The consequent increase of memory's density generated new types of defects during the manufacturing process that have become important concerns for the testing of Nano-Scale Static Random Access Memories (SRAMs). The rapidly increasing need to store more information results in the fact that the memory elements occupy great part of the Systemon-Chip's (SoC) silicon area. In this context, a technique based on On-Chip Current Sensors (OCCS) and Neighbourhood Comparison Logic (NCL) to detect resistive-open defects in SRAMs is proposed. The main idea behind the hardware-based technique is to explore the evaluation throughout an analysis of the current of neighbouring SRAM cells in order to identify the presence of manufacturing defects. Experimental results obtained throughout simulations demonstrate the technique's efficiency. Finally, an analysis of the overheads makes possible the comparison with today's standard techniques.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121787423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562674
S. Miryala, A. Calimera, E. Macii, M. Poncino, L. Bolzani
Graphene, one of the viable candidates to replace Silicon in the next generation electronic devices, is pushing the research community to find new technological solutions that can exploit its special characteristics. Among the proposed approaches, the electrostatic doping represents a key option. It allows the implementation of equivalent pn-junctions through which is possible to build a new class of reconfigurable logic gates, the devices analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22nm. This work explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, has been analyzed and mapped at a higher level of abstraction using proper fault models. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.
{"title":"Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices","authors":"S. Miryala, A. Calimera, E. Macii, M. Poncino, L. Bolzani","doi":"10.1109/LATW.2013.6562674","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562674","url":null,"abstract":"Graphene, one of the viable candidates to replace Silicon in the next generation electronic devices, is pushing the research community to find new technological solutions that can exploit its special characteristics. Among the proposed approaches, the electrostatic doping represents a key option. It allows the implementation of equivalent pn-junctions through which is possible to build a new class of reconfigurable logic gates, the devices analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22nm. This work explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, has been analyzed and mapped at a higher level of abstraction using proper fault models. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132000811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562657
M. Aparicio, M. Comte, F. Azaïs, M. Renovell, Jie Jiang, I. Polian, B. Becker
This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
{"title":"Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays","authors":"M. Aparicio, M. Comte, F. Azaïs, M. Renovell, Jie Jiang, I. Polian, B. Becker","doi":"10.1109/LATW.2013.6562657","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562657","url":null,"abstract":"This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123766072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562686
W. Rahajandraibe, F. Haddad, H. Aziza, K. Castellani-Coulié, J. Portal
This paper presents a built-in tuning technique of local oscillator part of radiofrequency (RF) transceiver using onchip temperature sensor and process monitoring in order to cancel the process, voltage and temperature (PVT) drift of the modulating frequency. An auto-calibration of the VCO, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency of operation and results in low-cost, low power solutions.
{"title":"Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver","authors":"W. Rahajandraibe, F. Haddad, H. Aziza, K. Castellani-Coulié, J. Portal","doi":"10.1109/LATW.2013.6562686","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562686","url":null,"abstract":"This paper presents a built-in tuning technique of local oscillator part of radiofrequency (RF) transceiver using onchip temperature sensor and process monitoring in order to cancel the process, voltage and temperature (PVT) drift of the modulating frequency. An auto-calibration of the VCO, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency of operation and results in low-cost, low power solutions.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133575244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-03DOI: 10.1109/LATW.2013.6562661
Arwa Ben Dhia, L. Naviner, Philippe Matherat
This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.
{"title":"Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs","authors":"Arwa Ben Dhia, L. Naviner, Philippe Matherat","doi":"10.1109/LATW.2013.6562661","DOIUrl":"https://doi.org/10.1109/LATW.2013.6562661","url":null,"abstract":"This paper first introduces three new architectures of a voter for a Butterfly CLB in an SRAM-based FPGA. Taking into account area and delay constraints, an optimized voter architecture is picked up for the Butterfly design. Another version for the latter is also proposed in order to reduce the area overhead. Afterward, we synthesize different CLB fabless architectures in STM 65nm CMOS technology and evaluate their fault tolerance and reliability, so as to obtain an overview of the current state of the art. Finally, we compare the CLB architectures with respect to the conventional one by defining a metric expressing the tradeoff between the fault tolerance gain, the performance degradation and the cost penalties including area, power and SRAM memory.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126230238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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